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The main objective was to reduce front-to back run-out-error and minimize wafer bow. We focused on: - DRIE recipe optimization - Gas flows - Etch timing - Power changes - Test of different substrates - Pyrex - Sapphire - Test of wafer adhesives
This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.
There is a need envisioned to investigate the application of commercial off-the-shelf (COTS) systems as tools that could be used within commercial preliminary curation as the expected space economy is supported and begins to take flight. NASA is involved with supporting and developing the space economy [1] and therefore it’s feasible that at some point, a commercial space company would bring back materials and either store initially, or permanently, within COTS equipment as a stand-in for custom curation laboratories. While utilizing opportunities to explore this capability at NASA-Johnson Space Center (JSC) during the establishment of other laboratories [2] it was realized that cleanliness and/or other properties could be evaluated for these COTS systems during their installation in advanced research facilities that are not ISO-class rated clean rooms. Several aspects of a COTS-Curation system were explored including various gloves for curation manipulation within a negative pressure glovebox (Fig.1), Balazs organic and inorganic contaminant levels testing prior to glovebox ever being used, mode swapping comparison of recirculation vs. single pass, constant monitoring of oxygen (O2) and moisture (H2O) levels in various conditions, etc. To acquire inorganic and organic compound loads inside the glovebox, Balazs wafer testing and gas sampling were implemented. These are standardized analytical tests provided by Balazs™ NanoAnalysis, a division of Air Liquide USA. Deployment of 8-inch silicon wafer witness plates for 24-hours in an undisturbed environment capture the organic compound load and inorganic trace metal contents which can be obtained by Vapor Phase Decomposition Inductively Coupled Plasma Mass Spectrometry (VPD ICP-MS). Balazs gas sample analysis was also performed for better measurements of volatile organic compounds (VOC) in glovebox air analyzed by Thermal Desorption Gas Chromatography Mass Spectrometry (TD GC-MS). These analytical testings were carried out in a controlled ultra high pure (UHP) gaseous nitrogen (N2)-purged environment where oxygen and moisture contents were continuously monitored at certain temperature and pressure. The preliminary outcomes of these testings are promising. The COTS systems appear to maintain the steady-state controlled environment for days, if not weeks, with uninterrupted gaseous N2-supply which was operated from a standard medium pressure LN2 250L 230L dewar, exchanged as needed. The outgassing load can be maintained by selecting the glove materials that have the least outgassing and particle shedding performances. Further experiments will be considered to validate the preliminary findings. While this project is exploratory, it is not intended as an endorsement by NASA Curation for approved materials or usage for advanced curatorial activities. NASA does not endorse nor promote any one particular product or company. References: [1] McCubbin F. M. et al. (2019) Space Science Reviews 215:A48. [2] Lewis, E.K. et. al (2024) LPSC LV, Abstract #2457.
More than 30% of electrical energy passes through power electronics today with speculation that in the next decade this could grow to 80%. The wide bandgap semiconductor market is already approaching $1 billon USD in 2019 and is projected to be almost $7 billion USD in 2028. Even with its high cost, SiC, is starting to dislodge the incumbent Si technology in some applications, such as hybrid and electric vehicles, due to smaller size, and higher efficiency. We review and report the IHS Markit’s market predictions for wide bandgap semiconductor technologies, and highlight the techno-economic analysis results for the manufacturing cost of Ga2O3 wafers. Specifically, we focus on the potential for Ga2O3 to be more economically advantageous than SiC using current manufacturing methods and then identify opportunities where research can further reduce the volume cost of Ga2O3 wafers.
A method for fabricating a neutron detector includes providing an epilayer wafer of Boron-10 enriched hexagonal boron nitride (h-10BN or h-BN or 10BN or BN) having a thickness (t), dicing or cutting the epilayer wafer into one or more BN strips having a width (W) and a length (L), and depositing a first metal contact on a first surface of at least one of the BN strip and a second metal contact on a second surface of the at least one BN strip. The neutron detector includes an electrically insulating submount, a BN epilayer of Boron-10 enriched hexagonal boron nitride (h-10BN or h-BN or 10BN or BN) placed on the insulating submount, a first metal contact deposited on a first surface of the BN epilayer, and a second metal contact deposited on a second surface of the BN epilayer.
The present invention relates to a method of fabricating an electrode array, in which an underlying handle wafer is removed to provide a planar device having the electrode array. Also provided are wafers including a plurality of planar devices having an electrode array, as well as sensors including such an electrode array.
A method for fabricating a neutron detector includes providing an epilayer wafer of Boron-10 enriched hexagonal boron nitride (h- 10 BN or h-BN or 10 BN or BN) having a thickness (t), dicing or cutting the epilayer wafer into one or more BN strips having a width (W) and a length (L), and depositing a first metal contact on a first surface of at least one of the BN strip and a second metal contact on a second surface of the at least one BN strip. The neutron detector includes an electrically insulating submount, a BN epilayer of Boron-10 enriched hexagonal boron nitride (h- 10 BN or h-BN or 10 BN or BN) placed on the insulating submount, a first metal contact deposited on a first surface of the BN epilayer, and a second metal contact deposited on a second surface of the BN epilayer.
This contribution explores a low-temperature route to forming dielectric pinholes to form poly-Si/dielectric/c-Si passivated contacts. The method utilizes controlled dielectric breakdown to form nanoscale pinholes in a thick (non-tunnelling) dielectric which, when annealed, allows dopant atoms to pass from doped poly-Si through the dielectric and into the c-Si wafer forming conductive pathways. We show that the pinholes can be repassivated with dopants and H diffusion which results in increased PL signals after processing. The method can be expanded to optimized dielectric passivation stacks (not just a single layer) and can be formed in parallel over the faces of the wafer in selected areas (only under the grid).
The demand for sensors in hostile environments, such as power plant environments, aerospace environments, oil and gas extraction, and high-temperature metallurgy environments, has risen over the past decades in a continuous attempt to increase process control, improve energy and process efficiency in production, reduce operational and maintenance costs, increase safety, and perform condition-based maintenance in equipment and structures operating in high-temperature harsh-environment conditions. The increased reliability, improved performance, and development of new sensors and networks with a multitude of components, especially wireless networks, are the target for operation in harsh environments. Gas sensors, in particular H2 sensors, operating above 200 C are required in the instrumentation, process control and general safety of a number of industries including coal, natural gas, and nuclear power generation facilities, the aerospace and automotive industries, metallurgical production and defense-related applications. The surface acoustic wave (SAW) platform is a particularly promising option for high-temperature, harsh-environment gas sensing applications since the platform exhibits advantages, such as battery-free and wireless operation, small size, possibility for scale production using well-developed technologies from the semiconductor industry, and low cost of installation and operation. In this work, one-port SAW resonators (SAWRs) operating along five different orientations on a commercially available langasite (LGS) wafer employing Pt-Al2O3 electrodes and reflectors were designed, fabricated, and used as high-temperature H2 sensors. Two of the selected orientations were predicted and confirmed to have temperature-compensated operation above 150 C. A gas sensor test setup was developed, capable of gas cycling between N2, O2 and N2/H2 mixtures under extended high-temperature periods (up to 650 C for over 20 hours). Thin film Pt-Al2O3 was used as the electrode material for the transducers and reflectors capable of high-temperature operation, and also as H2 sensing film. In addition, yttria-stabilized zirconia (YSZ) thin films with Pt decoration were tested as sensing films aimed to enhance the SAWR sensor response to H2. The SAW devices were monitored in excess of 1700 hours in real-time during gas cycling sequences up to 600 C, leading to the following findings: i) the Pt-Al2O3 electrodes performed better for H2 sensing than the Pt-decorated YSZ sensing film, showing as much as 50% higher frequency variation response in the 200 C to 400 C range; ii) different crystallographic orientations operating on the same LGS wafer experienced different responses to H2 exposures up to 500 C; iii) the surface oxidation state of the SAWR sensors was shown to have an important impact on subsequent H2 exposure responses. In addition, a sensor system employing two LGS SAWRs, aligned along two different orientations, has been developed to simultaneously determine H2 presence and temperature. Finally, wireless interrogation of a SAWR sensor was successful within the gas cycling test fixture, and successful wireless H2 detection was achieved above 400 C.
In recent years, better understanding and control over the formation of crystalline defects during the direct epitaxy of III-V semiconductors on Si substrates via metal organic vapor phase epitaxy (MOVPE) has enabled large gains in III-V-on-Si solar cell efficiency, pointing to pathway to lower-cost, high-performance III-V solar cells. However, such results have only been achieved on costly chemo-mechanically-polished (CMP) Si wafers. The use of V-groove nanopatterned Si substrates has demonstrated similarly high-crystalline-quality III-V-on-Si epitaxy, but also can be combined with lower-cost polishing techniques. Although they offer a potential cost advantage, growth on V-groove substrates adds challenges not present for epitaxy on planar wafers (the III-V material must be coalesced into a thin film after an initial nucleation stage). MOVPE growth conditions that promote highly facet-selective lateral growth needed for coalescence are generally actively avoided for conventional thin fim growth, so growth conditions need to be re-developed for V-groove-based epitaxy. Additionally, coalescence add complexity to the dislocation dynamics related to lattice relaxation, so strategies used to keep threading dislocation density (TDD) low on planar substrates need to be re-tuned for V-grooves. We have studied the morphological evolution and dislocation dynamics of GaP grown on V-groove Si by MOVPE. Growth conditions of V/III=5,000 and Tg=800 degrees C were uniquely found to produce extremely smooth coalesced thin films, with an RMS roughness of 0.2 nm measured by AFM. Additionally, at this growth condition, we identified two regimes of growth determined by the width of the SiNx cap (a remnant of the nanopatterning process) at the top of the V-grooves. For narrow caps, the GaP coalesces into a thin film, and for wide caps, the GaP evolves into {1 1 1}-faceted diamonds that do not coalesce. We suggest the influence of Si from the sidewalls of the V-grooves on the surface reconstruction of the GaP as the mechanism for this effect, with reflection difference spectroscopy (RDS) and Si doping experiments supporting this theory. In addition to morphology, the dislocation dynamics of the system were studied with electron channeling contrast imaging (ECCI) and transmission electron microscopy (TEM). The TDD of the coalesced GaP films was found to be 5 x 10^7 cm^-2 after coalescence via ECCI, a level still too high for high-quality solar cells. However, misfit dislocations crossing multiple grooves greater than 20 micrometers long were observed in ECCI, suggesting that the V-grooves do not block dislocation glide. TEM prior to and after coalescence was used to distinguish between dislocation creation driven by growth conditions and coalescence. Finally, strategies to reduce the dislocation density to levels acceptable for solar cells will be discussed.
Semiconductor manufacturing is a highly complex. Fabrication plants must deal with re-entrant flows to support multiple types of wafers being produced simultaneously, each with their own deadlines and specifications. The manufacturing process itself depends upon the ability to control and programmatically adjust a variety of environmental conditions including temperature, humidity, and air quality. In addition, wafer fabrication consumes large amounts of electricity. Emerging technologies may help reduce the energy footprint of such facilities but can introduce cybersecurity risks. Therefore, this paper presents a modeling and simulation framework to quantify tradeoffs between operational measures of performance, energy consumption, and cybersecurity controls. We augment the Intel Minifab model, with the Purdue Enterprise Reference Architecture (PERA) for cybersecurity as well as tool-level energy consumption data from a real-world semiconductor manufacturing testbed. In this manner, we intend to provide stakeholders with a systematic, data-driven approach to evaluate emerging risks within the manufacturing process.
With an increase of control over crystalline defects, metallorganic vapor phase epitaxy (MOVPE)-grown III-V-on-Si multijunction solar cells have seen rapid increases in efficiency in recent years, pointing to a promising path to lower cost III-V solar cells. However, the cost of chemo-mechanical polishing the Si wafers to prepare them for epitaxy is high. The use of V-groove nanopatterns enables similar defect reduction to that achieved on planar wafers, but the nanopatterns can be fabricated with a low-cost process. While V-grooves offer advantages over planar Si, they add complexity to the growth process. In particular, coalescence can cause the formation of threading dislocations, and the highly-directional growth conditions required for coalescence are unusual for MOVPE. We have studied the coalescence of GaP films nucleated directly on V-groove Si by MOVPE. We observed that for optimized growth conditions (V/III=5,000 and T=800 C) two growth modes were possible, and the resulting morphology depended on the exact geometry of the SiNx cap used to cover the (0 0 1)-oriented Si at the tops of the grooves. For caps with a width >100 nm, noncoalescing, nano ridge-like growth terminating in f1 1 1g facets was observed. For narrower caps, coalescence with an RMS roughness of 0.2 nm as measured by atomic force microscopy was observed. We will discuss mechanisms responsible for this phenomenon, including the role of Si from the substrate surface. The dislocation dynamics of this system were studied with electron channeling contrast imaging (ECCI) and transmission electron microscopy (TEM). We find that V-grooves do not block dislocation glide; ECCI measurements show misfit dislocations greater than 10 micrometers long observed to continue perpendicularly across neighboring V-grooves. In addition, all threading dislocations appear to lie on f1 1 1g planes, consistent with the GaP relaxing via glided-in glissile dislocations. The dislocation dynamics and morphological evolution of the coalescence of GaP on Si, possible mechanisms behind the observed phenomenons, and further dislocation mitigation strategies for these materials will be presented.
The present invention relates to methods of delayering a semiconductor integrated circuit die or wafer. In at least one aspect, the method includes exposing a die or wafer to plasma of an etching gas and detecting exposure of one or more metal layers within the die. In one aspect of the invention, the plasma of the etching gas is non-selective and removes all materials in a layer at about the same rate. In another aspect of the invention, two different plasmas of corresponding etching gases are employed with each plasma of the etching gas being selective, thus necessitating the sequential use of both plasmas of corresponding etching gases to remove all materials in a layer.
A hybrid photonic integrated circuit and a method of its manufacture are provided. A SiP functional layer is fabricated on an SOI wafer. A lithium niobate thin film is bonded to the SiP functional layer. The silicon handle layer is removed from the SOI wafer to expose buried oxide, and at least one III-V die is bonded to the exposed buried oxide. In embodiments, at least one waveguiding component is fabricated in the SiP functional layer. In embodiments, the SiP functional layer comprises a top waveguiding layer.
A method is provided for making gratings of gold or other metal in silicon substrates. The disclosed method may achieve high aspect ratios. According to the disclosed method, a silicon wafer is through-etched. A seed layer of metal is vapor-deposited on one side of the wafer, and a layer of metal is electrodeposited on the seed layer. The electrodeposited metal plugs the trenches and provides a conductive surface for subsequent electrodeposition. The trenches are then filled by electrodeposition from within the trenches, so that the walls of the metal grating grow on the metal plugs.
Controlled spalling is a technology to prepare single-crystal thin films of semiconductors by fracture with a subsurface crack propagating nearly parallel to the substrate surface. Practical applications require uniform thickness and a smooth surface across the whole film. Both wafer-scale and patterned-stressor-defined small-area spalling of germanium substrates are conducted experimentally and numerically. River line features are observed on spalled surfaces close to lateral edges of the spall, regardless of the spall direction and the size of the spalled area. Three-dimensional finite element method modeling shows the river lines are caused by mixed mode I?+?III loading near the lateral edges of spall and predicts a spall depth variation near the lateral edges of spall due to mixed mode I?+?II loading. The absolute range of river lines increases with lateral size of spall, while the relative range of river lines decreases, consistent with variations in mode mixity.
Bifacial technology enables solar cells to offer higher power output and lower levelized cost of energy compared to their monofacial counterparts. Here, we examined the adverse effects of ultraviolet-induced degradation (UVID) on a variety of high-efficiency silicon wafer-based bifacial cell technologies, including silicon heterojunction (SHJ), interdigitated back contact (IBC), passivated emitter rear contact (PERC), and passivated emitter rear totally-diffused (PERT). Both the front and rear sides of bifacial cells without any encapsulation were exposed to an artificially accelerated UV exposure test. After 2000 h of UV irradiation, the bifacial cells exhibited greater power loss with backside exposure indicating potential sensitivity of the rear passivation to UV. The highest power degradation is observed in SHJ cells, followed by p-PERC and n-PERT cell technologies. The degradation in SHJ cells is attributed to the reduction in V oc and FF, while the degradation in p-PERC and n-PERT cells is correlated with a significant drop in I sc . This suggests that each cell type/make degrades via different degradation pathways.
This work expands upon previous research related to transfer printed virtual substrates: a technique for generating low-cost engineered substrates that is not based on wafer reuse. Here, silicon and sapphire are evaluated as candidate low-cost handle materials, validated by metal organic chemical vapor deposition regrowth of GaAs single-junction solar cells. Resulting devices are studied via materials and electrical characterization techniques, including concentration measurements that indicate GaAs//sapphire TPVS open-circuit voltage at >10 suns comparable with identical devices grown on a prime GaAs substrate.