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Silicon transistor, developed for use in biotelemetry circuits, provides high current gain at low levels of power and voltage. Device operates from biopotential or miniature batteries and is suitable for incorporation into monolithic integrated circuits. Coaxial configuration and small size offer promise for high frequency application.
Large-scale integrated circuit generates and checks parity of four eight-bit registers. In addition, circuit will indicate by output signal whether parity error exists. Circuit can also generate or check parity of words up to 32 bits. This is done by making appropriate internal wiring connections on the large-scale integrated chip.
The potential for interference between solar power satellites (SPS) and other Earth satellite operations was examined along with interference problems involving specific electronic devices. Conclusions indicate that interference is likely in the 2500 MHz to 2690 MHz direct broadcast satellite band adjacent to SPS. Estimates of the adjacent channel noise from SPS in this band are as high as -124 dBc/4 kHz and -100 dBc/MHz, where dBc represents decibels relative to the total power in the fundamental. A second potential problem is the 7350 MHz, 3d harmonic from SPS that falls within the 7300 MHz to 7450 MHz space to Earth, government, satellite assignment. Catastrophic failures can be produced in integrated circuits when the microwave power levels coupled into inputs and power leads reach 1 to 100 watts. The failures are typically due to bonding wire melting, metallization failures, and junction shorting. Nondestructive interaction or interference, however, generally occurs with coupled power levels of the order of 10 milliwatts. This integration is due to the rectification of microwave energy by the numerous pn junctions within these circuits.
MEMS have shown a significant promise in the last decade for a variety of applications such as air-bag, pressure sensors, accelerometer, microgyro, chemical sensors, artificial nose, etc. Standard semiconductor microelectronics packaging needs the integrated circuits (IC) to be protected from the harsh environment, and provide electrical communication with the other parts of the circuit, facilitate thermal dissipation efficiently, and impart mechanical strength to the silicon die. Microelectronics packaging involves wafer dicing, bonding, lead attachment, encapsulation to protect from the environment, electrical integrity, and package leak tests to assure the reliable IC packaging technology. Active elements or microstructures in MEMS devices often interfaces with the hostile environment where packaging leak tests and testing of such devices using chemical and mechanical parameters will be very difficult and expensive. Packaging of MEMS is significantly complex as they serve to protect from the environment and microstructures interact with the same environment to measure or affect the desired physical or chemical parameters. The most of the silicon circuitry is sensitive to temperature, moisture, magnetic field, light, and electromagnetic interference. The package must then protect the on-board silicon circuitry while simultaneously exposing the microsensor to the effect it measures to assure the packaging technology of MEMS. MEMS technology has a major application in developing a microspacecraft for space systems provided reliability of MEMS packaging technology is sufficiently addressed. This MEMS technology would eventually miniaturize many of the components of the spacecraft to reach the NASA's goal by building faster, cheaper, better, smaller spacecraft to explore the space more effectively. This paper discusses the latest developments in the MEMS technology and challenging technical issues in the packaging of hermetically sealed and non-hermetically sealed MEMS sensor devices for microspacecraft applications.
Microelectromechanical systems (MEMS) have shown a significant promise in the last decade for a variety of applications such as air-bag, pressure sensors, accelerometer, microgyro, etc. Standard semiconductor microelectronics packaging needs the integrated circuits to be protected from the harsh environment, and provide electrical communication with the other parts of the circuit, facilitate thermal dissipation efficiently, and impart mechanical strength to the silicon die. Microelectronics packaging involves wafer dicing, bonding, lead attachment, encapsulation to protect from the environment, electrical integrity, and package leak tests to assure the packaging technology. In the case of MEMS the microstructures (active elements) often interfaces with the hostile environment where packaging leak tests and testing of such devices using chemical and mechanical parameters will be very difficult and expensive. Packaging of MEMS is significantly complex as they serve to protect from the environment and microstructures interact with the same environment to measure or affect the desired physical or chemical parameters. The most of the silicon circuitry is sensitive to temperature, moisture, magnetic field, light, and electromagnetic interference. The package must then protect the on-board silicon circuitry while simultaneously exposing the microsensor to the effect it 'measures to assure the MEMS technology by lowering the risk to zero. MEMS technology has a major application in developing a microspacecraft for space systems provided assurance of MEMS technology is sufficiently addressed nondestructively. This technology would eventually miniaturize many of the components of the spacecraft to reach the NASA's safety and mission assurance goal by building faster, cheaper, better, smaller spacecraft to explore the space more effectively by teaming-up with the other NASA centers using the limited resources available. This paper discusses the latest developments in the MEMS technology and challenging issues in the packaging of hermetically sealed and non-hermetically sealed MEMS sensor devices based on silicon, poly-silicon, and other materials for microspacecraft applications considering the space environment and reliability assurance qualification guidelines in perspective. Acknowledgments: The above research work is supported by the NASA Electronics Parts and Packaging Program (NEPP) and performed by the Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA under a contract with the NASA - Code Q for the Office of Safety and Mission Assurance Program 323-79.
A proposed integrated circuit based on quantum-dot cellular automata (QCA) would function as a bit-serial adder. This circuit would serve as a prototype building block for demonstrating the feasibility of quantum-dots computing and for the further development of increasingly complex and increasingly capable quantum-dots computing circuits. QCA-based bit-serial adders would be especially useful in that they would enable the development of highly parallel and systolic processors for implementing fast Fourier, cosine, Hartley, and wavelet transforms. The proposed circuit would complement the QCA-based circuits described in "Implementing Permutation Matrices by Use of Quantum Dots" (NPO-20801), NASA Tech Briefs, Vol. 25, No. 10 (October 2001), page 42 and "Compact Interconnection Networks Based on Quantum Dots" (NPO-20855), which appears elsewhere in this issue. Those articles described the limitations of very-large-scale-integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCA-based signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes. To enable a meaningful description of the proposed bit-serial adder, it is necessary to further recapitulate the description of a quantum-dot cellular automation from the first-mentioned prior article: A quantum-dot cellular automaton contains four quantum dots positioned at the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantum-mechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Again, for reasons too complex to describe here, in order to ensure accuracy and timeliness of the output of a QCA array, it is necessary to resort to an adiabatic switching scheme in which the QCA array is divided into subarrays, each controlled by a different phase of a multiphase clock signal. In this scheme, each subarray is given time to perform its computation, then its state is frozen by raising its inter-dot potential barriers and its output is fed as the input to the successor subarray. The successor subarray is kept in an unpolarized state so it does not influence the calculation of preceding subarray. Such a clocking scheme is consistent with pipeline computation in the sense that each different subarray can perform a different part of an overall computation. In other words, QCA arrays are inherently suitable for pipeline and, moreover, systolic computations. This sequential or pipeline aspect of QCA would be utilized in the proposed bit-serial adders.
The application of analog signal to discrete interval converter (ASDTIC), a hybrid micromodule, two loop control subsystem, to a switching, stepdown dc to dc converter is described. The power circuitry, interface and ASDTIC subsystems used in this switching regulator were developed to exhibit the improved regulation, transient performance, regulator stability and freedom from the effects of variations in parts characteristics due to environmental changes and aging. ASDTIC can be used with other types of power circuits that use duty-cycle control techniques by simple changes in the interface subsystem. The circuitry and performance characteristics of a +10V dc switching converter as well as that of the ASDTIC micromodule are described. Realization of the ASDTIC hybrid micromodule has been accomplished with a hermetically sealed, beam-lead, bonded/deposited nichrome thin film resistors, discrete capacitors and integrated circuits on dilithic, glazed alumina substrates using 22 feed through terminals in an integrated package.
Miniature, totally implantable, solid state RF-controlled switching circuit for biotelemetry systems consumes zero power in off condition and turns on or off by pulse of RF energy. Switch, the size of small coin, is reducible by integrated circuit techniques.
Ultra-high-purity silicon required for solar cells, transistors and integrated circuits can be produced from metallurgical grade silicon by formation and pyrolysis of silane gas in continuous-flow process that maximizes product purity with minimum amount of equipment. Integrated process recycles unreacted and byproduct materials, minimizing material losses and simplifying waste disposal. Ensures effective removal of impurities, including boron.
The use of new design methodologies to continue the evolution of telemetry data systems to higher levels of integration is discussed. In particular, hardware description languages and automated logic synthesis tools are used to create very dense Application Specific Integrated Circuits (ASICs) that generically implement telemetry processing functions. The use of the ASICs will make it possible to develop a new generation of functional components, each of the components integrating several telemetry processing subsystems into a single card.
Compact electronic circuit transfers dc power to, and preprocesses ac output of, accelerometer and associated preamplifier. Incorporated into accelerometer case during initial fabrication or retrofit onto commercial accelerometer. Made of commercial integrated circuits and other conventional components; made smaller by use of micrologic and surface-mount technology.
A radial probe transition between a monolithic microwave integrated circuit (MMIC) and a waveguide has been designed for operation at frequency of 340 GHz and to be fabricated as part of a monolithic unit that includes the MMIC. Integrated radial probe transitions like this one are expected to be essential components of future MMIC amplifiers operating at frequencies above 200 GHz. While MMIC amplifiers for this frequency range have not yet been widely used because they have only recently been developed, there are numerous potential applications for them-- especially in scientific instruments, test equipment, radar, and millimeter-wave imaging systems for detecting hidden weapons.
Circuit controls a voltage controlled oscillator from computer output binary data representing a rate at which the oscillator is to change. It operates with low level output devices such as integrated circuit registers and devices with somewhat variable output levels.
An adjustable planar imbedding circuit based on coplanar transmission lines is presented to deal with the impedance mismatch associated with the use of the Superconductor-Insulator-Superconductor tunnel junction. The planar embedding circuit is developed with movable noncontacting shorting elements that consist of thin metallic plates with optimized arrangements of rectangular holes. The rectangular holes are placed along the insulated metallic transmission line to provide a periodic variation of the line impedance. A large reflection coefficient is demonstrated with a scale model of the sliding backshort, and values of more than -0.5 dB are reported. The shorting elements are incorporated into a low-frequency tuning circuit to test the practical tuning ranges. The backshort can be used to fashion tuning stubs with variable post-fabrication electrical lengths which relaxes the design constraints of planar integrated circuits.
The NASA Small Explorer Data System (SEDS), a space flight data system developed to support the Small Explorer (SMEX) project, is addressed. The system was flown on the Solar Anomalous Magnetospheric Particle Explorer (SAMPEX) SMEX mission, and with reconfiguration for different requirements will fly on the X-ray Timing Explorer (XTE) and the Tropical Rainfall Measuring Mission (TRMM). SEDS is also foreseen for the Hubble repair mission. Its name was changed to Spacecraft Data System (SDS) in view of expansions. Objectives, SDS hardware, and software are described. Each SDS box contains two computers, data storage memory, uplink (command) reception circuitry, downlink (telemetry) encoding circuitry, Instrument Telemetry Controller (ITC), and spacecraft timing circuitry. The SDS communicates with other subsystems over the MIL-STD-1773 data bus. The SDS software uses a real time Operating System (OS) and the C language. The OS layer, communications and scheduling layer, application task layer, and diagnostic software, are described. Decisions on the use of advanced technologies, such as ASIC's (Application Specific Integrated Circuits) and fiber optics, led to technical improvements, such as lower power and weight, without increasing the risk associated with the data system. The result was a successful SAMPEX development, integration and test, and mission using SEDS, and the upgrading of that system to SDS for TRMM and XTE.
Power transistor is provided with an integral flat plate aluminum heat sink which mounts directly on a printed circuit board containing associated circuitry. Standoff spacers are used to attach the heat sink to the printed circuit board containing the remainder of the circuitry.
Laminanted copper and polyimide terminal strip makes it easy to modify printed-circuit (PC) board, after board has been fabricated. When epoxied over conductors or insulating portion of PC board, strip provides series of solder-coated copper conductor pads to which integrated-circuit leads are soldered for functional changes. Terminal strips accommodate leads on dual inline IC package or as staggered single or multiple leads on planar mounted flatpacks.
We are currently constructing the cryogenic infrared portion of the RATIR instrument at NASA's Goddard Space Flight Center (GSFC) in collaboration with University of California, Berkeley (UCB) and The University of Mexico (UNAM). The infrared instrument will consist of two 2048x2048 Hawaii 2RG detectors, one on axis and one off axis using diachronic. The detectors will be operated using state-of-the-art Teledyne SIDECAR (System Image, Digitizing, Enhancing, Controlling, And Retrieving) ASICs (Application- Specific Integrated Circuits) similar to NIRSpec on JWST. The visible portion of the instrument is currently being developed at UCB consisting of two CCD imagining cameras. Once completed, the two sections will be integrated into the RATIR instrument. Mounted on a dedicated, fully-automated 1.5-m telescope, the instrument will provide rapid (<10 min) identification of VHR GRBs allowing high-resolution spectroscopic follow-up observations with large aperture telescopes possible. The hosting Observatorio Astronomico Nacional of the Universidad Nacional Autonoma de Mexico (UNAM), located on the Sierra de San Pedro Martir in Baja California, Mexico, provides great seeing (-1 aresec), good weather, dark skies, and significant sky coverage so that RATIR will detect a significant number of Swift afterglows. While not all GRBs will be at high red shifts, the resulting light curves, combined with X-ray/UV observations, will address several open questions, including the nature of both "dark GRBs" and the GRB emission mechanism.