SEARCH · Engineering Papers
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Method calibrates transducer bridge curing unbalanced condition and line resistance errors are negligible. Series resistance method can be automated easily and controlled by 2-bit information source which provide 4 states for switches.
Phase-locked-loop (PLL) bit synchronizers often employ integrate-and-dump type phase detectors that provide phase error information only at discrete points in time. Usually these phase detectors are followed by sample-and-hold circuits to produce a stairstep error voltage as the input to a standard analog circuit loop filter. When the loop is configured in this manner, it is referred to as a hybrid PLL. Sampled-data analysis methods (Z transforms) are used to determine the stability and transient response of this loop.
This innovation is an efficient algorithm designed to perform bit-to-symbol and symbol-to-bit likelihood mappings that represent a significant portion of the complexity of an error-correction code decoder for high-order constellations. Recent implementation of the algorithm in hardware has yielded an 8- percent reduction in overall area relative to the prior design.
We report on the design, development, and testing of our high-power broadband optical modem supporting NASA’s crewed Artemis-2 mission. The O2O modem will be mounted in the crewed Orion module and provide a broadband 505,000 km bi-directional optical link back to earth while en route to the moon. The full-duplex modem consists of a high-power optical transmitter and receiver optimized for serially-concatenated pulse-position modulation (SCPPM). The transmitter is a master-oscillator power-amplifier optical architecture using efficient cladding-pumped amplification in erbium-ytterbium co-doped fiber. The transmitter outputs up to 1 W at ≈1550 nm (limited for eye safety) and supports 6 different user-rates ranging from 20.39 Mb/s to 260.95 Mb/s using PPM16 and PPM32 modulation formats. The optical receiver supports two user-rates: 10.19 Mb/s and 20.39 Mb/s with both rates employing PPM32. The narrowband receiver filtering is optimized to simultaneously accept four separate wavelength channels to mitigate atmospherics through spatial diversity. A configurable interleaver provides additional protection against atmospherics-based signal fading and a powerful soft-decision error correction scheme enables highly sensitive detection. The measured sensitivities at the two bit-rates are -73.8 and -71.8dBm, respectively. The architecture was designed for reliable operation in space, featuring automatic hardware interlocks, pump sparing for the amplifiers, and autonomous operation of all internal hardware and software control loops. The protoflight unit (PFU) was put through rigorous environmental testing which included pyroshock, vibration, electromagnetic interference/compatibility, and thermal-vacuum testing. The modem successfully passed all the environmental screening and has been declared at Technology Readiness Level (TRL) 6.
The authors report the final stage of a research project for the NASA mobile satellite experiment (MSAT-X). The work has resulted in two alternative coding techniques which have achieved good communications quality at 4.8 kb/s while tolerating vehicle noise, fading, and a fairly high-error-rate, bursty channel. The authors have constructed a circuit board based on three AT&T 32-bit floating-point DSP32 digital signal processors (DSP) and providing both excess processing power and considerable flexibility for handling different variations of the algorithms. A Motorola 68HC11 microcomputer chip serves as the board controller and interface handler. Mounted on a wirewrapped card, the prototype's circuit footprint amounts to only 225 cm2 and consumes about 13 W of power. A description is given of the architecture, signal processing and communication functions, circuitry, and firmware of the prototype. Issues such as synchronization, framing, error control, and modem interface are also addressed.
Multicast services needed for current distributed applications on LAN's fall generally into one of three categories: datagram, semi-reliable, and reliable. Transport layer multicast datagrams represent unreliable service in which the transmitting context 'fires and forgets'. XTP executes these semantics when the MULTI and NOERR mode bits are both set. Distributing sensor data and other applications in which application-level error recovery strategies are appropriate benefit from the efficiency in multidestination delivery offered by datagram service. Semi-reliable service refers to multicasting in which the control algorithms of the transport layer--error, flow, and rate control--are used in transferring the multicast distribution to the set of receiving contexts, the multicast group. The multicast defined in XTP provides semi-reliable service. Since, under a semi-reliable service, joining a multicast group means listening on the group address and entails no coordination with other members, a semi-reliable facility can be used for communication between a client and a server group as well as true peer-to-peer group communication. Resource location in a LAN is an important application domain. The term 'semi-reliable' refers to the fact that group membership changes go undetected. No attempt is made to assess the current membership of the group at any time--before, during, or after--the data transfer.
The ETROC2, the first full size and full functionality prototype chip for the CMS Endcap Timing Layer readout, is strategically designed to meet the SEE immunity requirements of detector operation with the low power constraint. The triplicated periphery and pixel I2C configuration registers are designed with self-correction feature. The pixel readout control is centralized in the global readout and fully triplicated. The pixel readout is not triplicated, instead protected with power-efficient one-bit correction Hamming code. The TMR protection of the on-pixel threshold calibration can be turned off allowing the detection of the beam spot during the beam test by checking the bit-flips of the internal memory cells. In the initial proton beam test in January 2024, the chip readout process did not hang throughout the tests. The Hamming code correction strategy works because the error corrected TDC data were observed in the data frames. The error-injection simulation is performed to analy ze the small number of bit-flips in the configuration registers. We also performed SEE testing with a heavy ion beam in April and the data analysis is ongoing. The detailed design on the SEE immunity and the testing as well as simulation results will be presented, including follow-up SEE testing results in May and June 2024.
In this work, we demonstrate SONOS (silicon-oxide-nitrideoxide- silicon) analog memory arrays that are optimized for neural network inference. The devices are fabricated in a 40nm process and operated in the subthreshold regime for in-memory matrix multiplication. Subthreshold operation enables low conductances to be implemented with low error, which matches the typical weight distribution of neural networks, which is heavily skewed toward near-zero values. This leads to high accuracy in the presence of programming errors and process variations. We simulate the end-to-end neural network inference accuracy, accounting for the measured programming error, read noise, and retention loss in a fabricated SONOS array. Evaluated on the ImageNet dataset using ResNet50, the accuracy using a SONOS system is within 2.16% of floating-point accuracy without any retraining. The unique error properties and high On/Off ratio of the SONOS device allow scaling to large arrays without bit slicing, and enable an inference architecture that achieves 20 TOPS/W on ResNet50, a >10× gain in energy efficiency over state-of-the-art digital and analog inference accelerators.
Noisy Intermediate-Scale Quantum (NISQ) computers consisting of tens of inherently noisy quantum bits (qubits) suffer from reliability problems. Qubits and their gates are susceptible to various types of errors. Due to limited numbers of qubits and high error rates, quantum error correction cannot be applied. Physical constraints of quantum hardware including the error rates are used to guide the design and the layout of quantum circuits. The error rates determine the selection of qubits and their operations. The resulting circuit is executed on the quantum computer. This study explores the risk of unexpected changes in the error rates of NISQ computers post-calibration. We show that unexpected changes in error rates can alter the output state of a quantum circuit. To detect these changes, we propose the insertion of test points into the quantum circuit to enable online monitoring of the physical qubit behavior. We utilize classical, superposition, and uncompute test points. Furthermore, we use a gate error coverage metric to assess the quality of the tests. We verify the effectiveness of the proposed scheme on different IBM quantum computers (IBM Q), in addition to a noisy simulation that shows the scalability of the proposed approach.
Fast Viterbi decoder with fully parallel, pipeline architecture implemented on two VLSI NMOS chips. Decoder used with constraint-length-7, rate-1/2, convolutional error-correcting code widely used by NASA for deepspace telemetry data. With this (7,1/2) code, bit stream contains 2 bits per original data bit, and information about 1 data bit distributed over 7 pairs of bits. Design principles of decoder also applicable to Viterbi codes of other lengths and rates.
We propose a superconducting qubit based on engineering the first and second harmonics of the Josephson energy and phase relation 𝐸 𝐽1 cos 𝜑 and 𝐸 𝐽2 cos 2𝜑. By constructing a circuit such that 𝐸 𝐽2 is negative and |𝐸 𝐽1 | ≪ |𝐸 𝐽2 |, we create a periodic potential with two nondegenerate minima. The qubit, which we dub “harmonium,” is formed from the lowest-energy states of each minimum. Bit-flip protection of the qubit arises due to the localization of each qubit state to their respective minima, while phase-flip protection can be understood by considering the circuit within the Born-Oppenheimer approximation. We demonstrate with time-domain simulations that single- and two-qubit gates can be performed in approximately 100 ns. Finally, we compute the qubit coherence times using numerical diagonalization of the complete circuit in conjunction with state-of-the-art noise models. We estimate out-of-manifold heating times on the order of milliseconds, which can be treated as erasure errors using conventional dispersive readout. We estimate pure-dephasing times on the order of many tens of milliseconds, and bit-flip times on the order of seconds.
The reflectarray antenna is a power-efficient antenna but with an inherent intersymbol interference (ISI) problem with digital modulations. The composite signal model of a reflectarray is established. The ISI is characterized by the signal components delays. The feed-to-element distance and the element-to-observation distance contribute to the total delay, with the latter having the major effect. The effect of typical phase shifters' phase errors is analyzed and evaluated. Simulations are performed. The analytical and simulation results for an example reflectarray at f(sub c) = 26.5 GHz and bit rate of 1.325 Gbps show that the BER degradation due to ISI is proportional to the symbol rate and the loss ranges from less than 1 dB to around 2 dB in E(sub b)/N(sub o), depending on original E(sub b)/N(sub o), for BPSK, QPSK, 8PSK and 16QAM. The phase error effect is negligible for lower order modulations and is unacceptable for higher order modulations such as 64 and 256QAM.
This innovation is intended to reduce the size, power, and complexity of pipeline analog-to-digital converters (ADCs) that require high resolution and speed along with low power. Digitizers are important components in any application where analog signals (such as light, sound, temperature, etc.) need to be digitally processed. The innovation implements amplification of a sampled residual voltage in a switched capacitor amplifier stage that does not depend on charge redistribution. The result is less sensitive to capacitor mismatches that cause gain errors, which are the main limitation of such amplifiers in pipeline ADCs. The residual errors due to mismatch are reduced by at least a factor of 16, which is equivalent to at least 4 bits of improvement. The settling time is also faster because of a higher feedback factor. In traditional switched capacitor residue amplifiers, closed-loop amplification of a sampled and held residue signal is achieved by redistributing sampled charge onto a feedback capacitor around a high-gain transconductance amplifier. The residual charge that was sampled during the acquisition or sampling phase is stored on two or more capacitors, often equal in value or integral multiples of each other. During the hold or amplification phase, all of the charge is redistributed onto one capacitor in the feedback loop of the amplifier to produce an amplified voltage. The key error source is the non-ideal ratios of feedback and input capacitors caused by manufacturing tolerances, called mismatches. The mismatches cause non-ideal closed-loop gain, leading to higher differential non-linearity. Traditional solutions to the mismatch errors are to use larger capacitor values (than dictated by thermal noise requirements) and/or complex calibration schemes, both of which increase the die size and power dissipation. The key features of this innovation are (1) the elimination of the need for charge redistribution to achieve an accurate closed-loop gain of two, (2) a higher feedback factor in the amplifier stage giving a higher closed-loop bandwidth compared to the prior art, and (3) reduced requirement for calibration. The accuracy of the new amplifier is mainly limited by the sampling networks parasitic capacitances, which should be minimized in relation to the sampling capacitors.
A pulse position modulated (PPM) optical communication system using narrow pulses of light for data transmission requires accurate time synchronization between transmitter and receiver. The presence of signal energy in the form of optical pulses suggests the use of a pulse edge tracking method of maintaining the necessary timing. The edge tracking operation in a binary PPM system is examined, taking into account the quantum nature of the optical transmissions. Consideration is given first to pure synchronization using a periodic pulsed intensity, then extended to the case where position modulation is present and auxiliary bit decisioning is needed to aid the tracking operation. Performance analysis is made in terms of timing error and its associated statistics. Timing error variances are shown as a function of system signal to noise ratio.
Demonstration that the error signal incurred by block quantizing stationary data is nonstationary under some conditions. Examples are presented which indicate that the mean square error is largest at the block edges. When block quantizers are used to encode pictures at low bit rates, this effect tends to make the block edges visible in the reconstructed picture.
Multiamplitude minimum shift keying (mamsk) transmission system, method of differential encoding overcomes problem of ambiguity associated with advanced digital-transmission techniques with little or no penalty in transmission rate, error rate, or system complexity. Principle of method states, if signal points are properly encoded and decoded, bits are detected correctly, regardless of phase ambiguities.
Both bipolar and MOS integrated circuits have been empirically demonstrated to be susceptible to single-particle soft-error generation, commonly referred to as single-event upset (SEU), which is manifested in a bit-flip in a latch-circuit construction. Here, the intrinsic characteristics of SEU in bipolar (static) RAM's are demonstrated through results obtained from the modeling of this effect using computer circuit-simulation techniques. It is shown that as the dimensions of the devices decrease, the critical charge required to cause SEU decreases in proportion to the device cross-section. The overall results of the simulations are applicable to most integrated circuit designs.
This thesis presents the design, implementation, and validation of a calorimeter Data Quality Monitoring (DQM) toolchain for the Mu2e experiment at Fermilab. Mu2e searches for charged lepton flavor violation via coherent muon-to-electron conversion in the field of an aluminum nucleus, $\mu^- Al \rightarrow e^-Al$, a process whose observation would constitute clear evidence of physics beyond the Standard Model. Achieving target sensitivity requires stringent control of detector performance and data integrity during acquisition, as subtle issues in readout configuration, data formatting, or electronics behavior can compromise reconstruction and bias downstream analyzes. To address these challenges, this work develops a multi-layer DQM approach spanning both raw data validation and reconstructed digi-level diagnostics. At the low level, a fragment analysis component performs word- and bit-field decoding of calorimeter readout blocks, enabling sanity checks of the expected structure and producing detailed error and integrity statistics useful for commissioning and troubleshooting. At the digi level, the CaloDigiDQM analyzer is implemented within the art framework and transforms each CaloDigiCollection into a structured hierarchy of ROOT histograms designed for fast drill-down diagnostics. The module generates coherent monitoring views at global, disk, board, and channel granularity, including occupancy, waveform-derived features (baseline, RMS, peak amplitude and position), and left-right sensor consistency metrics. Detector-aware channel-to-electronics mapping is performed through the conditions system (CaloDAQMap), ensuring that diagnostics remain aligned with hardware identifiers used in operations. For end-to-end testing without reliance on live DAQ data, a synthetic CaloDigi producer is developed to generate realistic waveforms with controlled noise and pulse shapes. The resulting system supports both offline ROOT-file production and online operation, including optional histogram streaming through otsdaq via ots::HistoSender. This toolchain provides a practical and scalable foundation for calorimeter commissioning and stable data collection, enabling early detection of anomalies and reducing operational risk for Mu2e.