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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 775 records · Page 43

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NASA NTRS1978

Fault tolerance using self-checking building-block computers

The paper attempts to define and characterize a set of VLSI (very large scale integration) building-block circuits which can be used to combine existing microprocessors and memories into a wide variety of fault-tolerant computing systems. Such VLSI circuits would transform fault-tolerant computing into an off-the-shelf technology and enable its routine use for new applications. The self-checking computer module (SCCM) is the basic component out of which fault-tolerant computer systems are constructed. Several fault-tolerant configurations of SCCM are discussed, including the standby redundant uniprocessor, the voted/hybrid uniprocessor, and the distributed computer network.

Rennels, D. A.↗

NASA NTRS1982

Short-term memory and dual task performance

Two hypotheses concerning the way in which short-term memory interacts with another task in a dual task situation are considered. It is noted that when two tasks are combined, the activity of controlling and organizing performance on both tasks simultaneously may compete with either task for a resource; this resource may be space in a central mechanism or general processing capacity or it may be some task-specific resource. If a special relationship exists between short-term memory and control, especially if there is an identity relationship between short-term and a central controlling mechanism, then short-term memory performance should show a decrement in a dual task situation. Even if short-term memory does not have any particular identity with a controlling mechanism, but both tasks draw on some common resource or resources, then a tradeoff between the two tasks in allocating resources is possible and could be reflected in performance. The persistent concurrence cost in memory performance in these experiments suggests that short-term memory may have a unique status in the information processing system.

Regan, J. E.↗

NASA NTRS1983

Development and evaluation of a Fault-Tolerant Multiprocessor (FTMP) computer. Volume 2: FTMP software

The software developed for the Fault-Tolerant Multiprocessor (FTMP) is described. The FTMP executive is a timer-interrupt driven dispatcher that schedules iterative tasks which run at 3.125, 12.5, and 25 Hz. Major tasks which run under the executive include system configuration control, flight control, and display. The flight control task includes autopilot and autoland functions for a jet transport aircraft. System Displays include status displays of all hardware elements (processors, memories, I/O ports, buses), failure log displays showing transient and hard faults, and an autopilot display. All software is in a higher order language (AED, an ALGOL derivative). The executive is a fully distributed general purpose executive which automatically balances the load among available processor triads. Provisions for graceful performance degradation under processing overload are an integral part of the scheduling algorithms.

Lala, J. H.↗

NASA NTRS1987

Life sciences flight experiments microcomputer

A promising microcomputer configuration for the Spacelab Life Sciences Lab. Equipment inventory consists of multiple processors. One processor's use is reserved, with additional processors dedicated to real time input and output operations. A simple form of such a configuration, with a processor board for analog to digital conversion and another processor board for digital to analog conversion, was studied. The system used digital parallel data lines between the boards, operating independently of the system bus. Good performance of individual components was demonstrated: the analog to digital converter was at over 10,000 samples per second. The combination of the data transfer between boards with the input or output functions on each board slowed performance, with a maximum throughput of 2800 to 2900 analog samples per second. Any of several techniques, such as use of the system bus for data transfer or the addition of direct memory access hardware to the processor boards, should give significantly improved performance.

Bartram, Peter N.↗

NASA NTRS1989

Enhancements to the IBM version of COSMIC/NASTRAN

Major improvements were made to the IBM version of COSMIC/NASTRAN by RPK Corporation under contract to IBM Corporation. These improvements will become part of COSMIC's IBM version and will be available in the second quarter of 1989. The first improvement is the inclusion of code to take advantage of IBM's new Vector Facility (VF) on its 3090 machines. The remaining improvements are modifications that will benefit all users as a result of the extended addressing capability provided by the MVS/XA operating system. These improvements include the availability of an in-memory data base that potentially eliminates the need for I/O to the PRIxx disk files. Another improvement is the elimination of multiple load modules that have to be loaded for every link switch within NASTRAN. The last improvement allows for NASTRAN to execute above the 16 mega-byte line. This improvement allows for NASTRAN to have access to 2 giga-bytes of memory for open core and the in-memory data base.

Brown, W. Keith↗

NASA NTRS1992

Laser Scanner Tests For Single-Event Upsets

Microelectronic advanced laser scanner (MEALS) is opto/electro/mechanical apparatus for nondestructive testing of integrated memory circuits, logic circuits, and other microelectronic devices. Multipurpose diagnostic system used to determine ultrafast time response, leakage, latchup, and electrical overstress. Used to simulate some of effects of heavy ions accelerated to high energies to determine susceptibility of digital device to single-event upsets.

Kim, Quiesup↗

NASA NTRS1992

Creative-Dynamics Approach To Neural Intelligence

Paper discusses approach to mathematical modeling of artificial neural networks exhibiting complicated behaviors reminiscent of creativity and intelligence of biological neural networks. Neural network treated as non-Lipschitzian dynamical system - as described in "Non-Lipschitzian Dynamics For Modeling Neural Networks" (NPO-17814). System serves as tool for modeling of temporal-pattern memories and recognition of complicated spatial patterns.

Zak, Michail A.↗

NASA NTRS1992

A self-defining hierarchical data system

The Self-Defining Data System (SDS) is a system which allows the creation of self-defining hierarchical data structures in a form which allows the data to be moved between different machine architectures. Because the structures are self-defining they can be used for communication between independent modules in a distributed system. Unlike disk-based hierarchical data systems such as Starlink's HDS, SDS works entirely in memory and is very fast. Data structures are created and manipulated as internal dynamic structures in memory managed by SDS itself. A structure may then be exported into a caller supplied memory buffer in a defined external format. This structure can be written as a file or sent as a message to another machine. It remains static in structure until it is reimported into SDS. SDS is written in portable C and has been run on a number of different machine architectures. Structures are portable between machines with SDS looking after conversion of byte order, floating point format, and alignment. A Fortran callable version is also available for some machines.

Bailey, J.↗

NASA NTRS1995

Interface Provides Standard-Bus Communication

Microprocessor-controlled interface (IEEE-488/LVABI) incorporates service-request and direct-memory-access features. Is circuit card enabling digital communication between system called "laser auto-covariance buffer interface" (LVABI) and compatible personal computer via general-purpose interface bus (GPIB) conforming to Institute for Electrical and Electronics Engineers (IEEE) Standard 488. Interface serves as second interface enabling first interface to exploit advantages of GPIB, via utility software written specifically for GPIB. Advantages include compatibility with multitasking and support of communication among multiple computers. Basic concept also applied in designing interfaces for circuits other than LVABI for unidirectional or bidirectional handling of parallel data up to 16 bits wide.

Culliton, William G.↗

NASA NTRS1997

A Report of Bethune-Cookman College NASA JOVE Projects

This document is the final report for the Joint Venture (JOVE) in Space Sciences, and describes the tasks, performed with the support of the contract. These tasks include work in: (1) interfacing microprocessor systems to high performance parallel interface chips, SCSI drive and memory, needed for the implementation of a Space Optical Data Recorder; (2) designing a digital interface architecture for a microprocessor controlled sensors monitoring unit for a NASA Jitter Attenuation and Dynamics Experiment (JADE) project; (3) developing an enhanced back-propagation training algorithm; (4) studying the effect of simulated spaceflight on Aortic Contractility; (5) developing a course in astronomy; and (6) improving internet access by running cables, and installing hubs in various places on the campus; and (7) researching the characteristics of Nd:YALO laser resonator.

Agba, Lawrence C.↗

NASA NTRS1999

Efficient Parallelization of a Dynamic Unstructured Application on the Tera MTA

The success of parallel computing in solving real-life computationally-intensive problems relies on their efficient mapping and execution on large-scale multiprocessor architectures. Many important applications are both unstructured and dynamic in nature, making their efficient parallel implementation a daunting task. This paper presents the parallelization of a dynamic unstructured mesh adaptation algorithm using three popular programming paradigms on three leading supercomputers. We examine an MPI message-passing implementation on the Cray T3E and the SGI Origin2OOO, a shared-memory implementation using cache coherent nonuniform memory access (CC-NUMA) of the Origin2OOO, and a multi-threaded version on the newly-released Tera Multi-threaded Architecture (MTA). We compare several critical factors of this parallel code development, including runtime, scalability, programmability, and memory overhead. Our overall results demonstrate that multi-threaded systems offer tremendous potential for quickly and efficiently solving some of the most challenging real-life problems on parallel computers.

Oliker, Leonid↗

NASA NTRS1994

What Can Interplanetary Dust Particles Tell Us About Interstellar Dust?

Dust is injected into the interplanetary medium by both comets and asteroids and there is reason to believe that particles from both of these types of sources are represented in the population of interplanetary dust collected in the stratosphere. The presence of isotopic anomalies and of adjacent mineral and carbonaceous phases that are chemically unequilibrated indicates that these particles contain primitive materials that have avoided many of the alteration processes that have affected most other extraterrestrial materials since their aggregation in the Solar nebula. This suggests that many of the subcomponents of the collected dust may have a chemical and isotopic 'memory' that extends back through the formation of the Solar System and therefore reflects the properties of interstellar dust populations. Indeed, it is possible that some of the subcomponents of the collected dust could have been true interstellar dust grains prior to the formation of the Solar nebula. The implications of this possibility will be discussed in light of our present knowledge of interplanetary dust.

Sandford, Scott A.↗

NASA NTRS2002

Pyrotechnically Operated Valves for Testing and Flight

Pyrovalves still warrant careful description of their operating characteristics, which is consistent with the NASA mission - to assure that both testing and flight hardware perform with the utmost reliability. So, until the development and qualification of the next generation of remotely controlled valves, in all likelihood based on shape memory alloy technology, pyrovalves will remain ubiquitous in controlling flow systems aloft and will possibly see growing use in ground-based testing facilities. In order to assist NASA in accomplishing this task, we propose a three-phase, three-year testing program. Phase I would set up an experimental facility, a 'test rig' in close cooperation with the staff located at the White Sands Test Facility in Southern New Mexico.

Conley, Edgar G.↗

NASA NTRS2002

National Combustion Code Parallel Performance Enhancements

The National Combustion Code (NCC) is being developed by an industry-government team for the design and analysis of combustion systems. The unstructured grid, reacting flow code uses a distributed memory, message passing model for its parallel implementation. The focus of the present effort has been to improve the performance of the NCC code to meet combustor designer requirements for model accuracy and analysis turnaround time. Improving the performance of this code contributes significantly to the overall reduction in time and cost of the combustor design cycle. This report describes recent parallel processing modifications to NCC that have improved the parallel scalability of the code, enabling a two hour turnaround for a 1.3 million element fully reacting combustion simulation on an SGI Origin 2000.

Quealy, Angela↗

NASA NTRS2002

NAS Parallel Benchmarks

We describe a new problem size, called Class D, for the NAS Parallel Benchmarks (NPB), whose MPI source code implementation is being released as NPB 2.4. A brief rationale is given for how the new class is derived. We also describe the modifications made to the MPI (Message Passing Interface) implementation to allow the new class to be run on systems with 32-bit integers, and with moderate amounts of memory. Finally, we give the verification values for the new problem size.

VanderWijngaart, Rob↗

NASA NTRS2003

Performance Analysis of Multilevel Parallel Applications on Shared Memory Architectures

Parallel programming paradigms include process level parallelism, thread level parallelization, and multilevel parallelism. This viewgraph presentation describes a detailed performance analysis of these paradigms for Shared Memory Architecture (SMA). This analysis uses the Paraver Performance Analysis System. The presentation includes diagrams of a flow of useful computations.

Biegel, Bryan A.↗

NASA NTRS2011

A Tribute to Professor Rene H. Miller - A Pioneer in Aeromechanics and Rotary Wing Flight Transportation

Rene H. Miller (May 19, 1916 January 28, 2003), Emeritus H. N. Slater Professor of Flight Transportation, was one of the most influential pioneers in rotary wing aeromechanics as well as a visionary whose dream was the development of a tilt-rotor based short haul air transportation system. This paper pays a long overdue tribute to his memory and to his extraordinary contributions.

Friedmann, Peretz P.↗

NASA NTRSDate not supplied

Development of Slat-gap and Slat-cove Filler Treatments for Noise Reduction Assessment on the High Lift Common Research Model in the NASA LaRC 14x22

Airframe noise is an important issue during the approach and landing phases of flight because engines are throttled back, and airframe sources become an equal or greater contributor to environmental noise. The leading-edge slat component of the high-lift system for transport aircraft has been identified as a prominent source of airframe noise. Noise production mechanisms and potential treatments to mitigate airframe noise have been areas of active research for nearly three decades. Two promising technologies for slat noise reduction are the slat-gap filler (SGF) and slat-cove filler (SCF). Previous work was done using a 2D section of a transport class aircraft wing to demonstrate their feasibility via benchtop and computational models. A wind tunnel test campaign was recently undertaken to test the SGF and SCF technologies in a flight-like environment by installing dynamically scaled treatments on the 10%-scale High-Lift Common Research Model (CRM-HL), which is representative of a commercial twin-aisle transport aircraft. Advancement of the SGF and SCF technologies to overcome challenges of integration with 3D airframe structures, computational simulations of the CRM-HL predicting the aerodynamic and aeroacoustic performance and structural loads, and design of wind tunnel model hardware with features accommodating noise treatments were conducted in parallel. Details of innovations in the SGF and SCF technologies for 3D airframe feasibility will be described. The loads the treatments must sustain in flight and the influence of those loads on the design is also discussed. Finally, the design of wing leading-edge assemblies to treat the 10% CRM-HL with dynamically scaled SGF and SCF components is presented. The treatments were successfully tested in 2020/2021 providing a demonstration of leading-edge noise reduction using components that would allow slat articulation.

airframe noise reduction↗