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At least 775 records · Page 43

A First Step Towards Quantum Simulating Jet Evolution in a Dense Medium

The fast development of quantum technologies over the last decades has offered a glimpse to a future where the quantum properties of multi particle systems might be more fully understood. In particular, quantum computing might prove crucial to explore many aspects of high energy physics unaccessible to classical methods. In this talk, we will describe how one can use digital quantum computers to study the evolution of QCD jets in quark gluons plasmas. We construct a quantum circuit to study single particle evolution in a dense QCD medium. Focusing on the jet quenching parameter $\hat{q}$, we present some early numerical results for a small quantum circuit. Future extensions of this strategy are also addressed.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

Closed circuit TV system automatically guides welding arc

Closed circuit television /CCTV/ system automatically guides a welding torch to position the welding arc accurately along weld seams. Digital counting and logic techniques incorporated in the control circuitry, ensure performance reliability.

Stephans, D. L.↗

Hierarchical hybrid control of manipulators: Artificial intelligence in large scale integrated circuits

Both in practical engineering and in control of muscular systems, low level subsystems automatically provide crude approximations to the proper response. Through low level tuning of these approximations, the proper response variant can emerge from standardized high level commands. Such systems are expressly suited to emerging large scale integrated circuit technology. A computer, using symbolic descriptions of subsystem responses, can select and shape responses of low level digital or analog microcircuits. A mathematical theory that reveals significant informational units in this style of control and software for realizing such information structures are formulated.

Greene, P. H.↗

CYBER 200 Applications Seminar

Applications suited for the CYBER 200 digital computer are discussed. Various areas of application including meteorology, algorithms, fluid dynamics, monte carlo methods, petroleum, electronic circuit simulation, biochemistry, lattice gauge theory, economics and ray tracing are discussed.

Gary, J. P.↗

Delay analysis of combinations of pass transistors and classical logic gates

Combinations of pass transistors and logic gates driving nonlinear capacitive loads are analyzed for the presence of characteristics that will permit easier and more accurate digital logic simulation. Accurate time delay models are developed by studying the nature of the response of simplified circuit models to variations of input waveform rise and fall times and output loading. The nonlinear effects of the CMOS logic devices are minimized to permit easier interpretation of the influence of nonlinear capacitive loads. The performance of a CMOS inverter with a complex nonlinear load consisting of a pass transistor that separates a range of capacitances is compared to the same inverter circuit with a linear capacitive load to develop an understanding of the unique requirements of modeling a nonlinear system. Several methods of modeling the delay of CMOS circuits are reviewed, and a multi-parameter linear model is described. General guidelines for designing CMOS circuits with complex load circuits are developed, emphasizing that the circuit output rise delays and fall delays must be separately analyzed.

Gibson, Jonathan S.↗

A Spaceflight Magnetic Bearing Equipped Optical Chopper with Six-Axis Active Control

This paper describes the development of an ETU (Engineering Test Unit) rotary optical chopper with magnetic bearings. An ETU is required to be both flight-like, nearly identical to a flight unit without the need for material certifications, and demonstrate structural and performance integrity. A prototype breadboard design previously demonstrated the feasibility of meeting flight performance requirements using magnetic bearings. The chopper mechanism is a critical component of the High Resolution Dynamics Limb Sounder (HIRDLS) which will be flown on EOS-CHEM (Earth Observing System-Chemistry). Particularly noteworthy are the science requirements which demand high precision positioning and minimal power consumption along with full redundancy of coils and sensors in a miniature, lightweight package. The magnetic bearings are unique in their pole design to minimize parasitic losses and utilize collocated optical sensing. The motor is of an unusual disk-type ironless stator design. The ETU design has evolved from the breadboard design. A number of improvements have been incorporated into the ETU design. Active thrust control has been added along with changes to improve sensor stability, motor efficiency, and touchdown and launch survivability. It was necessary to do all this while simultaneously reducing the mechanism volume. Flight-like electronics utilize a DSP (Digital Signal Processor) and contain all sensor electronics and drivers on a single five inch by nine inch circuit board. Performance test results are reported including magnetic bearing and motor rotational losses.

Blumenstock, Kenneth A.↗

A Spaceflight Magnetic Bearing Equipped Optical Chopper with Six-Axis Active Control

This paper describes the development of an ETU (Engineering Test Unit) rotary optical chopper with magnetic bearings. An ETU is required to be both flight-like, nearly identical to a flight unit without the need for material certifications, and demonstrate structural and performance integrity. A prototype breadboard design previously demonstrated the feasibility of meeting flight performance requirements using magnetic bearings. The chopper mechanism is a critical component of the High Resolution Dynamics Limb Sounder (HIRDLS) which will be flown on EOS-CHEM (Earth Observing System-Chemistry). Particularly noteworthy are the science requirements which demand high precision positioning and minimal power consumption along with full redundancy of coils and sensors in a miniature, lightweight package. The magnetic bearings are unique in their pole design to minimize parasitic losses and utilize collocated optical sensing. The motor is of an unusual disk-type ironless stator design. The ETU design has evolved from the breadboard design. A number of improvements have been incorporated into the ETU design. Active thrust control has been added along with changes to improve sensor stability, motor efficiency, and touchdown and launch survivability. It was necessary to do all this while simultaneously reducing the mechanism volume. Flight-like electronics utilize a DSP (Digital Signal Processor) and contain all sensor electronics and drivers on a single five inch by nine inch circuit board. Performance test results are reported including magnetic bearing and motor rotational losses.

Blumenstock, K. A.↗

A Spaceflight Magnetic Bearing Equipped Optical Chopper with Six-Axis Active Control

This paper describes the development of an ETU (Engineering Test Unit) rotary optical chopper with magnetic bearings. An ETU is required to be both flight-like, nearly identical to a flight unit without the need for material certifications, and demonstrate structural and performance integrity. A prototype breadboard design previously demonstrated the feasibility of meeting flight performance requirements using magnetic bearings. The chopper mechanism is a critical component of the High Resolution Dynamics Limb Sounder (HIRDLS) which will be flown on EOS-CHEM (Earth Observing System-Chemistry). Particularly noteworthy are the science requirements which demand high precision positioning and minimal power consumption along with full redundancy of coils and sensors in a miniature, lightweight package. The magnetic bearings are unique in their pole design to minimize parasitic losses and utilize collocated optical sensing. The motor is of an unusual disk-type ironless stator design. The ETU design has evolved from the breadboard design. A number of improvements have been incorporated into the ETU design. Active thrust control has been added along with changes to improve sensor stability, motor efficiency, and touchdown and launch survivability. It was necessary to do all this while simultaneously reducing the mechanism volume. Flight-like electronics utilize a DSP (Digital Signal Processor) and contain all sensor electronics and drivers on a single five inch by nine inch circuit board. Performance test results are reported including magnetic bearing and motor rotational losses.

Blumenstock, Kenneth A.↗

Using Modern Design Tools for Digital Avionics Development

Using Modem Design Tools for Digital Avionics Development Shrinking development time and increased complexity of new avionics forces the designer to use modem tools and methods during hardware development. Engineers at the Marshall Space Flight Center have successfully upgraded their design flow and used it to develop a Mongoose V based radiation tolerant processor board for the International Space Station's Water Recovery System. The design flow, based on hardware description languages, simulation, synthesis, hardware models, and full functional software model libraries, allowed designers to fully simulate the processor board from reset, through initialization before any boards were built. The fidelity of a digital simulation is limited to the accuracy of the models used and how realistically the designer drives the circuit's inputs during simulation. By using the actual silicon during simulation, device modeling errors are reduced. Numerous design flaws were discovered early in the design phase when they could be easily fixed. The use of hardware models and actual MIPS software loaded into full functional memory models also provided checkout of the software development environment. This paper will describe the design flow used to develop the processor board and give examples of errors that were found using the tools. An overview of the processor board firmware will also be covered.

Hyde, David W.↗

Field Programmable Gate Array for Implementation of Redundant Advanced Digital Feedback Control

The goal of this effort was to develop a digital motor controller using field programmable gate arrays (FPGAs). This is a more rugged approach than a conventional microprocessor digital controller. FPGAs typically have higher radiation (rad) tolerance than both the microprocessor and memory required for a conventional digital controller. Furthermore, FPGAs can typically operate at higher speeds. (While speed is usually not an issue for motor controllers, it can be for other system controllers.) Other than motor power, only a 3.3-V digital power supply was used in the controller; no analog bias supplies were used. Since most of the circuit was implemented in the FPGA, no additional parts were needed other than the power transistors to drive the motor. The benefits that FPGAs provide over conventional designs-lower power and fewer parts-allow for smaller packaging and reduced weight and cost.

King, K. D.↗

Development of Electronic Load Controllers for Free-Piston Stirling Convertors Aided by Stirling Simulation Model

The free-piston Stirling convertor end-to-end modeling effort at the NASA Glenn Research Center has produced a software-based test bed in which free-piston Stirling convertors can be simulated and evaluated. The simulation model includes all the components of the convertor: the Stirling cycle engine, heat source, linear alternator, controller, and load. So far, it has been used in evaluating the performance of electronic controller designs. Three different controller design concepts were simulated using the model: 1) Controllers with parasitic direct current loading. 2) Controllers with parasitic alternating current loading. 3) Controllers that maintain a reference current. The free-piston Stirling convertor is an electromechanical device that operates at resonance. It is the function of the electronic load controller to ensure that the electrical load seen by the machine is always great enough to keep the amplitude of the piston and alternator oscillation at the rated value. This is done by regulating the load on the output bus. The controller monitors the instantaneous voltage, regulating it by switching loads called parasitic loads onto the bus whenever the bus voltage is too high and removing them whenever the voltage is too low. In the first type of controller, the monitor-ing and switching are done on the direct-current (dc) bus. In the second type, the alternating current bus is used. The model allows designers to test a controller concept before investing time in hardware. The simulation code used to develop the model also offers detailed models of digital and analog electronic components so that the resulting designs are realistic enough to translate directly into hardware circuits.

Regan, Timothy F.↗

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

radiation hardened by design↗

A DATA EFFICIENT SPARSE MODELING FRAMEWORK FOR POWER ESTIMATION IN WATER TREATMENT SENSING OPERATIONS

With increasing freshwater scarcity, advanced process design mechanisms such as Closed-Circuit Reverse Osmosis (CCRO) and Digital/Physical Twin systems are gaining traction in water treatment and reuse operations. While digital and physical twin models enable improved system insight and control, their development is often expensive and computationally intensive, requiring large volumes of synthetic or experimental data to characterize underlying process dynamics. This work introduces a sparse surrogate modeling framework to estimate power consumption from measured flow and pressure variables, along with their nonlinear polynomial and interaction expansions. To ensure model reliability and reduce overfitting, a two-stage pipeline is proposed. First, a dynamic data filtering algorithm is employed to remove uninformative observations and transient operational states. Second, a sparse penalized regression technique is applied to select a minimal set of parsimonious features. The proposed model achieves high sparsity, retaining only 7 out of 34 candidate features (≈79.41% sparsity) while delivering a root mean square error (RMSE) of 0.072 on the test dataset.

Mukherjee, Subrata [ORNL] (ORCID:0000000309930338)↗

Self-Timed Digital System Design

A timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems was developed in this work. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modify the circuit clock period.

Walker, Alvernon↗

Strategies for on-chip digital data compression for X-ray pixel detectors

Here, the continued desire for X-ray pixel detectors with higher frame rates will stress the ability of application-specific integrated circuit (ASIC) designers to provide sufficient off-chip bandwidth to reach continuous frame rates in the 1 MHz regime. To move from the current 10 kHz to the 1 MHz frame rate regime, ASIC designers will continue to pack as many power-hungry high-speed transceivers at the periphery of the ASIC as possible. In this paper, however, we present new strategies to make the most efficient use of the off-chip bandwidth by utilizing data compression schemes for X-ray photon-counting and charge-integrating pixel detectors. In particular, we describe a novel in-pixel compression scheme that converts from analog to digital converter units to encoded photon counts near the photon Poisson noise level and achieves a compression ratio of >1.5x independent of the dataset. In addition, we describe a simple yet efficient zero-suppression compression scheme called "zeromask" (ZM) located at the ASIC's edge before streaming data off the ASIC chip. ZM achieves average compression ratios of >4x, >7x, and >8x for high-energy X-ray diffraction, ptychography, and X-ray photon correlation spectroscopy datasets, respectively. We present the conceptual designs, register-transfer level block diagrams, and the physical ASIC implementation of these compression schemes in 65 nm CMOS. When combined, these two digital compression schemes could increase the effective off-chip bandwidth by a factor of 6-12x.

47 OTHER INSTRUMENTATION↗

A Real-Time ANPC Inverter Digital Twin with Integrated Design-For-Trust

The demand for renewable energy has increased over the last few years, and so has the demand for greater expectations within the energy market. This increasing trend has been accompanied by more significant usage of internet-connected devices (IoT), leading to critical electrical infrastructure being connected to the internet. Implementing internet connectivity with such devices and systems provides benefits such as improving the system's performance, facilitating irregularity and anomaly mitigation, and providing additional situational awareness for enhanced decision-making. However, enhancing the connected system with IoT introduces a drawback – a greater vulnerability to cyber-attacks. Cyber-attacks targeting critical infrastructure in the electrical sector have occurred in the United States and Ukraine. These cyber-attacks highlight and expose vulnerabilities that a system inherits when connecting to the internet. These attacks left thousands of customers without electricity for hours until operators could regain control of the electric utility grid. Therefore, to address the vulnerabilities of an internet-connected power electronic device, this work focused on the hardware layer of the system. Implementing a cyber-control system inside the hardware layer can significantly reduce the possibility of an attacker patching malicious controller firmware into a photovoltaic grid-connected inverter, thus mitigating the likelihood that the inverter becomes inactive a cyber-attack scenario. With this mitigation technique, if a cyberattack is successful and an attacker gains control of the network, a cyber-defense technique is in place to mitigate the impact of the cyber-attack. This additional protection layer was developed based on an innovative concept known as Digital Twin (DT). A DT, in this case, replicates an Active-Neutral Point Clamped (ANPC) inverter and was designed using a hardware language known as VHDL (Very High-Speed Integrated Circuit Hardware Description Language) and applied to Field-Programmable-GateArray (FPGA). The DT is embedded within the FPGA and contained in a controller board, the UCB (Unified Controller Board), developed by the University of Arkansas electrical engineering team. This UCB also contains two Digital Signal Processors (DSPs) responsible for generating associated signals to control an authentic physical inverter. These DSP signals are received and processed by the FPGA that implements the DT of an ANPC; in other words, it simulates in realtime the expected output of an actual ANPC inverter using the signals from the DSP. When a new firmware is ready to be patched, the DT provides output signals simulating behavior that a real ANPC inverter would generate with the new firmware. The new firmware is tested to check if it meets all the operational requirements established using a Design-For-Trust technique (DFTr). If the new firmware fails in at least one of the DFT tests, it is considered malicious and must be rejected. This work is divided into sections, such as Background, which explains the pieces that were used and the strategy behind this work; Process and Procedure, which explains the methodology that was adopted to prove the reliability and effectiveness of this work; Results and Discussion, where the simulations and results are described and explained; followed by Conclusion and Future work section, which concludes this work and adds possible future projects to continue this work further.

do Amaral Custodio, Paulo Vitor↗

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗