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At least 757 records · Page 42

Simple digital pulse-programing circuit

Pulse-sequencing circuit uses only shift register and Exclusive-OR gates. Circuit also serves as date-transition edge detector (for rising or falling edges). It is used in sample-and-hold, analog-to-digital conversion sequence control, multiphase clock logic, precise delay control computer control logic, edge detectors, other timing applications, and provides simple means to generate timing and control signals for data transfer, addressing, or mode control in microprocessors and minicomputers.

Langston, J. L.↗

A high-speed computer link for moderate distances and noisy environments

To satisfy the need for a fully duplex high-speed computer data link for the antenna automation project at DSS 13, a very simple and inexpensive scheme was employed. The link requires two coaxial cables over which is sent a unipolar digital frequency modulated signal in which a logical 1 has twice the frequency of a logical 0. Optical isolators and filters reduce ground loop effects and increase noise immunity. Tests conducted in various environments and over different cable lengths at JPL, DSS 14 and DSS 13 have indicated that the link is highly effective.

Sievers, M. W.↗

Heliocentric interplanetary low thrust trajectory optimization program, supplement 1, part 2

The improvements made to the HILTOP electric propulsion trajectory computer program are described. A more realistic propulsion system model was implemented in which various thrust subsystem efficiencies and specific impulse are modeled as variable functions of power available to the propulsion system. The number of operating thrusters are staged, and the beam voltage is selected from a set of five (or less) constant voltages, based upon the application of variational calculus. The constant beam voltages may be optimized individually or collectively. The propulsion system logic is activated by a single program input key in such a manner as to preserve the HILTOP logic. An analysis describing these features, a complete description of program input quantities, and sample cases of computer output illustrating the program capabilities are presented.

Mann, F. I.↗

Failure detection and correction for turbofan engines

In this paper, a failure detection and correction strategy for turbofan engines is discussed. This strategy allows continuing control of the engines in the event of a sensor failure. An extended Kalman filter is used to provide the best estimate of the state of the engine based on currently available sensor outputs. Should a sensor failure occur the control is based on the best estimate rather than the sensor output. The extended Kalman filter consists of essentially two parts, a nonlinear model of the engine and up-date logic which causes the model to track the actual engine. Details on the model and up-date logic are presented. To allow implementation, approximations are made to the feedback gain matrix which result in a single feedback matrix which is suitable for use over the entire flight envelope. The effect of these approximations on stability and response is discussed. Results from a detailed nonlinear simulation indicate that good control can be maintained even under multiple failures.

Corley, R. C.↗

Real-time digital integrator

Field programmable logic array (FPLA) is used to make 3-bit arithmetic logic unit (ALU) for large integrator that can be read and cleared while new data is added to begin new integral. Arrangement of device can provide for full carry/lookahead capability with minimum gate delays.

Rubin, A. L.↗

Spacecraft trajectory

Two programs, Hiltop I and Hiltop II, generate optimum trajectory data for electric propulsion missions of interest in exploration of solar system. Propulsion-system logic is activated by single program-input key; program modifications retain Hiltop I within framework of logic, so that Hiltop I input files, will run Hiltop II version and produce identical results as before.

Horsewood, J. L.↗

Solar heating system final design package

The system is composed of a warm air collector, a logic control unit and a universal switching and transport unit. The collector was originally conceived and designed as an integrated roof/wall system and therefore provides a dual function in the structure. The collector serves both as a solar energy conversion system and as a structural weather resistant skin. The control unit provides totally automatic control over the operation of the system. It receives input data from sensor probes in collectors, storage and living space. The logic was designed so as to make maximum use of solar energy and minimize use of conventional energy. The transport and switching unit is a high-efficiency air-handling system equipped with gear motor valves that respond to outputs from the control system. The fan unit was designed for maximum durability and efficiency in operation, and has permanently lubricated ball bearings and excellent air-handling efficiency.

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Reconfigurable modular computer networks for spacecraft on-board processing

The core electronics subsystems on unmanned spacecraft, which have been sent over the last 20 years to investigate the moon, Mars, Venus, and Mercury, have progressed through an evolution from simple fixed controllers and analog computers in the 1960's to general-purpose digital computers in current designs. This evolution is now moving in the direction of distributed computer networks. Current Voyager spacecraft already use three on-board computers. One is used to store commands and provide overall spacecraft management. Another is used for instrument control and telemetry collection, and the third computer is used for attitude control and scientific instrument pointing. An examination of the control logic in the instruments shows that, for many, it is cost-effective to replace the sequencing logic with a microcomputer. The Unified Data System architecture considered consists of a set of standard microcomputers connected by several redundant buses. A typical self-checking computer module will contain 23 RAMs, two microprocessors, one memory interface, three bus interfaces, and one core building block.

Rennels, D. A.↗

Fault-tolerance - The survival attribute of digital systems

Fault-tolerance is the architectural attribute of a digital system that keeps the logic machine doing its specified tasks when its host, the physical system, suffers various kinds of failures of its components. A more general concept of fault-tolerance also includes human mistakes committed during software and hardware implementation and during man/machine interaction among the causes of faults that are to be tolerated by the logic machine. This paper discusses the concept of fault-tolerance, the reasons for its inclusion in digital system architecture, and the methods of its implementation. A chronological view of the evolution of fault-tolerant systems and an outline of some goals for its further development conclude the presentation.

Avizienis, A.↗

Independent synchronizer for digital decoders

Logic circuit synchronizes branches of any convolution code-decoder at low signal to noise ratios. Parity checks determine correct node synchronization. Device maintains synchrony as low as -3 dB. Circuit consists of 15 stage shift register, three up down counters, and some logic gates.

Stiffler, J. J.↗

MCC level C formulation requirements. Entry guidance and entry autopilot, optional TAEM targeting

The level C software formulations requirements for the entry guidance and the simplified autopilot to be used by the Mission Control Center (MCC) entry processor are presented. The modifications required to functionally simulate optional Terminal Area Energy Management (TAEM) targeting capability (OTT) are incorporated. Implementation of this logic in the MCC must be coordinated with flight software OTT implementation and MCC TAEM guidance OTT. The entry guidance logic is based on the orbiter avionics entry guidance software. Descriptions of the entry guidance detailed formulation requirements, the detailed autopilot formulation requirements, and the targeting routine are given. Also included are a definition of coordinate systems, a list of parameter definitions for the software formulations, and a set of formulation flow charts.

Harpold, J. C.↗

Shuttle program. MCC Level C formulation requirements: Entry guidance and entry autopilot

A set of preliminary entry guidance and autopilot software formulations is presented for use in the Mission Control Center (MCC) entry processor. These software formulations meet all level B requirements. Revision 2 incorporates the modifications required to functionally simulate optimal TAEM targeting capability (OTT). Implementation of this logic in the MCC must be coordinated with flight software OTT implementation and MCC TAEM guidance OTT. The entry guidance logic is based on the Orbiter avionics entry guidance software. This MCC requirements document contains a definition of coordinate systems, a list of parameter definitions for the software formulations, a description of the entry guidance detailed formulation requirements, a description of the detailed autopilot formulation requirements, a description of the targeting routine, and a set of formulation flow charts.

Harpold, J. C.↗

Pioneer Venus Sounder Probe gas chromatograph

The design logic, construction, function, and data processing of the Pioneer Venus Sounder Probe gas chromatograph instrument are discussed. A gas chromatograph for the analysis of the chemical composition of the lower atmosphere of Venus was included in the Sounder Probe of the Pioneer Venus mission. This paper describes the design logic of the gas chromatograph as constrained by the mission; attention is given to instrument construction, function, and data reduction.

Oyama, V. I.↗

The response of the Seasat and Magsat infrared horizon scanners to cold clouds

Cold clouds over the Earth are shown to be the principal cause of pitch and roll measurement noise in flight data from the infrared horizon scanners onboard Seasat and Magsat. The observed effects of clouds on the fixed threshold horizon detection logic of the Magsat scanner and on the variable threshold detection logic of the Seasat scanner are discussed. National Oceanic and Atmospheric Administration (NOAA) Earth photographs marked with the scanner ground trace clearly confirm the relationship between measurement errors and Earth clouds. A one to one correspondence can be seen between excursion in the pitch and roll data and cloud crossings. The characteristics of the cloud-induced noise are discussed, and the response of the satellite control systems to the cloud errors is described. Changes to the horizon scanner designs that would reduce the effects of clouds are noted.

Bilanow, S.↗

The Spacelab Experiment Interface Device (SEID)

The Spacelab experiment interface device (SEID) is described which simulates the electrical, and logical connections of the Spacelab remote acquisition unit (RAU), the interface functions of the Spacelab experiment computer software, and the electrical aspects of the high rate multiplexer. Simulated RAU interfaces include PCM serial channels (up to four), user time clock (UTC), flexible inputs (up to 128) and discrete outputs (up to 64). Connectors are logically compatible with the rau. be instructed to execute sequences of input/output commands to the RAU, similar to those performed during flight. This approximation of the experiment computer software is adequate to detect interface problems and prevent these from occurring during Spacelab payload integration. The SEID hardware is a microprocessor based system, utilizing an 8085 microprocessor with 6K of PROM and 4K of static RAM. The basic unit is augmented with an LSI-11 microcomputer to provide disk storage and a more dynamic environment for generation of control data. A simulation of the general monitoring loop is provided to emulate Spacelab system timing.

Kallus, R.↗

High speed CMOS/SOS standard cell notebook

The NASA/MSFC high speed CMOS/SOS standard cell family, designed to be compatible with the PR2D (Place, Route in 2-Dimensions) automatic layout program, is described. Standard cell data sheets show the logic diagram, the schematic, the truth table, and propagation delays for each logic cell.

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C-MOS array design techniques

The entire complement of standard cells and components, except for the set-reset flip-flop, was completed. Two levels of checking were performed on each device. Logic cells and topological layout are described. All the related computer programs were coded and one level of debugging was completed. The logic for the test chip was modified and updated. This test chip served as the first test vehicle to exercise the standard cell complementary MOS(C-MOS) automatic artwork generation capability.

Feller, A.↗

Engineering evaluations and studies. Report for Ku-band studies, exhibit A

System performance aspects of the Ku band radar communication hardware and investigations into the Ku band/payload interfaces are discussed. The communications track problem caused by the excessive signal dynamic range at the servo input was investigated. The management/handover logic is discussed and a simplified description of the transmitter enable logic function is presented. Output noise produced by a voltage-controlled oscillator chip used in the SPA return-link channel 3 mid-bit detector is discussed. The deployed assembly (DA) and EA-2 critical design review data are evaluated. Cross coupling effects on antenna servo stability were examined. A series of meetings on the acceptance test specification for the deployed assembly is summarized.

Dodds, J. G.↗