Progress of analog/hybrid computation.
Analog/hybrid computer design, noting inclusion of solid state and integrated circuits for reliability cost reduction and speed
HYBRID COMPUTER↗
SEARCH · Engineering Papers
Results for “integrated circuits”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Input gate circuit converted for use as linear amplifier
Commercially available integrated circuit that is marketed as a digital computer input gate circuit was converted to a linear amplifier in a microphone circuit that has high input impedance, low output impedance, low cost, and is small enough to fit on a standard printed circuit card.
Harper, T. P.↗
Design rules for CMOS/SOS circuits
Report presents design rules for advanced-technology integrated circuits made by self-aligned silicongate complementary - metal - oxide - semiconductor/silicon-on-sapphir (CMOS/SOS) process.
Source record↗
Statistical circuit design for yield improvement in CMOS circuits
This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.
Kamath, H. J.↗
Non dissipative solar array optimum charge regulator Second quarterly report
Closed loop, integrated circuit voltage regulator for use in transmission of power from solar array to battery
POWER TRANSMISSION↗
Apacecraft Uplink, Downlink, and Intercommunications in a Space-Qualified ASIC Chip Set
This paper describes the functionality of four application specific integrated circuits (ASICs) developed for the Cassini spacecraft.
application specific integrated circuits (ASICs) u↗
Forward Bias Inhibits Single-Event Upsets
Bipolar integrated circuits more resistant to ionizing radiation. Tests show resistance of bipolar integrated logic or memory circuit by single-event upsets increased by imparting forward bias to diode constituted by buried layer of substrate and collector.
Zoutendyk, John A.↗
Miniature MMIC Low Mass/Power Radiometer Modules for the 180 GHz GeoSTAR Array
We have developed and demonstrated miniature 180 GHz Monolithic Microwave Integrated Circuit (MMIC) radiometer modules that have low noise temperature, low mass and low power consumption. These modules will enable the Geostationary Synthetic Thinned Aperture Radiometer (GeoSTAR) of the Precipitation and All-weather Temperature and Humidity (PATH) Mission for atmospheric temperature and humidity profiling. The GeoSTAR instrument has an array of hundreds of receivers. Technology that was developed included Indium Phosphide (InP) MMIC Low Noise Amplifiers (LNAs) and second harmonic MMIC mixers and I-Q mixers, surface mount Multi-Chip Module (MCM) packages at 180 GHz, and interferometric array at 180 GHz. A complete MMIC chip set for the 180 GHz receiver modules (LNAs and I-Q Second harmonic mixer) was developed. The MMIC LNAs had more than 50% lower noise temperature (NT=300K) than previous state-of-art and MMIC I-Q mixers demonstrated low LO power (3 dBm). Two lots of MMIC wafers were processed with very high DC transconductance of up to 2800 mS/mm for the 35 nm gate length devices. Based on these MMICs a 180 GHz Multichip Module was developed that had a factor of 100 lower mass/volume (16x18x4.5 mm3, 3g) than previous generation 180 GHz receivers.
Monolithic Microwave Integrated Circuit (MMIC)↗
Spacecraft Uplink, Downlink, and Intercommunications in a Space-Qualified ASIC Chip Set
This paper describes the functionality of four application specific integrated circuits (ASICs) developed for the Cassini spacecraft.
Spacecraft↗
Spaceborne multiprocessing seminar
Multiprocessor organization, integrated circuit techniques, self-repairing systems for spaceborne computer designs - conference
ON-LINE PROGRAMMING↗
Design for ASIC reliability for low-temperature applications
In this paper, we present a methodology to design for reliability for low temperature applications without requiring process improvement. The developed hot carrier aging lifetime projection model takes into account both the transistor substrate current profile and temperature profile to determine the minimum transistor size needed in order to meet reliability requirements. The methodology is applicable for automotive, military, and space applications, where there can be varying temperature ranges. A case study utilizing this methodology is given to design for reliability into a custom application-specific integrated circuit (ASIC) for a Mars exploration mission.
reliability↗
Design, development and fabrication of prototype semiconductor amplifiers Final report, 17 Mar. 1965 - 16 Mar. 1966
Fabrication of high temperature silicon carbide integrated circuit using junction-gate type field effect transistor as active component
JUNCTION TRANSISTOR↗
Rapid Selective Annealing of Cu Thin Films on Si Using Microwaves
A major goal of the semiconductor indurstry is to lower the processing temperatures needed for interconnects in silicon integrated circuits. Typical rapid thermal annealing processes heat the film as well as the substrate, creating device problems.
silicon integrated circuits microwave thin films↗
TTDAQ: A Continuous Flow, Timing and Trigger DAQ System
Final Scientific/Technical Report for DOE Award DE-SC0019581, “TTDAQ: A Continuous Flow, Timing and Trigger DAQ System.” The report summarizes Telluric Labs’ Phase II STTR work developing silicon-photonic building blocks for a software-defined, continuous-flow, trigger-less data acquisition system for next-generation high-energy and nuclear-physics detectors. The project focused on radiation-hard photonic integrated circuits, remote optical illumination, dense wavelength-division multiplexing, and a differential microring-resonator transceiver architecture designed to improve high-speed optical link stability and bandwidth. The report describes project objectives, technical accomplishments, AIM Photonics tape-outs, bench characterization, radiation-hardness testing, deferred integration work, and potential applications beyond physics readout.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
Defect filtering for thermal expansion induced dislocations in III–V lasers on silicon
Epitaxially integrated III–V semiconductor lasers for silicon photonics have the potential to dramatically transform information networks, but currently, dislocations limit performance and reliability even in defect-tolerant InAs quantum dot (QD)-based lasers. Despite being below the critical thickness, QD layers in these devices contain previously unexplained misfit dislocations, which facilitate non-radiative recombination. We demonstrate here that these misfit dislocations form during post-growth cooldown due to the combined effects of (1) thermal-expansion mismatch between the III–V layers and silicon and (2) mechanical hardening in the active region. By incorporating an additional sub-critical thickness, indium-alloyed “misfit dislocation trapping layer,” we leverage these mechanical hardening effects to our advantage, displacing 95% of misfit dislocations from the QD layer in model structures. Unlike conventional dislocation mitigation strategies, the trapping layer reduces neither the number of threading dislocations nor the number of misfit dislocations. It simply shifts the position of misfit dislocations away from the QD layer, reducing the defects' impact on luminescence. In full lasers, adding a misfit dislocation trapping layer both above and below the QD active region displaces misfit dislocations and substantially improves performance: we measure a twofold reduction in lasing threshold currents and a greater than threefold increase in output power. Overall, our results suggest that devices employing both traditional threading dislocation reduction techniques and optimized misfit dislocation trapping layers may finally lead to fully integrated, commercially viable silicon-based photonic integrated circuits.
36 MATERIALS SCIENCE↗
Tutorial on forming through-silicon vias
Through-silicon vias (TSVs) are a critical technology for three-dimensional integrated circuit technology. These through-substrate interconnects allow electronic devices to be stacked vertically for a broad range of applications and performance improvements such as increased bandwidth, reduced signal delay, improved power management, and smaller form-factors. There are many interdependent processing steps involved in the successful integration of TSVs. This article provides a tutorial style review of the following semiconductor fabrication process steps that are commonly used in forming TSVs: deep etching of silicon to form the via, thin film deposition to provide insulation, barrier, and seed layers, electroplating of copper for the conductive metal, and wafer thinning to reveal the TSVs. Recent work in copper electrochemical deposition is highlighted, analyzing the effect of accelerator and suppressor additives in the electrolyte to enable void-free bottom-up filling from a conformally lined seed metal.
42 ENGINEERING↗
W-band InP based HEMT MMIC low noise amplifiers
This paper presents the designs and measurement results of a three-stage and a four-stage W-band monolithic microwave integrated circuits (MMIC) including a three-stage and a four-stage low noise amplifiers.
monolithic microwave integrated circuits low noise↗
A 220-GHz InP HEMT Direct Detection Polarimeter
In this article, a 220-GHz direct detection polarimetric receiver is reported. This polarimetric receiver is intended for sensing of the microphysical properties of cloud ice in the earth's upper atmosphere. In the article, we report the measured RF performance, including RF gain of approximately 35 dB per channel and integrated noise figure of the receiver. The noise figure is measured to be 5.1 dB for the horizontally polarized channel and 5.4 dB for the vertically polarized channel. The receiver measures only 1.8 cm × 3.0 cm × 6.4 cm and has a total regulated dc power consumption of 520 mW. This article represents the first 220-GHz polarimetric direct detection receiver and is enabled by an advanced 25-nm indium phosphide (InP) HEMT monolithic microwave integrated circuit (MMIC) technology.
Indium phosphide (InP)↗