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At least 757 records · Page 42

Strategies for concurrent processing of complex algorithms in data driven architectures

The purpose is to document research to develop strategies for concurrent processing of complex algorithms in data driven architectures. The problem domain consists of decision-free algorithms having large-grained, computationally complex primitive operations. Such are often found in signal processing and control applications. The anticipated multiprocessor environment is a data flow architecture containing between two and twenty computing elements. Each computing element is a processor having local program memory, and which communicates with a common global data memory. A new graph theoretic model called ATAMM which establishes rules for relating a decomposed algorithm to its execution in a data flow architecture is presented. The ATAMM model is used to determine strategies to achieve optimum time performance and to develop a system diagnostic software tool. In addition, preliminary work on a new multiprocessor operating system based on the ATAMM specifications is described.

Stoughton, John W.↗

Software For Development Of Expert Systems

Modular software system helps create efficient artificial-intelligence computer programs. STAR*TOOL system: Set of high-level software tools; assists programmers in creation of efficient knowledge-based software systems. Provides language and capabilities for compilation of application programs written in Common LISP. Features modularity enabling elimination of unnecessary capabilities from final application program and achieves greater computing performance. Runs on any computer that supports Common LISP and has sufficient memory. Provides programmer with necessary software tools to build wide variety of reasoning and inference engines for such applications as planning, diagnosis and analysis, and simulation.

James, Mark L.↗

Statistical discrete particle simulation studies

A particle simulation code was developed that is suited to Multiple Instruction Multiple Data multiprocessor computers. The resulting code is designed to be portable between a large class of multiprocessor computer architectures, including hypercubes (e.g., Intel iPSC/860), shared memory machines (e.g., Cray, SGI, DASH), and simple uniprocessors (e.g., SUN, VAX, IBM PC). This code provides a powerful general framework that can be adapted to specific applications, such as thermomechanical modeling, general 3-D geometry support, or visualization support via a codeveloped CPlot data reduction and visualization system. Chemistry models were implemented and validated with comparison to continuum solutions of thermochemically relaxing gas mixtures and with experimental results from the high speed flow about a circular cylinder. Furthermore, the exchange of energy between translational and internal modes was modeled. New models were developed, combining greater efficiency than earlier phenomenological models. They offer greater physical detail by addressing vibrational energy as a discretely distributed quantity.

Mcdonald, Jeffrey D.↗

Redundant disk arrays: Reliable, parallel secondary storage

During the past decade, advances in processor and memory technology have given rise to increases in computational performance that far outstrip increases in the performance of secondary storage technology. Coupled with emerging small-disk technology, disk arrays provide the cost, volume, and capacity of current disk subsystems, by leveraging parallelism, many times their performance. Unfortunately, arrays of small disks may have much higher failure rates than the single large disks they replace. Redundant arrays of inexpensive disks (RAID) use simple redundancy schemes to provide high data reliability. The data encoding, performance, and reliability of redundant disk arrays are investigated. Organizing redundant data into a disk array is treated as a coding problem. Among alternatives examined, codes as simple as parity are shown to effectively correct single, self-identifying disk failures.

Gibson, Garth Alan↗

Preliminary efforts toward development of data handling and analysis software for unsteady flow measurements: An application for aeroelastic transonic flow configurations

A few years ago the Structural Dynamics Division at LaRC started ambitious experimental research efforts known as the Benchmark Models Program. The primary objective of this program was to provide experimental data that may serve as a calibration source for computational fluid dynamics (CFD) efforts that deal with aeroelastic unsteady flow configurations. It also focuses on the understanding of complex flow phenomenon associated with unsteady flow developments. The overall plan for the program has been described by Bennett, including a presentation of initial test results of flutter of a rigid wing mounted on flexible supports. An example of a test model employed to measure the dynamic response along with corresponding pressure distributions is shown. This model incorporates eighty pressure transducers distributed along two spanwise stations. In addition, the models are equipped with four accelerometers and two strain gages. The data handling system for the Benchmark Model Program is under development. Several interactive computer routines designed for the user interface, dynamic memory allocation, unsteady flow measurements data extraction, and further data processing were developed. To present a few examples of measured data, the unsteady pressure distributions and the wing model dynamic response were plotted.

Finaish, Fathi↗

Robotic Assisted Microsurgery - RAMS FY'97

JPL and Microdexterity Systems collaborated to develop new surgical capabilities. They developed a Robot Assisted Microsurgery (RAM) tool for surgeons to use for operating on the eye, ear, brain, and blood vessels with unprecedented dexterity. A surgeon can hold the surgical instrument with motions of 6 degrees of freedom with an accuracy of 25 microns in a 70 cu cm workspace. In 1996 a demonstration was performed to remove a microscopic particle from a simulated eyeball. In 1997, tests were performed at UCLA to compare telerobotics with mechanical operations. In 5 out of 7 tests, the RAM tool performed with a significant improvement of preciseness over mechanical operation. New design features include: (1) amplified forced feedback; (2) simultaneous slave robot instrumentation; (3) index control switch on master handle; and (4) tool control switches. Upgrades include: (1) increase in computational power; and (2) installation of hard disk memory storage device for independent operation and independent operation of forceps. In 1997 a final demonstration was performed using 2 telerobotics simultaneously in a microsurgery suture procedure to close a slit in a thin sheet of latex rubber which extended the capabilities of microsurgery procedures. After completing trials and demonstrations for the FDA the potential benefits for thousands of operations will be exposed.

Source record↗

Spacecraft computer resource margin management

The conduction of the Project Galileo Orbiter, with 18 microcomputers and the equivalent of 360K 8-bit bytes of memory contained within two major engineering subsystems and eight science instruments, requires that the key onboard computer system resources be managed in a very rigorous manner. Attention is given to the rationale behind the project policy, the development stage, the preliminary design stage, the design/implementation stage, and the optimization or 'scrubbing' stage. The implementation of the policy is discussed, taking into account the development of the Attitude and Articulation Control Subsystem (AACS) and the Command and Data Subsystem (CDS), the reporting of margin status, and the response to allocation oversubscription.

Larman, B. T.↗

The Remote Analysis Station (RAS) as an instructional system

"Hands-on" training in LANDSAT data analysis techniques can be obtained using a desk-top, interactive remote analysis station (RAS) which consists of a color CRT imagery display, with alphanumeric overwrite and keyboard, as well as a cursor controller and modem. This portable station can communicate via modem and dial-up telephone with a host computer at 1200 baud or it can be hardwired to a host computer at 9600 baud. A Z80 microcomputer controls the display refresh memory and remote station processing. LANDSAT data is displayed as three-band false-color imagery, one-band color-sliced imagery, or color-coded processed imagery. Although the display memory routinely operates at 256 x 256 picture elements, a display resolution of 128 x 128 can be selected to fill the display faster. In the false color mode the computer packs the data into one 8-bit character. When the host is not sending pictorial information the characters sent are in ordinary ASCII code. System capabilities are described.

Rogers, R. H.↗

Measurement-based performance evaluation technique for high-performance computers

A measurement-based performance evaluation technique has been used to characterize the OS performance of Cedar, a hierarchical shared-memory multiprocessor system. Thirteen OS performance meters were used to capture the operating system activities for compute-bound workloads. Three representative applications from the Perfect Benchmark Suite were used to measure the OS performance in a dedicated system and in multiprogrammed workloads. It was found that 13-23 percent of the total execution time on a dedicated system was spent in executing OS-related activities. Under multiprogramming, 12-14 percent of the total execution time was used by the OS. The impact of multiprogramming on the operating system performance meters was also measured.

Sharma, S.↗

An interface between a datametrics 1085A manometer and a Hewlett-Packard 2100S computer

A hardware/software interface designed to mate a Datametrics models 1085A electronic manometer to a Hewlett-Packard (HP) model 2100S computer is described. The software driver operates in the basic control system (BCS) and requires 173 words of memory; the hardware interface uses an HP data source interface (DSI) card which requires one computer input/output channel. Results obtained by incorporating this interface into a data acquisition system indicate that the interface operates successfully.

Hillard, M. E., Jr.↗

Application of supercomputers to computational aerodynamics

Computers are playing an increasingly important role in the field of aerodynamics such that they now serve as a major complement to wind tunnels in aerospace research and development. Factors pacing advances in computational aerodynamics are identified, including the amount of computational power required to take the next major step in the discipline. Example results obtained from the successively refined forms of the governing equations are discussed, both in the context of levels of computer power required and the degree to which they either further the frontiers of research or apply to problems of practical importance. Finally, the Numerical Aerodynamic Simulation (NAS) Program - with its 1988 target of achieving a sustained computational rate of 1 billion floating point operations per second and operating with a memory of 240 million words - is discussed in terms of its goals and its projected effect on the future of computational aerodynamics.

Peterson, V. L.↗

A Multi-Level Parallelization Concept for High-Fidelity Multi-Block Solvers

The integration of high-fidelity Computational Fluid Dynamics (CFD) analysis tools with the industrial design process benefits greatly from the robust implementations that are transportable across a wide range of computer architectures. In the present work, a hybrid domain-decomposition and parallelization concept was developed and implemented into the widely-used NASA multi-block Computational Fluid Dynamics (CFD) packages implemented in ENSAERO and OVERFLOW. The new parallel solver concept, PENS (Parallel Euler Navier-Stokes Solver), employs both fine and coarse granularity in data partitioning as well as data coalescing to obtain the desired load-balance characteristics on the available computer platforms. This multi-level parallelism implementation itself introduces no changes to the numerical results, hence the original fidelity of the packages are identically preserved. The present implementation uses the Message Passing Interface (MPI) library for interprocessor message passing and memory accessing. By choosing an appropriate combination of the available partitioning and coalescing capabilities only during the execution stage, the PENS solver becomes adaptable to different computer architectures from shared-memory to distributed-memory platforms with varying degrees of parallelism. The PENS implementation on the IBM SP2 distributed memory environment at the NASA Ames Research Center obtains 85 percent scalable parallel performance using fine-grain partitioning of single-block CFD domains using up to 128 wide computational nodes. Multi-block CFD simulations of complete aircraft simulations achieve 75 percent perfect load-balanced executions using data coalescing and the two levels of parallelism. SGI PowerChallenge, SGI Origin 2000, and a cluster of workstations are the other platforms where the robustness of the implementation is tested. The performance behavior on the other computer platforms with a variety of realistic problems will be included as this on-going study progresses.

Hatay, Ferhat F.↗

An iterative approach to region growing using associative memories

Region growing, often given as a classical example of the recursive control structures used in image processing which are often awkward to implement in hardware where the intent is the segmentation of an image at raster scan rates, is addressed in light of the postulate that any computation which can be performed recursively can be performed easily and efficiently by iteration coupled with association. Attention is given to an algorithm and hardware structure able to perform region labeling iteratively at scan rates. Every pixel is individually labeled with an identifier which signifies the region to which it belongs. Difficulties otherwise requiring recursion are handled by maintaining an equivalence table in hardware transparent to the computer, which reads the labeled pixels. A simulation of the associative memory has demonstrated its effectiveness.

Snyder, W. E.↗

Single event upset vulnerability of selected 4K and 16K CMOS static RAM's

Upset thresholds for bulk CMOS and CMOS/SOS RAMS were deduced after bombardment of the devices with 140 MeV Kr, 160 MeV Ar, and 33 MeV O beams in a cyclotron. The trials were performed to test prototype devices intended for space applications, to relate feature size to the critical upset charge, and to check the validity of computer simulation models. The tests were run on 4 and 1 K memory cells with 6 transistors, in either hardened or unhardened configurations. The upset cross sections were calculated to determine the critical charge for upset from the soft errors observed in the irradiated cells. Computer simulations of the critical charge were found to deviate from the experimentally observed variation of the critical charge as the square of the feature size. Modeled values of series resistors decoupling the inverter pairs of memory cells showed that above some minimum resistance value a small increase in resistance produces a large increase in the critical charge, which the experimental data showed to be of questionable validity unless the value is made dependent on the maximum allowed read-write time.

Kolasinski, W. A.↗

Demonstration of Cost-Effective, High-Performance Computing at Performance and Reliability Levels Equivalent to a 1994 Vector Supercomputer

The Affordable High Performance Computing (AHPC) project demonstrated that high-performance computing based on a distributed network of computer workstations is a cost-effective alternative to vector supercomputers for running CPU and memory intensive design and analysis tools. The AHPC project created an integrated system called a Network Supercomputer. By connecting computer work-stations through a network and utilizing the workstations when they are idle, the resulting distributed-workstation environment has the same performance and reliability levels as the Cray C90 vector Supercomputer at less than 25 percent of the C90 cost. In fact, the cost comparison between a Cray C90 Supercomputer and Sun workstations showed that the number of distributed networked workstations equivalent to a C90 costs approximately 8 percent of the C90.

Babrauckas, Theresa↗

Avoiding and tolerating latency in large-scale next-generation shared-memory multiprocessors

A scalable solution to the memory-latency problem is necessary to prevent the large latencies of synchronization and memory operations inherent in large-scale shared-memory multiprocessors from reducing high performance. We distinguish latency avoidance and latency tolerance. Latency is avoided when data is brought to nearby locales for future reference. Latency is tolerated when references are overlapped with other computation. Latency-avoiding locales include: processor registers, data caches used temporally, and nearby memory modules. Tolerating communication latency requires parallelism, allowing the overlap of communication and computation. Latency-tolerating techniques include: vector pipelining, data caches used spatially, prefetching in various forms, and multithreading in various forms. Relaxing the consistency model permits increased use of avoidance and tolerance techniques. Each model is a mapping from the program text to sets of partial orders on program operations; it is a convention about which temporal precedences among program operations are necessary. Information about temporal locality and parallelism constrains the use of avoidance and tolerance techniques. Suitable architectural primitives and compiler technology are required to exploit the increased freedom to reorder and overlap operations in relaxed models.

Probst, David K.↗

Run-time scheduling and execution of loops on message passing machines

Sparse system solvers and general purpose codes for solving partial differential equations are examples of the many types of problems whose irregularity can result in poor performance on distributed memory machines. Often, the data structures used in these problems are very flexible. Crucial details concerning loop dependences are encoded in these structures rather than being explicitly represented in the program. Good methods for parallelizing and partitioning these types of problems require assignment of computations in rather arbitrary ways. Naive implementations of programs on distributed memory machines requiring general loop partitions can be extremely inefficient. Instead, the scheduling mechanism needs to capture the data reference patterns of the loops in order to partition the problem. First, the indices assigned to each processor must be locally numbered. Next, it is necessary to precompute what information is needed by each processor at various points in the computation. The precomputed information is then used to generate an execution template designed to carry out the computation, communication, and partitioning of data, in an optimized manner. The design is presented for a general preprocessor and schedule executer, the structures of which do not vary, even though the details of the computation and of the type of information are problem dependent.

Crowley, Kay↗