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At least 757 records · Page 42

Parasail: SIMD C library for global, semi-global, and local pairwise sequence alignments

Sequence alignment algorithms are a key component of many bioinformatics applications. Though various fast Smith-Waterman local sequence alignment implementations have been developed for x86 CPUs, most are embedded into larger database search tools. In addition, fast implementations of Needleman-Wunsch global sequence alignment and its semi-global variants are not as widespread. This article presents the first software library for local, global, and semi-global pairwise intra-sequence alignments and improves the performance of previous intra-sequence implementations. As a result, a faster intra-sequence pairwise alignment implementation is described and benchmarked. Using a 375 residue query sequence a speed of 136 billion cell updates per second (GCUPS) was achieved on a dual Intel Xeon E5-2670 12-core processor system, the highest reported for an implementation based on Farrar’s ’striped’ approach. When using only a single thread, parasail was 1.7 times faster than Rognes’s SWIPE. For many score matrices, parasail is faster than BLAST. The software library is designed for 64 bit Linux, OS X, or Windows on processors with SSE2, SSE41, or AVX2. Source code is available from https://github.com/jeffdaily/parasail under the Battelle BSD-style license. In conclusion, applications that require optimal alignment scores could benefit from the improved performance. For the first time, SIMD global, semi-global, and local alignments are available in a stand-alone C library.

97 MATHEMATICS AND COMPUTING↗

Quantum search on noisy intermediate-scale quantum devices

Abstract Quantum search algorithm (also known as Grover's algorithm) lays the foundation for many other quantum algorithms. Although it is very simple, its implementation is limited on noisy intermediate-scale quantum (NISQ) processors. Grover's algorithm was designed without considering the physical resources, such as depth, in the real implementations. Therefore, Grover's algorithm can be improved for NISQ devices. In this paper, we demonstrate how to implement quantum search algorithms better on NISQ devices. We present detailed benchmarks of the five-qubit quantum search algorithm on different quantum processors, including IBMQ, IonQ, and Honeywell quantum devices. We report the highest success probability of the five-qubit search algorithm compared to previous works. Our results show that designing the error-aware quantum search algorithms is possible, which can maximally harness the power of NISQ computers.

Physics↗

Frontier Job-Centric Telemetry Dataset

Comprehensive analysis of high-performance computing (HPC) systems requires linking workload execution to system behavior. This kind of analysis is vital for diagnosing performance issues, managing capacity, detecting anomalous workloads, and understanding how applications interact with system hardware. This job-centric telemetry dataset unifies scheduler job records with node-level measurements, enabling direct association between workloads and their corresponding power, thermal, and performance characteristics. It contains sanitized, scheduler related metadata for 152,400 individual jobs that ran on the Frontier supercomputer and ended on selected days throughout 2024 and 2025, a subpopulation of ~6.8% of the total number of allocated jobs with non-zero run time on the system over that same period. Each is linked with files that contain telemetry time series records of the power utilization and temperature behavior of its allocated nodes and their processors during the run time of the job. Where available, a portion of the job files also contain network performance time series. Jobs are sampled from select days that reflect normal levels of user activity and possess job size distributions with large numbers of leadership class jobs (>20% of Frontier nodes). Jobs in this dataset attempt to best represent successful user workflows.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

Neutron multiplicity counting: Confidence intervals for reconstruction parameters

From nuclear materials accountability to homeland security, the need for improved nuclear material detection, assay, and authentication has grown over the past decades. Starting in the 1940s, neutron multiplicity counting techniques have enabled quantitative evaluation of masses and multiplications of fissile materials. In this paper, we propose a new method to compute uncertainties on these parameters using a model-based sequential Bayesian processor, resulting in credible regions in the fissile material mass and multiplication space. These uncertainties will enable us to evaluate quantitatively proposed improvements to the theoretical fission chain model. Additionally, because the processor can calculate uncertainties in real time, it is a useful tool in applications such as portal monitoring: monitoring can stop as soon as a preset confidence of non-threat is reached.

11 NUCLEAR FUEL CYCLE AND FUEL MATERIALS↗

Increased phase precision of spatial light modulators using irrational slopes: application to attosecond metrology

The ability of spatial light modulators (SLMs) to modify the amplitude and phase of light has proved them invaluable to the optics and photonics community. In many applications, the bit-depth of SLMs is a major limiting factor dictated by a digital processor. As a result, there is usually a compromise between refresh speed and bit-depth. Here, we present a method to increase the effective bit-depth of SLMs, which utilizes a linear slope, as is commonly applied to deal with the zeroth-order effect. This technique was tested using two interferometric transient absorption spectroscopy setups. Through the high harmonic generation in gases producing a train of attosecond pulses and harmonics from solids in the ultraviolet, two pulses are generated that interfere in the far field providing a measurement of the optical phase. An increase in the precision far beyond the limit dictated by the digital processor in the bit-depth was found.

Harrison, Geoffrey R. (ORCID:0000000152141866)↗

Vintage electronics for trusted radiation measurements and verified dismantlement of nuclear weapons

Information barriers are trusted measurement systems to confirm the authenticity of nuclear warheads based on their radiation signatures. Traditional inspection systems rely on complex electronics both for data acquisition and processing. Several research efforts have produced prototype systems, but it has proven difficult to demonstrate that hidden switches and side channels do not exist. After almost thirty years of research and development, no viable and widely accepted system has emerged. We pursue a fundamentally different approach: Our prototype of an inspection system uses vintage hardware built around a 6502 processor. The processor uses 8-micron technology and has only about 4,200 transistors. Vintage electronics may have a number of important advantages for applications where two parties need to simultaneously establish trust in the hardware used. CPUs designed in the distant past, at a time when their use for sensitive measurements was never envisioned, drastically reduce concerns that the other party implemented backdoors or hidden switches on the hardware level. We demonstrate the performance of a prototype system using an Apple IIe and a custom-made open-source data-processing board connected to a standard sodiumiodide radiation detector for low-resolution gamma spectroscopy. Data processing and analysis is exclusively done on the Apple IIe hardware. We show that subtle differences in radiation signatures can be detected in 2–3 minutes based on the result of a simple chi-squared test. Vintage electronics may therefore offer a new path toward fieldable, trusted information barriers.

98 NUCLEAR DISARMAMENT, SAFEGUARDS, AND PHYSICAL P↗

Recovery Act: SeaMicro Volume Server Power Reduction Research Development

Cloud data centers are projected to be the fastest growing segment of the server market through 2015, according to IDC. Increasingly people and businesses rely on the Cloud to deliver digital content quickly and efficiently. Recovery Act funding from the Department of Energy has helped SeaMicro's technologies enhance the total cost of operation, performance and energy efficiency in large data center and Cloud environments. SeaMicro's innovative supercomputer fabric connects thousands of processor cores, memory, storage and input/output traffic. The company's fabric supports multiple processor instruction sets. Current systems featuring SeaMicro technology typically use one quarter the power and take one sixth the space of traditional servers with the same compute performance, yet deliver up to 12 times the bandwidth per core. Mozilla and eHarmony are two customers successfully using SeaMicro's technology. Numerous non-public customers have been successfully using the SeaMicro product in test and production facilities. As a result of the Recovery Act funding from the U.S. Department of Energy, more than 50 direct jobs were created at SeaMicro. To date, they primarily have been high-value, engineering jobs. Hardware, software and manufacturing engineering positions have been created, as well as sales and sales engineering. The positions have allowed SeaMicro to significantly accelerate engineering development and accelerate commercialization. As a result, commercialization and delivery to market are months ahead of initial schedule. Additional jobs were indirectly created through the development of the SeaMicro product. Through many years of research and hard work prior to receipt of public funding, SeaMicro was awarded 2 patents for its work. SeaMicro's product led the way for industry leaders to reconsider the market for low power servers and create new product lines. With valuable support of the U.S. Department of Energy and through SeaMicro's product, the market has been reshaped by the company's unique approach and ground breaking technology.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

UNAP DCM Theory of Operations

The UNAP DCM board is capable of measuring currents with a dynamic range of 3 x 10 -14 A to 3 x 10 -4 A. The design of the DCM closely matches the proven N-1 minigrand family DCM design. The most significant difference is the replacement of the Actel FPGA with an SPI I/O expander. The original DCM design used an Actel FPGA to communicate with the processor over the expansion bus controling the DCM gain and filtering. The UNAP processor communicates with the UDA FPGA over the cPCI bus. The UNAP DCM control functions are accomplished in the UDA FPGA and communicated to the DCM board via an SPI bus.

98 NUCLEAR DISARMAMENT, SAFEGUARDS, AND PHYSICAL P↗

Xyce TM Parallel Electronic Simulator: Users’ Guide, Version 5.3

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: ■ Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). Note that this includes support for most popular parallel and serial computers. ■ Improved performance for all numerical kernels (e.g., time integrator, nonlinear and linear solvers) through state-of-the-art algorithms and novel techniques. ■ Device models which are specifically tailored to meet Sandia’s needs, including some radiation-aware devices (for Sandia users only). ■ Object-oriented code design and implementation using modern coding practices that ensure that the Xyce Parallel Electronic Simulator will be maintainable and extensible far into the future. Xyce is a parallel code in the most general sense of the phrase - a message passing parallel implementation - which allows it to run efficiently on the widest possible number of computing platforms. These include serial, shared-memory and distributed-memory parallel as well as heterogeneous platforms. Careful attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows. The development of Xyce provides a platform for computational research and development aimed specifically at the needs of the Laboratory. With Xyce, Sandia has an “in-house” capability with which both new electrical (e.g., device model development) and algorithmic (e.g., faster time-integration methods, parallel solver algorithms) research and development can be performed. As a result, Xyce is a unique electrical simulation capability, designed to meet the unique needs of the laboratory

42 ENGINEERING↗

Multi-Instrument Collect User’s Manual (Version 2.0.0.8)

The Multi-Instrument Collect, MIC, program is designed for unattended collection and saving of data from multiple, distributed data acquisition instruments. It is highly configurable, supporting collection of data from up to 128 instruments on up to 128 communications channels. MIC also provides the ability to copy data to removable disks for exporting the data it collects. MIC is a complex state-of-the-art multi-tasking application. It is designed to function on a fast multi-processor system but can run adequately on a single-processor platform.

Nuclear Disarmament, Safeguards, & Physical Protec↗

Cayuga County Regional Digester: Vision Becomes Reality. Final Report

With an average herd size of 113 mature cows, Cayuga County is home to 280 dairy farms and 31,500 dairy milking cows producing approximately 855 million gallons of milk per year. The Cayuga Dairy industry is a major contributor to the countys economy, employing nearly 1200 people, while generating $140,000,000 of revenue from sale of milk alone. At the same time, the Cayuga County dairy industry also produces 5.7 million gallons of manure daily: (a) Nearly 34% of this manure is produced on smaller farms. (b) Digesters are expensive pieces of equipment and require attention and care. ( c) The on-farm digester systems have fairly long payback (>10 years) even for larger CAFO farms (>1000 milking cows). In 2005, Cayuga County Soil and Water Conservation District (The District), a Public Agency under Cayuga County, decided to undertake a centralized community digester project. The primary goal of the project was to develop an economically sustainable model, under the auspices of The District to address manure management issues facing the smaller dairies, improve the water quality and improve the quality of life for Cayuga County residents. It is believed that the District has accomplished this goal by completing construction of Cayuga County Regional Digester on a parcel of land behind the Cayuga County Natural Resource Center located at 7413 County House Road in the Town of Sennett in Cayuga County, New York. The digester facility consists of the following major components. 1. Transfer Station: This an indoor truck bay, where 35,000 gallons of manure from three local farms, 8,500 gallons of liquid organic food-processor waste, and 1,200 gallons of brown grease are unloaded from tanker trucks and the digested slurry is loaded onto the tanker trucks for delivery back to the participating farms. 2. Anaerobic Digester: The project utilizes a hydraulic mix anaerobic digester, a unique design that has no internal moving parts for mixing. The digester, which operates at mesophilic temperatures, is designed to process the daily feedstock and produce 220,000 SCF2 of biogas per day. The digester also produces 44,000 gallons of digested slurry per day. 3. Biogas Conditioning System: The plant employs a biological biogas conditioning system to remove the H2S and moisture contents of the biogas and prepare it to be used by the plant generation system. 4. Combined Heat and Power System (CHP): This is a 633kW high efficiency biogas-fired GE-Jenbacher model JMS-312 GS-NL reciprocating engine cogeneration system. The heat recovery system incorporated into the package is designed to capture the waste heat from the engine exhaust, the jacket cooling water and the engine oil circuit. 5. Electrical Substation and Power Distribution Systems: An electrical distribution system has been constructed on-site that aggregates the electrical service of the different county buildings on the District campus into a county owned electric distribution system that is interconnected with the CHP and the local electric grid. The electrical system is designed, in accordance with the utility guidelines, to allow grid-parallel operation of CHP and provide for import and export of electric power. 6. Thermal Energy Distribution System: The heat recovery system has been integrated into a high temperature water distribution system that distributes the heat to the thermal circuits for the anaerobic digester facility. Additional piping has also been installed to transfer the remaining thermal energy to other county buildings on the campus. On a daily basis, the plant will co-process 35,000 gallons of manure from local dairy farms, 8,500 gallons of food-processor waste and 1,200 gallons of brown grease to produce 200,000 ft3/d of biogas and 44,000 gallons of pathogen-free nutrient-rich digested slurry for agricultural use by farms and in the local area.The biogas fueled CHP produces 5,157,000 kWh of electricity and 19,506 dekatherms of thermal energy per year. Electrical power generated by the cogeneration system powers all the buildings on the Cayuga County campus and any surplus power is exported to the grid under a power purchase agreement. Heat recovered from the cogeneration system will be used to maintain the temperature of the process equipment and the excess will be transported to the Cayuga County Public Safety Building to offset purchase of fossil fuel to fuel the boilers. The majority of plant operations are unmanned and automated. However, the plant will have a small staff of well-trained personnel to coordinate the feedstock deliveries and shipments, supervise the day-to-day operation, monitor the systems and perform maintenance, maintain a safe and reliable operation and to respond to emergencies.

09 BIOMASS FUELS↗

In-Situ Statistical Analysis of Autotune Simulation Data using Graphical Processing Units

Developing accurate building energy simulation models to assist energy efficiency at speed and scale is one of the research goals of the Whole-Building and Community Integration group, which is a part of Building Technologies Research and Integration Center (BTRIC) at Oak Ridge National Laboratory (ORNL). The aim of the Autotune project is to speed up the automated calibration of building energy models to match measured utility or sensor data. The workflow of this project takes input parameters and runs EnergyPlus simulations on Oak Ridge Leadership Computing Facility’s (OLCF) computing resources such as Titan, the world’s second fastest supercomputer. Multiple simulations run in parallel on nodes having 16 processors each and a Graphics Processing Unit (GPU). Each node produces a 5.7 GB output file comprising 256 files from 64 simulations. Four types of output data covering monthly, daily, hourly, and 15- minute time steps for each annual simulation is produced. A total of 270TB+ of data has been produced. In this project, the simulation data is statistically analyzed in-situ using GPUs while annual simulations are being computed on the traditional processors. Titan, with its recent addition of 18,688 Compute Unified Device Architecture (CUDA) capable NVIDIA GPUs, has greatly extended its capability for massively parallel data processing. CUDA is used along with C/MPI to calculate statistical metrics such as sum, mean, variance, and standard deviation leveraging GPU acceleration. The workflow developed in this project produces statistical summaries of the data which reduces by multiple orders of magnitude the time and amount of data that needs to be stored. These statistical capabilities are anticipated to be useful for sensitivity analysis of EnergyPlus simulations

accelerators↗

Xyce parallel electronic simulator users guide, version 6.0.

This manual describes the use of the Xyce Parallel Electronic Simulator. Xyce has been designed as a SPICE-compatible, high-performance analog circuit simulator, and has been written to support the simulation needs of the Sandia National Laboratories electrical designers. This development has focused on improving capability over the current state-of-the-art in the following areas: Capability to solve extremely large circuit problems by supporting large-scale parallel computing platforms (up to thousands of processors). This includes support for most popular parallel and serial computers. A differential-algebraic-equation (DAE) formulation, which better isolates the device model package from solver algorithms. This allows one to develop new types of analysis without requiring the implementation of analysis-specific device models. Device models that are specifically tailored to meet Sandia s needs, including some radiationaware devices (for Sandia users only). Object-oriented code design and implementation using modern coding practices. Xyce is a parallel code in the most general sense of the phrase a message passing parallel implementation which allows it to run efficiently a wide range of computing platforms. These include serial, shared-memory and distributed-memory parallel platforms. Attention has been paid to the specific nature of circuit-simulation problems to ensure that optimal parallel efficiency is achieved as the number of processors grows.

Keiter, Eric R↗

SBIR PHASE I FINAL REPORT: Adoption of High Performance Computational (HPC) Modeling Software for Widespread Use in the Manufacture of Welded Structures

Many US manufacturing companies have moved fabrication and production facilities off shore because of cheaper labor costs. A key aspect in bringing these jobs back to the US is the use of technology to render US-made fabrications more efficient overall with higher quality. A new initiative of the current administration has the goal of enhancing competitiveness to retain manufacturing jobs in the US. One significant competitive advantage that has emerged in the US over the last two decades is the use of virtual design for fabrication of large structures in the light and heavy materials industries. Industries that have used virtual design and analysis tools have reduced material parts size, developed environmentally-friendly fabrication processes, improved product quality and performance, and reduced manufacturing costs. Indeed, Caterpillar Inc. (CAT), one of the partners in this effort, continues to have a large fabrication presence in the US because of the use of weld fabrication modeling to optimize fabrications by controlling weld residual stresses and distortions and improving fatigue, corrosion, and fracture performance. This report describes Engineering Mechanics Corporation of Columbus (Emc2's) DOE SBIR Phase I results which extended an existing, state-of-the-art software code, VFT, currently used to design and model large welded structures prior to fabrication - to a broader range of products with widespread applications for small and medium-sized enterprises (SMEs). VFT helps control distortion, can minimize and/or control residual stresses, control welding microstructure, and pre-determine welding parameters such as weld-sequencing, pre-bending, thermal-tensioning, etc. VFT uses material properties, consumable properties, etc. as inputs. Through VFT, manufacturing companies can avoid costly design changes after fabrication. This leads to the concept of joint design/fabrication where these important disciplines are intimately linked to minimize fabrication costs. VFT currently is tied to a commercial solver which makes it prohibitively expensive for use by SMEs, as there is a significant licensing cost for the solver - over and above for the relatively minimal cost for VFT. Emc2 developed this software code over a number of years in close cooperation with CAT (Peoria, IL), who currently uses this code exclusively for worldwide fabrication, product design and development activities. The use of VFT has allowed CAT to move directly from design to product fabrication and helped eliminate (to a large extent) new product prototyping and subsequent testing. Additionally, CAT has been able to eliminate/reduce costly one-of-a-kind appliances used to reduce distortion effects due to fabrication. In this context, SMEs can realize the same kind of improved product quality and reduced cost through adoption of the adapted version of VFT for design and subsequent manufacture of new products. Emc2's DOE SBIR Phase I effort successfully adapted VFT so that SMEs have access to this sophisticated and proven methodology that is quick, accurate and cost effective and available on-demand to address weld-simulation and fabrication problems prior to manufacture. The open source code, WARP3D, a high performance finite element code mainly used in fracture and damage assessment of structures, was modified so that computational weld problems can be solved efficiently on multiple processors and threads with VFT. The thermal solver for VFT, based on a series of closed form solution approximations, was enhanced for solution on multiple processors greatly increasing overall speed. In addition, the graphical user interface (GUI) has been tailored to integrate these solutions with WARP3D. The GUI is used to define all the weld pass descriptions, number of passes, material properties, consumable properties, weld speed, etc. for the structure to be modeled. The GUI was improved to make it user-friendly for engineers that are not experts in finite element modeling. Finally, a plan for porting VFT onto the Ohio Supercomputer Center (OSC) through its hosted Manufacturing and Polymer Portal has been developed. This access route will permit SMEs to perform weld modeling to improve their competitiveness at a reasonable cost. All of these improvements are detailed in this repo

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

Automated Cache Performance Analysis And Optimization

While there is no lack of performance counter tools for coarse-grained measurement of cache activity, there is a critical lack of tools for relating data layout to cache behavior to application performance. Generally, any nontrivial optimizations are either not done at all, or are done ”by hand” requiring significant time and expertise. To the best of our knowledge no tool available to users measures the latency of memory reference instructions for particular addresses and makes this information available to users in an easy-to-use and intuitive way. In this project, we worked to enable the Open|SpeedShop performance analysis tool to gather memory reference latency information for specific instructions and memory addresses, and to gather and display this information in an easy-to-use and intuitive way to aid performance analysts in identifying problematic data structures in their codes. This tool was primarily designed for use in the supercomputer domain as well as grid, cluster, cloud-based parallel e-commerce, and engineering systems and middleware. Ultimately, we envision a tool to automate optimization of application cache layout and utilization in the Open|SpeedShop performance analysis tool. To commercialize this software, we worked to develop core capabilities for gathering enhanced memory usage performance data from applications and create and apply novel methods for automatic data structure layout optimizations, tailoring the overall approach to support existing supercomputer and cluster programming models and constraints. In this Phase I project, we focused on infrastructure necessary to gather performance data and present it in an intuitive way to users. With the advent of enhanced Precise Event-Based Sampling (PEBS) counters on recent Intel processor architectures and equivalent technology on AMD processors, we are now in a position to access memory reference information for particular addresses. Prior to the introduction of PEBS counters, cache behavior could only be measured reliably in the aggregate across tens or hundreds of thousands of instructions. With the newest iteration of PEBS technology, cache events can be tied to a tuple of instruction pointer, target address (for both loads and stores), memory hierarchy, and observed latency. With this information we can now begin asking questions regarding the efficiency of not only regions of code, but how these regions interact with particular data structures and how these interactions evolve over time. In the short term, this information will be vital for performance analysts understanding and optimizing the behavior of their codes for the memory hierarchy. In the future, we can begin to ask how data layouts might be changed to improve performance and, for a particular application, what the theoretical optimal performance might be. The overall benefit to be produced by this effort was a commercial quality easy-to- use and scalable performance tool that will allow both beginner and experienced parallel programmers to automatically tune their applications for optimal cache usage. Effective use of such a tool can literally save weeks of performance tuning effort. Easy to use. With the proposed innovations, finding and fixing memory performance issues would be more automated and hide most to all of the performance engineer expertise ”under the hood” of the Open|SpeedShop performance tool. One of the biggest public benefits from the proposed innovations is that it makes performance analysis more usable to a larger group of application developers. Intuitive reporting of results. The Open|SpeedShop performance analysis tool has a rich set of intuitive, yet detailed reports for presenting performance results to application developers. Our goal was to leverage this existing technology to present the results from our memory performance addition to Open|SpeedShop. Suitable for experts as well as novices. Application performance is getting more difficult to measure as the hardware platforms they run on become more complicated. This makes life difficult for the application developer, in that they need to know more about the hardware platform, including the memory system hierarchy, in order to understand the performance of their application. Some application developers are comfortable in that sceario, while others want to do their scientific research and not have to understand all the nuances in the hardware platform they are running their application on. Our proposed innovations were aimed to support both experts and novice performance analysts. Useful in many markets. The enhancement to Open|SpeedShop would appeal to a broader market space, as it will be useful in scientific, commercial, and cloud computing environments. Our goal was to use technology developed initially at the and Lawrence Livermore National Laboratory combined with the development and commercial software experience of the Argo Navis Technologies, LLC (ANT) to form a powerful combination to delivery these objectives.

97 MATHEMATICS AND COMPUTING↗

Scalable Domain Decomposed Monte Carlo Particle Transport

In this dissertation, we present the parallel algorithms necessary to run domain decomposed Monte Carlo particle transport on large numbers of processors (millions of processors). Previous algorithms were not scalable, and the parallel overhead became more computationally costly than the numerical simulation.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

A pervasive parallel framework for visualization: final report for FWP 10-014707

We are on the threshold of a transformative change in the basic architecture of highperformance computing. The use of accelerator processors, characterized by large core counts, shared but asymmetrical memory, and heavy thread loading, is quickly becoming the norm in high performance computing. These accelerators represent significant challenges in updating our existing base of software. An intrinsic problem with this transition is a fundamental programming shift from message passing processes to much more fine thread scheduling with memory sharing. Another problem is the lack of stability in accelerator implementation; processor and compiler technology is currently changing rapidly. This report documents the results of our three-year ASCR project to address these challenges. Our project includes the development of the Dax toolkit, which contains the beginnings of new algorithms for a new generation of computers and the underlying infrastructure to rapidly prototype and build further algorithms as necessary.

97 MATHEMATICS AND COMPUTING↗

Authenticating cache

The aim of the Authenticating Cache architecture is to ensure that machine instructions in a Read Only Memory (ROM) are legitimate from the time the ROM image is signed (immediately after compilation) to the time they are placed in the cache for the processor to consume. The proposed architecture allows the detection of ROM image modifications during distribution or when it is loaded into memory. It also ensures that modified instructions will not execute in the processor-as the cache will not be loaded with a page that fails an integrity check. The authenticity of the instruction stream can also be verified in this architecture. The combination of integrity and authenticity assurance greatly improves the security profile of a system.

97 MATHEMATICS AND COMPUTING↗