Results for “processors” — Page 41

DOE OSTI2021

VTK-m User's' Guide (V.1.7)

High-performance computing relies on ever finer threading. Advances in processor technology include ever greater numbers of cores, hyperthreading, accelerators with integrated blocks of cores, and special vectorized instructions, all of which require more software parallelism to achieve peak performance. Traditional visualization solutions cannot support this extreme level of concurrency. Extreme scale systems require a new programming model and a fundamental change in how we design algorithms. To address these issues we created VTK-m: the visualization toolkit for multi-/many-core architectures. VTK-m supports a number of algorithms and the ability to design further algorithms through a top-down design with an emphasis on extreme parallelism. VTK-m also provides support for finding and building links across topologies, making it possible to perform operations that determine manifold surfaces, interpolate generated values, and find adjacencies. Although VTK-m provides a simplified high-level interface for programming, its template-based code removes the overhead of abstraction. VTK-m simplifies the development of parallel scientific visualization algorithms by providing a framework of supporting functionality that allows developers to focus on visualization operations. Consider the listings in Figure 1.1 that compares the size of the implementation for the Marching Cubes algorithm in VTK-m with the equivalent reference implementation in the CUDA software development kit. Because VTK-m internally manages the parallel distribution of work and data, the VTK-m implementation is shorter and easier to maintain. Additionally, VTK-m provides data abstractions not provided by other libraries that make code written in VTK-m more versatile.This book includes contributions from the VTK-m community including the VTK-m development team and the user community.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2023

Crystal growth and nucleation at metal-organic framework / solution interfaces

Metal-organic frameworks (MOFs) represent an incredibly diverse class of materials with equally diverse applications in catalysis, separations, and gas storage. Despite the prevalence of MOF structures in the literature, in many cases the synthesis of pure, crystalline MOF materials remains a significant challenge, with failed syntheses often yielding mixed crystalline or non-porous amorphous products. Our recent work aims to enable targeted MOF synthesis by developing a comprehensive and predictive model of the fundamental processes occurring at the MOF-solution interface under synthetically-relevant conditions. Our recent accomplishments include: (i) development and implementation of a graphics processor-accelerated approach to simulation the nucleation of weak electrolytes, and the extension of these methods to large/complex solutes such as MOFs; and (ii) studies of the structure of ZIF interfaces under conditions relevant to crystal growth; and (iii) addressing important open questions in the mechanism of MOF solvent-assisted linker exchange, and important synthetic pathway for MOFs.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

DOE OSTI2022

Unified Memory: GPGPU-Sim/UVM Smart Integration

CPU/GPU heterogeneous compute platforms are an ubiquitous element in computing and a programming model specified for this heterogeneous computing model is important for both performance and programmability. A programming model that exposes the shared, unified, address space between the heterogeneous units is a necessary step in this direction as it removes the burden of explicit data movement from the programmer while maintaining performance. GPU vendors, such as AMD and NVIDIA, have released software-managed runtimes that can provide programmers the illusion of unified CPU and GPU memory by automatically migrating data in and out of the GPU memory. However, this runtime support is not included in GPGPU-Sim, a commonly used framework that models the features of a modern graphics processor that are relevant to non-graphics applications. UVM Smart was developed, which extended GPGPU-Sim 3.x to in- corporate the modeling of on-demand pageing and data migration through the runtime. This report discusses the integration of UVM Smart and GPGPU-Sim 4.0 and the modifications to improve simulation performance and accuracy.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

Vector-Matrix Multiplication Engine for Neuromorphic Computation with a CBRAM Crossbar Array [Slides]

The core function of many neural network algorithms is the dot product, or vector matrix multiply (VMM) operation. Crossbar arrays utilizing resistive memory elements can reduce computational energy in neural algorithms by up to five orders of magnitude compared to conventional CPUs. Moving data between a processor, SRAM, and DRAM dominates energy consumption. By utilizing analog operations to reduce data movement, resistive memory crossbars can enable processing of large amounts of data at lower energy than conventional memory architectures.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

Computer Science Research Needs for Parallel Discrete Event Simulation (PDES)

Historically, scientific computing efforts have demonstrated the clear need for, and effective use of, supercomputing with traditional time-stepped simulations. Nevertheless, there are several areas in the mission spaces of the U.S. Department of Energy and other agencies waiting to tap advanced computing research using a different, discrete event style of modeling, simulation, and analysis. These span a wide spectrum of applications including energy grid resilience, urban planning and policy, transportation science, building technologies, emergency response and planning, environmental impact analysis, computational epidemiology, Internet communications, cyber security, and cyber-physical systems, to name only a few. Even within traditional scientific applications, the role of discrete event modes of execution is increasing in the form of new event-based mathematical solvers such as quantized state integration methods and discrete-continuous hybrid system solvers. Co-design of advanced supercomputing hardware systems is another area that exploits discrete event simulation at its core for effective analyses. Complex systems, entity behaviors and interconnections play a significant role in all these applications, which are mapped to large-scale models with discrete event formulations. To make advancements in all the aforementioned scientific areas, many technical aspects need to be more thoroughly studied and deeply understood in parallel discrete event simulation (PDES). The unique dynamics inherent in a discrete event modeling approach, by their very nature, intersect and influence the entire stack of the computing system, including (a) the unique nature of the instruction sets exercised in PDES workloads without a predominance of high-precision floating point operations, (b) virtual time-constrained multi-threaded execution of many logical processes per processor, (c) extremely variable and difficult to predict network traffic characteristics, (d) interfaces and inter-dependencies with machine learning and artificial intelligence codes at higher software layers, and (e) highly challenging load balancing needs, especially in effectively accounting for accelerated/extremely heterogeneous computing in current and future high-performance computing systems. Efficient and accurate parallel execution of PDES workloads is also dominated by challenges in dealing with their asynchronous concurrency fundamentally present at the model level. Conservative synchronization, optimistic/speculative synchronization, and their hybrid schemes open new questions in fundamental computer science with respect to reversibility of computation and prediction (lookahead) of behaviors inherent within model codes. On the implementation front, there are relatively few scalable, general-purpose parallel discrete event simulators in the world, and even fewer have been studied on emerging hardware platforms. To enable scientific advances using PDES, the research needs in computer science must also be pursued and met in the intersection of the algorithmic and hardware-aware aspects of scalable PDES engines. This report is aimed at capturing a computer science-oriented view of this important area of research in PDES, presenting a sample of important applications with their inherent discrete event technology elements. Needs are outlined in core areas of parallel discrete event research as well as cross-cutting directions in computer science research that positively impact scientific advancements across several important application areas. A selection of priority research opportunities in advanced computing for PDES is identified to serve as reference for key research topics and their order of importance for scientific advancements.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2021

Bamboo Bio-composite Truck/Trailer Decking

Bamboo is one of the fastest growing plants in the world. Massively productive, bamboo will maintain that productivity with limited inputs and minimal management resulting in predictable volume and operating margins and with low overhead. The goal of this project was to develop a bamboo bio-composite trailer decking product that replaces apitong, is lighter weight, stronger and luminescent. The collaboration partners, Fontaine, Resource Fiber and IACMI, worked closely to develop the bamboo bio-composite decking to Fontaine Trailer’s (end-user) specifications. The various technological objectives were (a) To conduct a comprehensive Design of Experiments study for bamboo composites to understand the structure-property relationships for different resin composites and bamboo forms (strips, woven, bulk etc); (b) To establish the nail pull out characteristics of trailer deck geometry bamboo composite form. The nail pull out is a critical test in trailer decks; (c) To design, process and prototype select number of trailer decking planks for Fontaine evaluation; and (d) To conduct life cycle analysis to conduct energy calculations from the various conversion steps of the bamboo from crop to product. The project meets DOE/IACMI metrics of reduced embodied energy, lightweighting and lowering the cost of the end product. It also offers a green solution to a value-added application, i.e. trailer decking. The development goals and benefits of bamboo composite decking included: A. Decreased weight when compared to Apitong and Gen 1, thereby reducing operating costs and petroleum usage due to increased miles per gallon. B. Flexibility to allow camber design into trailers. C. Luminescence to increase safety during low light and dark conditions. D. Composite material to maximize use of bamboo bio-composites as substitute for petroleum-based composites. E. Embedded layer(s) of conditioned bamboo for added strength and stability. F. Improved safety over Apitong by temporary cargo indentation in planks for better stability. G. Cradle-to-cradle design so end-of-life becomes beginning-of-life for other products. Resource Fiber’s bamboo biocomposite trailer decking passed nail pullout tests as compared to apitong (incumbent), was lighter weight than apitong, and used less embodied energy particularly when bamboo is sourced domestically. The planks were optimized in the lab setting to the extent possible and successfully installed on the trailer at Fontaine for field testing. Despite the process not being fully optimized due to through-heat and tooling limitations within the budget constraints, the prototype decking withstood 400 cycles of reverse fatigue loading of a 107,000 lb Caterpillar 349F which was extreme conditions of field testing by Fontaine Trailer. Resource Fiber plans to outsource production of a next round of planks with a commercial pultrusion processor, then to do a re-test with Fontaine Trailers. Tooling specific to the part is required. Long-term commercial plans are to continue outsourcing production while supplying bamboo fiber and mats. Commercial markets include heavy haul trailers, military trailers, and decking for marine, industrial and residential use.

36 MATERIALS SCIENCE↗

DOE OSTI2022

CrossSim Inference Manual v2.0

Neural networks are largely based on matrix computations. During forward inference, the most heavily used compute kernel is the matrix-vector multiplication (MVM): $W \vec{x} $. Inference is a first frontier for the deployment of next-generation hardware for neural network applications, as it is more readily deployed in edge devices, such as mobile devices or embedded processors with size, weight, and power constraints. Inference is also easier to implement in analog systems than training, which has more stringent device requirements. The main processing kernel used during inference is the MVM.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

QSCOUT Progress Report, June 2022 [Quantum Scientific Computing Open User Testbed]

Quantum information processing has reached an inflection point, transitioning from proof-of-principle scientific experiments to small, noisy quantum processors. To accelerate this process and eventually move to fault-tolerant quantum computing, it is necessary to provide the scientific community with access to whitebox testbed systems. The Quantum Scientific Computing Open User Testbed (QSCOUT) provides scientists unique access to an innovative system to help advance quantum computing science.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

VERAIO Software Management Plan

VERAIO is a set of utility codes used to provide a common set of inputs and outputs to the Virtual Environment for Reactor Applications (VERA). VERA is a collection of several different computer codes that all have a common input and output. This prevents the need to manage input and output from each individual code, allowing for ease of use and reducing errors associated with code operability. The VERAIO utilities include VERAIn, VERAView, and VERARun. Each of these utilities is described below. VERAIn is an input processor that reads an ASCII input file generated by users, parses the file, performs some error checking, and writes an XML file to be read by other VERA codes. The main purpose of VERAIn is to provide a common input to all of the VERA codes, so users only need to learn one input. VERAIn is written in Perl and uses YAML configuration files to provide flexibility. VERAView is a graphical user interface (GUI) that reads a VERA hierarchical data format (HDF) output file and allows users to visualize results. VERAView is written in Python. VERARun is a script that drives the VERA execution in a high performance computing (HPC) environment. Work performed at the code level supports the quality assurance program plan (QAPP) (VERA-QA-001) and the VERA Software Quality Assurance Plan (VERA-QA-002).

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

The Importance of Scientific Visualization on Novel Hardware

Innovation in HPC hardware and adoption of heterogeneous systems has led to a variety of unique programming models. This has led to a challenge for scientific visualization software (and indeed all HPC software) to take full advantage of recent generations of supercomputing. Edge computing, where hardware is specialized for the needs of the particular application, exacerbates the problem. VTK-m has had many successes on this front by providing device-agnostic algorithms that compare favorably to implementations written to specific devices as shown in Table 1. However, VTK-m has focused mostly on GPU and traditional CPU multicore technology. There are numerous processor technologies, both existing and potential future, that are not being addressed by current R&D efforts.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

Emulating the Android Boot Process

Critical vulnerabilities continue to be discovered in the boot process of Android smartphones used around the world. The entire device's security is compromised if boot security is compromised, so any weakness presents undue risk to users. Vulnerabilities persist, in part, because independent security analysts lack access and appropriate tools. In response to this gap, we implemented a procedure for emulating the early phase of the Android boot process. This work demonstrated feasibility and utility of emulation in this space. By using HALucinator, we derived execution context and data flow, as well as incorporated peripheral hardware behavior. While smartphones with shared processors have substantial code overlap regardless of vendor, generational changes can have a significant impact. By applying our approach to older and modern devices, we learned interesting characteristics about the system. Such capabilities introduce new levels of introspection and operation understanding not previously available to mobile researchers.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

The VTK-m Users' Guide (V.1.9)

High-performance computing relies on ever finer threading. Advances in processor technology include ever greater numbers of cores, hyperthreading, accelerators with integrated blocks of cores, and special vectorized instructions, all of which require more software parallelism to achieve peak performance. Traditional visualization solutions cannot support this extreme level of concurrency. Extreme scale systems require a new programming model and a fundamental change in how we design algorithms. To address these issues we created VTK-m: the visualization toolkit for multi-/many-core architectures. VTK-m supports a number of algorithms and the ability to design further algorithms through a top-down design with an emphasis on extreme parallelism. VTK-m also provides support for finding and building links across topologies, making it possible to perform operations that determine manifold surfaces, interpolate generated values, and find adjacencies. Although VTK-m provides a simplified high-level interface for programming, its template-based code removes the overhead of abstraction. VTK-m simplifies the development of parallel scientific visualization algorithms by providing a framework of supporting functionality that allows developers to focus on visualization operations. Consider the listings in Figure 1.1 that compares the size of the implementation for the Marching Cubes algorithm in VTK-m with the equivalent reference implementation in the CUDA software development kit. Because VTK-m internally manages the parallel distribution of work and data, the VTK-m implementation is shorter and easier to maintain. Additionally, VTK-m provides data abstractions not provided by other libraries that make code written in VTK-m more versatile.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2021

Impacts of Substrate Thinning on FPGA Performance and Reliability [Slides]

Substrate thinning is necessary in devices with flip-chip BGA packages to enable both radiation testing and component qualification and high-spatial resolution beam-based failure analysis methods. We investigated three factors affecting device performance: subsurface damage from the thinning process, reduced heat spreading in thin substrates, and changes in device switching speed. We conclude subsurface damage to crystalline Si caused by the thinning process is removable with sufficient SiO 2 slurry polishing. Local temperature differences increase minimally in devices thinned to 3 μm. Compressive stress in the Si increases globally after device thinning and leads to slowing of ring oscillator frequency by about 0.5% compared to full-thickness devices. Future work will include extending the results to submicron Si thickness values, which also has important benefits for failure analysis, debug, and security assessments. We also plan to extend this type of work to other FPGAs and other devices like memory and processors.

36 MATERIALS SCIENCE↗

DOE OSTI2022

Enabling Parallel Execution of System-level Simulations in SAM

This report summarizes the recent code updates related to “element ghosting” in SAM to enable the parallel execution of system-level simulations using multiple processors/cores. Unlike typical MOOSE-based applications, for system-level simulations, SAM mostly deals with a collection of discrete small pieces of meshes, and the connection of physics on these meshes are realized by using “connector” types of components/code structures, such as conjugate heat transfer and flow junctions. The required code implementation is to correctly mark the necessary ghost elements for each type of such components/code structures; thus, the lower-level libraries can correctly perform the necessary data transfer between processors (CPUs) when executed in parallel mode. After the code updates, SAM can now run system-level simulations in the parallel mode. The parallel execution capability was then tested with an ABTR input model with 23k DOFs. Significant speedup was demonstrated when the optimal number of CPUs were used in parallel mode. Future systematic studies on parallelization performance using additional test cases covering different physics/scenarios will be needed to provide additional insights into the scalability of SAM parallelization.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

DOE OSTI2023

Implementation and Demonstration of P4 Software for Improving ICS Protocol Visibility and Control [Slides]

No prior enabling funded work applicable to this proposal. Programming Protocol-independent Packet Processors (P4) is an open source, domain-specific programming language for network switching devices. P4 complements traditional Software Defined Networking (SDN) which is primarily concerned with the management of packets (e.g. routing/dropping decisions) rather than how each packet is processed. The introduction of P4 provided new capabilities (e.g. firewall, load balancing, enhanced security) but has primarily been deployed in data centers. This effort investigates ways to expand P4 into other niches such as ICS networks.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2023

The VTK-m Users' Guide (V.2.0)

High-performance computing relies on ever finer threading. Advances in processor technology include ever greater numbers of cores, hyperthreading, accelerators with integrated blocks of cores, and special vectorized instructions, all of which require more software parallelism to achieve peak performance. Traditional visualization solutions cannot support this extreme level of concurrency. Extreme scale systems require a new programming model and a fundamental change in how we design algorithms. To address these issues we created VTK-m: the visualization toolkit for multi-/many-core architectures. VTK-m supports a number of algorithms and the ability to design further algorithms through a top-down design with an emphasis on extreme parallelism. VTK-m also provides support for finding and building links across topologies, making it possible to perform operations that determine manifold surfaces, interpolate generated values, and find adjacencies. Although VTK-m provides a simplified high-level interface for programming, its template-based code removes the overhead of abstraction. VTK-m simplifies the development of parallel scientific visualization algorithms by providing a framework of supporting functionality that allows developers to focus on visualization operations. Consider the listings in Figure 1.1 that compares the size of the implementation for the Marching Cubes algorithm in VTK-m with the equivalent reference implementation in the CUDA software development kit. Because VTK-m internally manages the parallel distribution of work and data, the VTK-m implementation is shorter and easier to maintain. Additionally, VTK-m provides data abstractions not provided by other libraries that make code written in VTK-m more versatile.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

Specifications of EBR-II Neutron Radiography Method Description and Digitization Approach

All neutron radiography (NRAD) images of fuel pins in Argonne’s collection were originally generated using the NRAD imaging facility established in the Hot Fuel Examination Facility (HFEF) at Idaho National Laboratory (INL). The NRAD reactor facility was built in 1977 and has been operating since. The reactor is a TRIGA-type reactor operating at a power level of 250 kWth to provide a neutron source for radiography imaging. The reactor is equipped with two beam tubes (i.e., east beam tube and north beam tube) to guide the neutron beams to two radiography stations. The east radiography station is directly under the HFEF main cell and is dedicated for specimens already in the HFEF hot cell. The north radiography station is outside of the main HFEF hot cell and allows NRAD imaging of non-irradiated items. The NRAD images of EBR-II irradiated metallic fuel pins were taken in the east radiography station. Thermal neutrons have the capability to transmit through most materials and are ideal for NRAD imaging. However, because of their high thermal neutron absorption cross-section, fissile materials (e.g., highly-enriched nuclear fuels) may not be as transmissible to thermal neutrons. This is also the case for oversize specimens with extraneous thickness. Epithermal neutron imaging is therefore used as a complement to thermal neutron NRAD imaging. At HFEF’s NRAD facility, both thermal and epithermal neutrons can be used for NRAD imaging. Irradiated nuclear fuels emit high levels of γ radiation that can easily darken X-ray films, so direct exposure NRAD cannot be used to image them. Instead, an indirect NRAD imaging method was developed at HFEF’s NRAD facility. In this method, foils made of materials that can be activated by neutrons (i.e., with large neutron absorption cross section) are used to collect transmitted neutron signals. Then the activated foils are then placed against X-ray films and enclosed in a vacuum cassette so that the γ decay from the activated foils can produce images on the X-ray films. Then, general X-ray film processing procedures are used to digitize and store the images. By using different foil materials, different energy neutrons can be used for NRAD imaging. At the HFEF NRAD station, two types of films are commonly used: dysprosium (Dy) foils with thickness of 130 microns are used to capture thermal neutron signal, while indium (In) foils with thickness of 130 microns are used to capture epithermal neutron signal. A cadmium or gadolinium foil is put before the indium foil to work as a thermal neutron filter. The thermal and epithermal NRAD images can be taken simultaneously by using a Dy/Cd/In sandwiched foil combination. The typical NRAD exposure time is approximately 20 minutes. Then the exposed foils are transferred to film vacuum cassettes. The vacuum ensures that there is no gap between the foil and the film. The foil-to-film exposure time is at least three half-lives of the corresponding radioisotopes, which are 3 hours for In and 7.5 hours for Dy, respectively. Exposed films are processed using an automatic film processor to produce completed NRAD images.

11 NUCLEAR FUEL CYCLE AND FUEL MATERIALS↗

DOE OSTI2023

Next-Generation Modular Flexible Low-Cost SiC-based High-Frequency-Link Transformer (Final Technical Report)

This project, led by the small business NextWatt LLC, led to the design and development of a novel high-frequency-link (HFL) transformer that yields reduce number of semiconductor devices compared to conventional solid-state transformers (SSTs). The HFL transformer is based on SiC device technology and nanocrystalline-core-based magnetics techniology. The control actuation of the SiC devices are algorithmically implemented in digital signal processor (DSP) platform. The overall HFL transformer technology is conceived and developed using a modular approach. During the course of the project the novel technology and its experimental performances at the module, multi-phase, and cascaded multi-phase levels have been demonstrated to the sponsor U.S. Department of Energy (DOE).

24 POWER TRANSMISSION AND DISTRIBUTION↗