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At least 739 records · Page 41
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

A review of crosstalk polymorphic circuits and their scalability

Using a control variable, the functionality of Polymorphic circuits can be modified, making them adaptable and useful for reconfiguring circuit behavior — all the way from gate level to system level. State-of-the art polymorphic circuits are based on custom non-linear circuit design or emerging devices such as ambipolar FET, configurable magnetic devices etc. While some of these approaches are inefficient in performance, others involve exotic devices. The Crosstalk computing based polymorphic circuits offer a fresh perspective. In Crosstalk, the interconnect interference between nanoscale metal lines is intentionally engineered to exhibit the programmable Boolean logic behavior. This approach relies on the coupling between metal lines and not on the transistors for computing, resulting in better scalability, security by obscurity, and fault tolerance by reconfiguration. Our novel approach is backed by the mathematical formulation that conveys the rationale to generalize and achieve a wide variety of polymorphic circuits. Our experiments, including design, simulation, and Power Performance Area (PPA) characterization results indicate that crosstalk circuits provide significant improvement in transistor count (about 3x), switching energy (2x), and speed (1.5x) for polymorphic logic circuits. In the best-case scenario, the transistor count reduction is 5x. This paper presents Crosstalk computing’s fundamentals, polymorphism and the scalability aspects to compete/co-exist with CMOS for digital logic implementations below 10 nm. Our scalability study uses Open Source 7 nm PDK, considers all process variation aspects and accommodates worst-case scenarios. The study results for various benchmark circuits show that the Crosstalk technology is a viable alternative to CMOS for digital logic implementations below 10 nm, having 48% density, 57% power, and 10% performance gains over equivalent CMOS counterparts. Finally, we compare Crosstalk Polymorphic Circuit design technique with similar approaches described in related works and discuss its features and constraints.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Signal propagation in reversible digital mechanics

Digital mechanics explores information processing through binary, mechanical circuits. This work demonstrates a flexural, mechanical integrated circuit (m-IC) that achieves reversible, non-reciprocal signal propagation through integrated AND logic and memory. Our approach exploits sequential bistable transitions with symmetric energy wells, tunable stiffness, impedance matching, and AND gate non-linearity, to enable signal propagation, repeatability, and reversibility. We present a generalized model of logic kinematics and energetics, validated experimentally, to study energy flows, quantify energetic limits, and identify operating regimes for reversible logic. Macro-scale experiments confirm propagation dynamics, and new fabrication methods extend the architecture to micro-scale devices. By achieving controlled, reversible signal transmission across interconnected logic and memory, this work establishes a scalable platform for robust mechanical computing and adaptive sensing.

Johnson, Hilary A. [Lawrence Livermore National La↗
DOE OSTI2023

Model-based data center cooling controls comparative co-design

This article presents a comparative simulation-based control logic design process. It uses the Control Description Language (CDL) and the ASHRAE Guideline 36 high-performing building control sequences with the Modelica Buildings Library (MBL) to demonstrate a comparative analysis of two control designs for a data center chilled water plant. Details include a description of the closed-loop plant and control design methodology, including sizing and parameterization, base and alternative (Guideline 36) control logic with software implementation structure, and outline of the simulation experimentation process. The selected control designs are paired with comparable chilled water plant configurations. The models include a chiller, a water-side economizer, and an evaporative cooling tower. The plant provides cooling at 27ºC zone supply air temperature to a data center in Sacramento, CA. The comparative simulation results examined the impacts of a selected control logic detail, and present an example model-based design application. Overall, the simulation results showed a 25% annual and a 18% summer energy use reduction for alternative controls. This shows that simulation-based control logic design performance evaluation can improve energy efficiency and resilience aspects of system controls at large.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2024

Dynamically generated decoherence-free subspaces and subsystems on superconducting qubits

Abstract Decoherence-free subspaces and subsystems (DFS) preserve quantum information by encoding it into symmetry-protected states unaffected by decoherence. An inherent DFS of a given experimental system may not exist; however, through the use of dynamical decoupling (DD), one can induce symmetries that support DFSs. Here, we provide the first experimental demonstration of DD-generated decoherence-free subsystem logical qubits. Utilizing IBM Quantum superconducting processors, we investigate two and three-qubit DFS codes comprising up to six and seven noninteracting logical qubits, respectively. Through a combination of DD and error detection, we show that DFS logical qubits can achieve up to a 23% improvement in state preservation fidelity over physical qubits subject to DD alone. This constitutes a beyond-breakeven fidelity improvement for DFS-encoded qubits. Our results showcase the potential utility of DFS codes as a pathway toward enhanced computational accuracy via logical encoding on quantum processors.

Physics↗
DOE OSTI2020

Revisiting separation: Algorithms and complexity

Abstract Linear temporal logic (LTL) with Since and Until modalities is expressively equivalent, over the class of complete linear orders, to a fragment of first-order logic known as FOMLO (first-order monadic logic of order). It turns out that LTL, under some basic assumptions, is expressively complete if and only if it has the property, called separation, that every formula is equivalent to a Boolean combination of formulas that each refer only to the past, present or future. Herein we present simple algorithms and their implementations to perform separation of the LTL with Since and Until, over discrete and complete linear orders, and translation from FOMLO formulas into equivalent temporal logic formulas. We additionally show that the separation of a certain fragment of LTL results in at most a double exponential size growth.

Oliveira, Daniel↗
DOE OSTI2026

Clifford Hierarchy Stabilizer Codes: Transversal Non-Clifford Gates and Magic States

A fundamental problem in fault-tolerant quantum computation is the tradeoff between universality and dimensionality, exemplified by the the Bravyi-König bound for $n$-dimensional topological stabilizer codes. In this work, we extend topological Pauli stabilizer codes to a broad class of $n$-dimensional Clifford hierarchy stabilizer codes. These codes correspond to the $(n+1)$D Dijkgraaf-Witten gauge theories with non-Abelian topological order. We construct transversal non-Clifford gates through automorphism symmetries represented by cup products. In 2D, we obtain the first transversal non-Clifford logical gates including T and CS for Clifford stabilizer codes, using the automorphism of the twisted $\mathbb{Z}_2^3$ gauge theory (equivalent to $\mathbb{D}_4$ topological order). We also combine it with the just-in-time decoder to fault-tolerantly prepare the logical T magic state in $O(d)$ rounds via code switching. In 3D, we construct a transversal logical $\sqrt{\text{T}}$ gate in a non-Clifford stabilizer code at the third level of the Clifford hierarchy, located on a tetrahedron corresponding to a twisted $\mathbb{Z}_2^4$ gauge theory. Furthermore, our constructions surpass the Bravyi-König bound by achieving the logical gates in the $(n+1)$-th level of Clifford hierarchy in $n$ spatial dimension.

Kobayashi, Ryohei [Institute for Advanced Study, P↗
DOE OSTI2023

Better Than Worst-Case Decoding for Quantum Error Correction

The overheads of classical decoding for quantum error correction in cryogenic quantum systems grow rapidly with the number of logical qubits and their correction code distance. Decoding at room temperature is bottlenecked by refrigerator I/O bandwidth while cryogenic on-chip decoding is limited by area/power/thermal budget. To overcome these overheads, we are motivated by the observation that in the common case (over 90% of the time), error correction 'syndromes' are fairly trivial with high redundancy / sparsity, since the error correction codes are over-provisioned to be able to correct for uncommon worst-case complex scenarios (to ensure substantially low logical error rates). If suitably exploited, these trivial scenarios can be handled with insignificant overhead, thereby alleviating any bottlenecks towards handling the worst-case scenarios by state-of-the-art means. Here, we propose Better Than Worst-Case Decoding for Quantum Error Correction, targeting cryogenic quantum systems and Surface Code, consisting of: On-chip Clique Decoder: An extremely lightweight decoder for correcting trivial common-case errors, designed for the cryogenic domain. The decoder is implemented and evaluated for SFQ logic. Statistical Off-chip Bandwidth Allocation: A statistical confidence-based technique for allocation of off-chip decoding bandwidth, to efficiently handle the rare complex decodes that are not covered by the Clique Decoder. Decode-Overflow Execution Stalling: A method to stall circuit execution, for the worst-case scenarios in which the provisioned off-chip bandwidth is insufficient to complete all requested off-chip decodes. In all, BTWC decoding achieves 70-99+% off-chip bandwidth elimination across a range of logical and physical error rates, without significantly sacrificing the accuracy of a state-of-the-art off-chip decoder. Further, it achieves 10-1000x bandwidth reduction over prior bandwidth reduction techniques, as well as 15-37x resource overhead reduction compared to prior on-chip decoding.

cryogenic optimization↗
DOE OSTI2024

Realistic Cost to Execute Practical Quantum Circuits using Direct Clifford+T Lattice Surgery Compilation

We report a resource estimation pipeline that explicitly compiles quantum circuits expressed using the Clifford+T gate set into a surface code lattice surgery instruction set. The cadence of magic state requests from the compiled circuit enables the optimization of magic state distillation and storage requirements in a post-hoc analysis. To compile logical circuits into lattice surgery operations, we build upon the open-source Lattice Surgery Compiler. The revised compiler operates in two stages: the first translates logical gates into an abstract, layout-independent instruction set; the second compiles these into local lattice surgery instructions that are allocated to hardware tiles according to a specified resource layout. The second stage retains logical parallelism while avoiding resource contention in the fault-tolerant layer, aiding realism. Additionally, users can specify dedicated tiles at which magic states are replenished, enabling resource costs from the logical computation to be considered independently from magic state distillation and storage. We demonstrate the applicability of our pipeline to large practical quantum circuits by providing resource estimates for the ground state estimation of molecules. Finally, we find that variable magic state consumption rates in real circuits can cause the resource costs of magic state storage to dominate unless production is varied to suit.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Sentinel

Network intrusion detection systems (NIDS) are commonplace in network security but they frequently employ algorithms that are computational demanding requiring hardware and software with significant power requirements. Two examples of such resource-intensive algorithms used for network security are regular expression matching and broader signature pattern matching which are commonly used in deep packet inspection (DPI). Network security algorithms that have large power requirements may be a challenge for low-power internet-of-things (IoT) environments, which generally lack the power resources to implement complex security measures like computationally expensive DPI at the edge. Furthermore, IoT environments incorporating 5G standalone networks have network latency constraints beyond just power that make DPI at the edge even more difficult. Programmable logic is ideally suited for machine learning inference for DPI because of its deep instruction level parallelism and single-cycle memory access. Machine learning approaches for DPI have been explored before using the programmable logic of field programmable gate arrays (FPGA) as a potential solution for NIDS approaches that would be power-suitable for IoT. However, those previous programmable logic NIDS approaches utilize either a supervised or unsupervised learning model. Sentinel utilizes the ensemble of these two machine learning approaches known as a semi-supervised approach which has shown promise in NIDS implementations. Sentinel provides a programmable logic implementation of a semi-supervised approach for DPI which operates at much lower power and latency than a GPU implementation with negligible loss of accuracy due to quantization through a logistic regressor.

Anderson, MatthewW [Idaho National Laboratory (INL↗
DOE OSTI2025

Hierarchical memories: Simulating quantum LDPC codes with local gates

Constant-rate low-density parity-check (LDPC) codes are promising candidates for constructing efficient fault-tolerant quantum memories. However, if physical gates are subject to geometric-locality constraints, it becomes challenging to realize these codes. In this paper, we construct a new family of [[N,K,D]] codes, referred to as hierarchical codes, that encode a number of logical qubits K=Ω(N/log(N) 2 ). The N th element of this code family is obtained by concatenating a constant-rate quantum LDPC code with a surface code; nearest-neighbor gates in two dimensions are sufficient to implement the corresponding syndrome-extraction circuit and achieve a threshold. Below threshold the logical failure rate vanishes superpolynomially as a function of the distance D(N). We present a bilayer architecture for implementing the syndrome-extraction circuit, and estimate the logical failure rate for this architecture. Under conservative assumptions, we find that the hierarchical code outperforms the basic encoding where all logical qubits are encoded in the surface code.

Pattison, Christopher A. [California Institute of ↗
DOE OSTI2023

Universal Passive Synchronization Method for Grid-Forming Inverters Without Mode Transition

Power systems are transforming with increasing levels of inverter-based resources (IBRs). This transformation requires critical roles of grid-forming (GFM) inverters replacing synchronous generators for bulk power system stabilization and ancillary services, also allowing flexible power system operation, such as microgrid that is operated by multiple GFM IBRs to achieve system resilience against contingencies. To realize the resilient power systems allowing flexible in-and-out operation of GFM IBRs potentially programmed with different primary controls, a synchronization method universally applicable, i.e., independent of control types, would be beneficial to ease the integration process, but it has not been actively studied. To fill the gap, this paper proposes a universal synchronization method that achieves a passive synchronization to enable a smooth transition in a grid with off-nominal system parameters, i.e., voltage and frequency. The logic proposed requires no modification on the primary control, thus applicable to any type of GFMs with a voltage reference input. To validate the concept, a simulation of an IEEE 13-bus benchmark system modified with 3 GFM inverters is presented. It simulates an inverter-driven black start scenario in which GFM inverters autonomously turn on and connect to the grid under heavy loading, using the synchronization logic. The case study demonstrates that GFM inverters can tune their voltage reference to smoothly synchronize without severe transients, and contribute to a seamless black start of the grid under unbalanced load conditions. Two GFM methods - Droop and dispatchable virtual oscillator control - are used for the demo to validate feasibility and interoperability of the passive synchronization.

black start↗
NASA NTRS1974

A self-reorganizing digital flight control system for aircraft

This paper presents a design method for digital self-reorganizing control systems which is optimally tolerant of failures in aircraft sensors. The functions of this system are accomplished with software instead of the popular and costly technique of hardware duplication. The theoretical development, based on M-ary hypothesis testing, results in a bank of M Kalman filters operating in parallel in the failure detection logic. A moving window of the innovations of each Kalman filter drives the detection logic to decide the failure state of the system. The detection logic also selects the optimal state estimate (for control logic) from the bank of Kalman filters. The design process is applied to the design of a self-reorganizing control system for a current configuration of the space shuttle orbiter at Mach 5 and 120,000 feet. The failure detection capabilities of the system are demonstrated using a real-time simulation of the system with noisy sensors.

Montgomery, R. C.↗
NASA NTRS1975

Launch vehicle attitude control

The minor loop and minor loop support modules which maintain correct vehicle attitude control by generating vehicle attitude error signals were verified. The logic is checked during boost and orbit (unusual timing situations necessitate the additional orbit checks) and the constants used by these modules checked at every point during the flight. Since the same logic instructions are used throughout the flight with only the constants changing, verification of the logic at two points and the constants at all points verify the logic throughout the flight.

Source record↗
NASA NTRS1976

TPGITF user's manual

The primary purpose of TPG interface (TPGITF) software is to create test patterns, according to a mathematical model, for a real device. In order for the device actually to be tested or to be accurately simulated, a means is required to transform the TPGITF generated test into forms acceptable as input to logic test equipment or to a software logic simulator. The MACRODATA-200 Logic Test System and the LOGSIM logic simulator are the particular systems supported by the TPGITF software. A description is presented of the TPGITF software processor. It is assumed that the reader is familiar with the TPG, LOGSIM, and TOIL systems. Flow charts are given.

Pitts, E. R.↗
NASA NTRS1975

Testability enhancement in digital system design

A new way of employing hardware redundancy to reduce the number of tests for fault detection in both combinational and synchronous sequential circuits is investigated. An approach is presented for utilizing systematic redundancy to simplify design work. Models for PLM (programmable logic module) and CMM (controllable memory module) are depicted. Systematic design and detection procedures are described. Using these procedures, an easily testable circuit (for stuck faults) can be designed. In contrast to the earlier results on fault detection in logic circuit, two tests are needed to detect any stuck faults of combinational logic circuit. Four tests are necessary and sufficient to detect any stuck faults of elementary logic gates and the malfunction of flip-flops of synchronous sequential circuit using Delay flip-flops or trigger flip-flops.

Chuang, C. S.↗
NASA NTRS1976

TSE computers - A means for massively parallel computations

A description is presented of hardware concepts for building a massively parallel processing system for two-dimensional data. The processing system is to use logic arrays of 128 x 128 elements which perform over 16 thousand operations simultaneously. Attention is given to image data, logic arrays, basic image logic functions, a prototype negator, an interleaver device, image logic circuits, and an image memory circuit.

Strong, J. P., III↗
NASA NTRS1981

CADAT network translator

Program converts cell-net data into logic-gate models for use in test and simulation programs. Input consists of either Place, Route, and Fold (PRF) or Place-and-Route-in-Two-Dimensions (PR2D) layout data deck. Output consists of either Test Pattern Generator (TPG) or Logic-Simulation (LOGSIM) logic circuitry data deck. Designer needs to build only logic-gate-model circuit description since program acts as translator. Language is FORTRAN IV.

Pitts, E. R.↗
NASA NTRS1985

Encoding Scheme Reduces Hardware Requirements

Shift register time-shared in proposed error-correcting code for tape-storage systems. Error-correcting code logic for blocks of 256-bit data words implemented by 14-stage-time-shared shift register, two 4,096bit RAM's and logic gates. Encoding and decoding logic implement generator polynomial that defines error-correcting code, and error correction based on algorithm also implemented by logic.

Sasnowitz, H.↗