Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “execution architecture”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 739 records · Page 41

Human Transportation System (HTS) study: Executive summary

This report summarizes work completed under the Human Transportation System Study. This study was conducted by the New Initiatives Office at JSC with the technical support of Boeing, General Dynamics, Lockheed, McDonnell-Douglas, Martin Marietta, and Rockwell. The study was designed to generate information on determining the appropriate path to follow for new system development to meet the Nation's space transportation needs. The study evaluates 18 transportation architecture options using a parametric set of mission requirements. These options include use of current systems (e.g., Shuttle, Titan, etc.) as well as proposed systems (e.g., PLS, Single-Stage-to-Orbit, etc.) to assess the impact of various considerations, such as the cost of alternate access, or the benefit of separating people and cargo. The architecture options are compared to each other with six measurable evaluation criteria or attributes. They are: funding profile, human safety, probability of mission success, architecture cost risk, launch schedule confidence, and environmental impact. Values for these attributes are presented for the architecture options, with pertinent conclusions and recommendations.

Unmanned spacecraft↗

Analyzing the Performance Trade-Off in Implementing User-Level Threads

User-level threads have been widely adopted as a means of achieving lightweight concurrent execution without the costs of OS-level threads. Nevertheless, the costs of managing user-level threads represent a performance barrier that dictates how fine grained the concurrency exposed by an application can be without incurring significant overheads; this in turn may translate into insufficient parallelism to exploit highly parallel systems. This article is a deep dive into the fundamental costs in implementing user-level threads. We first identify that one of the highest sources of fork-join overheads stems from deviations, events that incur context switching during the execution of a thread and disrupt a run-to-completion execution. We then conduct an in-depth investigation of a wide spectrum of methods with respect to how they handle deviations while covering both parent- and child-first scheduling policies. Our methodology involves a comprehensive instruction- and cache-level analysis of all methods on several modern CPU architectures. Finally, the primary finding of our evaluation is that dynamic promotion methods that assume the absence of deviation and dynamically provide context-switching support offer the best trade-off between performance and capability when the likelihood of deviation is low.

97 MATHEMATICS AND COMPUTING↗

QCOR; A Language Extension Specification for the Heterogeneous Quantum-Classical Model of Computation

Quantum computing (QC) is an emerging computational paradigm that leverages the laws of quantum mechanics to perform elementary logic operations. Existing programming models for QC were designed with fault-tolerant hardware in mind, envisioning stand-alone applications. However, the susceptibility of near-term quantum computers to noise limits their stand-alone utility. To better leverage limited computational strengths of noisy quantum devices, hybrid algorithms have been suggested whereby quantum computers are used in tandem with their classical counterparts in a heterogeneous fashion. This modus operandi calls out for a programming model and a high-level programming language that natively and seamlessly supports heterogeneous quantum-classical hardware architectures in a single-source-code paradigm. Motivated by the lack of such a model, we introduce a language extension specification, called QCOR, which enables single-source quantum-classical programming. Programs written using the QCOR library–based language extensions can be compiled to produce functional hybrid binary executables. After defining QCOR’s programming model, memory model, and execution model, we discuss how QCOR enables variational, iterative, and feed-forward QC. Additionally, QCOR approaches quantum-classical computation in a hardware-agnostic heterogeneous fashion and strives to build on best practices of high-performance computing. The high level of abstraction in the language extension is intended to accelerate the adoption of QC by researchers familiar with classical high-performance computing.

97 MATHEMATICS AND COMPUTING↗

Parallel solution of finite element equations

The paper examines several parallel processing solution algorithms for finite element equations arising in linear equilibrium problems. Two basic groups of algorithms, direct and iterative, are investigated with respect to a number of parallel computer architectures and associated selection criteria. The direct algorithms include: LR-Gauss, Crout, Cholesky, Cyclic Reduction and WZ-factorization. The iterative methods examined are: Accelerated Gauss-Seidel, Surrogate Stiffness, Jacobi, Series Expansion, and Energy Monte Carlo. For real-time applications, where the object is to minimize the execution time, Cyclic Reduction appears to be best suited. This assumes a computer with an unlimited number of parallel processors. However, for computers with a limited number of parallel processors that must be used efficiently, both Gauss factorization and Jacobi-like iterative methods rank favorably.

Salama, M.↗

In-Space Assembly Capability Assessment for Potential Human Exploration and Science Applications

Human missions to Mars present several major challenges that must be overcome, including delivering multiple large mass and volume elements, keeping the crew safe and productive, meeting cost constraints, and ensuring a sustainable campaign. Traditional methods for executing human Mars missions minimize or eliminate in-space assembly, which provides a narrow range of options for addressing these challenges and limits the types of missions that can be performed. This paper discusses recent work to evaluate how the inclusion of in-space assembly in space mission architectural concepts could provide novel solutions to address these challenges by increasing operational flexibility, robustness, risk reduction, crew health and safety, and sustainability. A hierarchical framework is presented to characterize assembly strategies, assembly tasks, and the required capabilities to assemble mission systems in space. The framework is used to identify general mission system design considerations and assembly system characteristics by assembly strategy. These general approaches are then applied to identify potential in-space assembly applications to address each challenge. Through this process, several focus areas were identified where applications of in-space assembly could affect multiple challenges. Each focus area was developed to identify functions, potential assembly solutions and operations, key architectural trades, and potential considerations and implications of implementation. This paper helps to identify key areas to investigate were potentially significant gains in addressing the challenges with human missions to Mars may be realized, and creates a foundation on which to further develop and analyze in-space assembly concepts and assembly-based architectures.

Jefferies, Sharon A.↗

GPU acceleration of hybrid functional calculations in the SPARC electronic structure code

We present a Graphics Processing Unit (GPU)-accelerated version of the real-space SPARC electronic structure code for performing hybrid functional calculations in generalized Kohn–Sham density functional theory. In particular, we develop a batch variant of the recently formulated Kronecker product-based linear solver for the simultaneous solution of multiple linear systems. We then develop a modular, math kernel based implementation for hybrid functionals on NVIDIA architectures, where computationally intensive operations are offloaded to the GPUs, while the remaining workload is handled by the central processing units (CPUs). Considering bulk and slab examples, we demonstrate that GPUs enable up to 8× speedup in node-hours and 80× in core-hours compared to CPU-only execution, reducing the time to solution on V100 GPUs to around 300 s for a metallic system with over 6000 electrons, and significantly reducing the computational resources required for a given wall time.

Kohn-Sham density functional theory↗

The fault-tolerant multiprocessor computer

The development and evaluation of fault-tolerant computer architectures and software-implemented fault tolerance (SIFT) for use in advanced NASA vehicles and potentially in flight-control systems are described in a collection of previously published reports prepared for NASA. Topics addressed include the principles of fault-tolerant multiprocessor (FTMP) operation; processor and slave regional designs; FTMP executive, facilities, acceptance-test/diagnostic, applications, and support software; FTM reliability and availability models; SIFT hardware design; and SIFT validation and verification.

Smith, T. B., III↗

Supervised Remote Robot with Guided Autonomy and Teleoperation (SURROGATE): A Framework for Whole-Body Manipulation

The use of the cognitive capabilties of humans to help guide the autonomy of robotics platforms in what is typically called "supervised-autonomy" is becoming more commonplace in robotics research. The work discussed in this paper presents an approach to a human-in-the-loop mode of robot operation that integrates high level human cognition and commanding with the intelligence and processing power of autonomous systems. Our framework for a "Supervised Remote Robot with Guided Autonomy and Teleoperation" (SURROGATE) is demonstrated on a robotic platform consisting of a pan-tilt perception head, two 7-DOF arms connected by a single 7-DOF torso, mounted on a tracked-wheel base. We present an architecture that allows high-level supervisory commands and intents to be specified by a user that are then interpreted by the robotic system to perform whole body manipulation tasks autonomously. We use a concept of "behaviors" to chain together sequences of "actions" for the robot to perform which is then executed real time.

Hebert, Paul↗

Progressive Development of Fleet Management Capabilities for a High Density Vertiplex Environment

The High Density Vertiplex (HDV) Sub-Project, as part of NASA’s Advanced Air Mobility (AAM) Project, has been developing a reference automation architecture with a far-term view of scalable, high-density operations in and around vertiport terminal areas. One of the components of that architecture under development has been focused on fleet management capabilities to support the management of multiple AAM operations from a supervisory role of a fleet manager. This capability relies on connectivity and information exchanges with other services for airspace and vertiport management as well as with flight crews responsible for operation execution. This paper will present this capability with a focus on its user interface developments as well as its integration into the simulation and flight testing performed as part of the HDV research roadmap.

AAM↗

Progressive Development of Fleet Management Capabilities for a High Density Vertiplex Environment

The High Density Vertiplex (HDV) Sub-Project, as part of NASA’s Advanced Air Mobility (AAM) Project, has been developing a reference automation architecture with a far-term view of scalable, high-density operations in and around vertiport terminal areas. One of the components of that architecture under development has been focused on fleet management capabilities to support the management of multiple AAM operations from a supervisory role of a fleet manager. This capability relies on connectivity and information exchanges with other services for airspace and vertiport management as well as with flight crews responsible for operation execution. This paper will present this capability with a focus on its user interface developments as well as its integration into the simulation and flight testing performed as part of the HDV research roadmap.

high density vertiport↗

Architecture for Quantum Time-dependent Circuits (ArQTIC) v1.0

ArQTiC is a domain-specific full-stack software package built for the dynamic simulations of materials on quantum computers. Its main contributions include providing a software library for high-level programming of such simulations on quantum computers, and providing post-processing capabilities that allow users to more efficiently analyze results from the quantum computer. Paired with the power to optimize and execute quantum circuits, ArQTiC opens the field of dynamic materials simulations on quantum computers to a broader community of scientists from a wider range of domain sciences, paving the way for accelerated progress towards physical quantum supremacy.

Bassman, Lindsay↗

Obstacle Detection Algorithms for Aircraft Navigation: Performance Characterization of Obstacle Detection Algorithms for Aircraft Navigation

The research reported here is a part of NASA's Synthetic Vision System (SVS) project for the development of a High Speed Civil Transport Aircraft (HSCT). One of the components of the SVS is a module for detection of potential obstacles in the aircraft's flight path by analyzing the images captured by an on-board camera in real-time. Design of such a module includes the selection and characterization of robust, reliable, and fast techniques and their implementation for execution in real-time. This report describes the results of our research in realizing such a design. It is organized into three parts. Part I. Data modeling and camera characterization; Part II. Algorithms for detecting airborne obstacles; and Part III. Real time implementation of obstacle detection algorithms on the Datacube MaxPCI architecture. A list of publications resulting from this grant as well as a list of relevant publications resulting from prior NASA grants on this topic are presented.

Kasturi, Rangachar↗

The " Swarm of Ants vs. Herd of Elephants" Debated Revisited: Performance Measurements of PVM-Overflow Across a Wide Spectrum of Architectures

The Gorden Bell Prizes given out at Supercomputing every year includes at least two catergories: performance (highest GFLOP count) and price-performance (GFLOP/million $$) for real applications. In the past five years, the winners of the price-performance categories all came from networks of work-stations. This reflects three important facts: 1. supercomputers are still too expensive for the masses; 2. achieving high performance for real applications takes real work; and, most importantly; 3. it is possible to obtain acceptable performance for certain real applications on network of work stations. With the continued advance of network technology as well as increased performance of "desktop" workstation, the "Swarm of Ants vs. Herd of Elephants" debate, which began with vector multiprocessors (VPPs) against SIMD type multiprocessors (e.g. CM2), is now recast as VPPs against Symetric Multiprocessors (SMPs, e.g. SGI PowerChallenge). This paper reports on performance studies we performed solving a large scale (2-million grid pt.s) CFD problem involving a Boeing 747 based on a parallel version of OVERFLOW that utilizes message passing on PVM. A performance monitoring tool developed under NASA HPCC, called AIMS, was used to instrument and analyze the the performance data thus obtained. We plan to compare its performance data obtained across a wide spectrum of architectures including: the Cray C90, IBM/SP2, SGI/Power Challenge Cluster, to a group of workstations connected over a simple network. The metrics of comparison includes speed-up, price-performance, throughput, and turn-around time. We also plan to present a plan of attack for various issues that will make the execution of Grand Challenge Applications across the Global Information Infrastructure a reality.

Yan, Jerry C.↗

Development and flight evaluation of an augmented stability active controls concept: Executive summary

A pitch active control system (PACS) was developed and flight tested on a wide body jet transport (L-1011) with a flying horizontal stabilizer. Two dual channel digital computers and the associated software provide command signals to a dual channel series servo which controls the stabilizer power actuators. Input sensor signals to the computer are pitch rate, column trim position, and dynamic pressure. Control laws are given for the PACS and the system architecture is defined. Discussions are given regarding piloted flight simulation and vehicle system simulation and vehicle system simulation tests that are performed to verify control laws and system operation prior to installation on the aircraft. Modifications to the basic aircraft included installation of the PACS, addition of a c.g. management system to provide a c.g. range from 25 to 39% mac, and downrigging of the geared elevator to provide the required nose down control authority for aft c.g. flight test conditions. Three pilots used the Cooper-Harper Rating Scale to judge flying qualities of the aircraft with PACS on and off. The handling qualities with the c.g. at 39% mac (41% stability margin) and PACS operating were judged to be as good as the handling qualities with the c.g. at 25% mac (+15% stability margin) and PACS off.

Guinn, W. A.↗

Accelerated Constrained Sparse Tensor Factorization on Massively Parallel Architectures

This study presents the first constrained sparse tensor factorization (cSTF) framework that optimizes and fully offloads computation to massively parallel GPU architectures, and the first performance characterization of cSTF on GPU architectures. In contrast to prior work on tensor factorization, where the matricized tensor times Khatri-Rao product (MTTKRP) is the primary performance bottleneck, our systematic analysis of the cSTF algorithm on GPUs reveals that adding constraints creates an additional bottleneck in the update operation for many real-world sparse tensors. While executing the update operation on the GPU brings significant speedup over its CPU counterpart, it remains a significant bottleneck. To further accelerate the update operation, we propose cuADMM, a new update algorithm that leverages algorithmic and code optimization strategies to minimize both computation and data movement on GPUs. As a result, our framework delivers significantly improved performance compared to prior state-of-the-art. On 10 real-world sparse tensors, our framework achieves geometric mean speedup of 5.1 × (max 41.59 ×) and 7.01 × (max 58.05 ×) on the NIVIDA A100 and H100 GPUs, respectively, over the state-of-the-art SPLATT library running on a 26-core Intel Ice Lake Xeon CPU.

Soh, Yongseok↗

Compressed basis GMRES on high-performance graphics processing units

Krylov methods provide a fast and highly parallel numerical tool for the iterative solution of many large-scale sparse linear systems. To a large extent, the performance of practical realizations of these methods is constrained by the communication bandwidth in current computer architectures, motivating the investigation of sophisticated techniques to avoid, reduce, and/or hide the message-passing costs (in distributed platforms) and the memory accesses (in all architectures). This article leverages Ginkgo’s memory accessor in order to integrate a communication-reduction strategy into the (Krylov) GMRES solver that decouples the storage format (i.e., the data representation in memory) of the orthogonal basis from the arithmetic precision that is employed during the operations with that basis. Given that the execution time of the GMRES solver is largely determined by the memory accesses, the cost of the datatype transforms can be mostly hidden, resulting in the acceleration of the iterative step via a decrease in the volume of bits being retrieved from memory. Together with the special properties of the orthonormal basis (whose elements are all bounded by 1), this paves the road toward the aggressive customization of the storage format, which includes some floating-point as well as fixed-point formats with mild impact on the convergence of the iterative process. We develop a high-performance implementation of the “compressed basis GMRES” solver in the Ginkgo sparse linear algebra library using a large set of test problems from the SuiteSparse Matrix Collection. We demonstrate robustness and performance advantages on a modern NVIDIA V100 graphics processing unit (GPU) of up to 50% over the standard GMRES solver that stores all data in IEEE double-precision.

97 MATHEMATICS AND COMPUTING↗

Space Station Freedom operations planning

The Space Station Freedom program is developing an operations planning structure which assigns responsibility for planning activities to three tiers of management. The strategic level develops the policy, goals and requirements for the program over a five-year horizon. Planning at the tactical level emphasizes program integration and planning for a two-year horizon. The tactical planning process, architecture, and products have been documented and discussed with the international partners. Tactical planning includes the assignment of user and system hardware as well as significant operational events to a time increment (the period of time from the arrival of one Shuttle to the manned base to the arrival of the next). Execution-level planning emphasizes implementation, and each organization produces detailed plans, by increment, that are specific to its function.

Accola, Anne L.↗

Fault injection experiments using FIAT

The results of several experiments conducted using the fault-injection-based automated testing (FIAT) system are presented. FIAT is capable of emulating a variety of distributed system architectures, and it provides the capabilities to monitor system behavior and inject faults for the purpose of experimental characterization and validation of a system's dependability. The experiments consist of exhaustively injecting three separate fault types into various locations, encompassing both the code and data portions of memory images, of two distinct applications executed with several different data values and sizes. Fault types are variations of memory bit faults. The results show that there are a limited number of system-level fault manifestations. These manifestations follow a normal distribution for each fault type. Error detection latencies are found to be normally distributed. The methodology can be used to predict the system-level fault responses during the system design stage.

Barton, James H.↗