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At least 739 records · Page 41

A New Route Toward Atomically Flat and Defect-Free Ge/SiGe Planar Heterostructures

Germanium-based planar heterostructures are emerging as versatile platforms for realizing quantum devices. In particular, planar Ge/SiGe quantum wells (QWs) host hole states with exceptionally high mobility and strong, electrically tunable spin–orbit interactions, enabling full electrical control of quantum information. A key requirement for these systems is the growth of microscopic, defect-free, atomically flat Ge QW heterostructures on relaxed or reverse-graded SiGe buffer layers, as well as on commercial Ge substrates. While several physical deposition techniques have demonstrated high-quality planar Ge/SiGe QWs, a major challenge remains: minimizing defect density typically requires high growth temperatures, which are incompatible with standard CMOS process flows. Here, we present a convenient low-temperature process for realizing high-quality planar SiGe/Ge heterostructures using a combination of thermal and electron-beam evaporation. We systematically map the effects of ex-situ and in-situ substrate preparation protocols, growth temperature, and post-deposition annealing conditions, and correlate these parameters with surface roughness and defect density. We find that in-situ oxide desorption conditions and post-annealing parameters have the most pronounced impact on improving surface quality. Under optimized conditions, we achieve atomically smooth surfaces with root-mean-square roughness σrms​ ≤ 10 Å and negligible defect density. Interestingly, thermally evaporated Ge layers exhibit oriented triangular crystallites that elongate upon post-annealing in the presence of high Ge vapor pressure. These results demonstrate that this simple, low-temperature deposition approach is a viable and effective route for achieving high-quality Ge QW heterostructures, with strong potential for scalable quantum computing and sensing applications.

Tripathi, Malvika [Fermilab] (ORCID:00000001989251↗

A New Route Toward Atomically Flat and Defect-Free Ge/SiGe Planar Heterostructures

Germanium-based planar heterostructures are emerging as versatile platforms for realizing quantum devices. In particular, planar Ge/SiGe quantum wells (QWs) host hole states with exceptionally high mobility and strong, electrically tunable spin–orbit interactions, enabling full electrical control of quantum information. A key requirement for these systems is the growth of microscopic, defect-free, atomically flat Ge QW heterostructures on relaxed or reverse-graded SiGe buffer layers, as well as on commercial Ge substrates. While several physical deposition techniques have demonstrated high-quality planar Ge/SiGe QWs, a major challenge remains: minimizing defect density typically requires high growth temperatures, which are incompatible with standard CMOS process flows. Here, we present a convenient low-temperature process for realizing high-quality planar SiGe/Ge heterostructures using a combination of thermal and electron-beam evaporation. We systematically map the effects of ex-situ and in-situ substrate preparation protocols, growth temperature, and post-deposition annealing conditions, and correlate these parameters with surface roughness and defect density. We find that in-situ oxide desorption conditions and post-annealing parameters have the most pronounced impact on improving surface quality. Under optimized conditions, we achieve atomically smooth surfaces with root-mean-square roughness σrms​ ≤ 10 Å and negligible defect density. Interestingly, thermally evaporated Ge layers exhibit oriented triangular crystallites that elongate upon post-annealing in the presence of high Ge vapor pressure. These results demonstrate that this simple, low-temperature deposition approach is a viable and effective route for achieving high-quality Ge QW heterostructures, with strong potential for scalable quantum computing and sensing applications.

Tripathi, Malvika [Fermilab] (ORCID:00000001989251↗

Using High-Performance Cameras for Advanced Plasma Diagnostics

We will present insights, challenges, and recent progress on using a multi-megapixel deep-depletion CCD camera for quantitative X-ray spectra in a single-hit exposure mode in order to optimize X-ray diffraction experiments. We will also present some applications of Sandia’s in-house developed hybrid CMOS (hCMOS) sensors, which can record up to four full frames of optical or X-ray images in sequences with only a few nanoseconds interframe timing in a single line-of-sight.

Geissel, Matthias [Sandia National Laboratories (S↗

RD53 analog front-end processors for the ATLAS and CMS experiments at the High-Luminosity LHC

This work discusses the design and the main results relevant to the characterization of analog front-end processors in view of their operation in the pixel detector readout chips of ATLAS and CMS at the High-Luminosity LHC. The front-end channels presented in this paper are part of RD53A, a large scale demonstrator designed in a 65 nm CMOS technology by the RD53 collaboration.The collaboration is now developing the full-sized readout chips for the actual experiments. Some details on the improvements implemented in the analog front-ends are provided in the paper.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Unconventional compute methods and future challenges for superconducting digital computing

Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.

EDA tools↗

Engineering Tunneling Selector to Achieve High Non-linearity for 1S1R Integration

Memristor devices have been extensively studied as one of the most promising technologies for next-generation non-volatile memory. However, for the memristor devices to have a real technological impact, they must be densely packed in a large crossbar array (CBA) exceeding Gigabytes in size. Devising a selector device that is CMOS compatible, 3D stackable, and has a high non-linearity (NL) and great endurance is a crucial enabling ingredient to reach this goal. Tunneling based selectors are very promising in these aspects, but the mediocre NL value limits their applications in large passive crossbar arrays. In this work, we demonstrated a trilayer tunneling selector based on the Ge/Pt/TaN 1+x /Ta 2 O 5 /TaN 1+x /Pd layers that could achieve a NL of 3 × 10 5 , which is the highest NL achieved using a tunnel selector so far. The record-high tunneling NL is partially attributed to the bottom electrode's ultra-smoothness (BE) induced by a Ge/Pt layer. We further demonstrated the feasibility of 1S1R (1-selector 1-resistor) integration by vertically integrating a Pd/Ta 2 O 5 /Ru based memristor on top of the proposed selector.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

Evaluation of fluxon synapse device based on superconducting loops for energy efficient neuromorphic computing

With Moore’s law nearing its end due to the physical scaling limitations of CMOS technology, alternative computing approaches have gained considerable attention as ways to improve computing performance. Here, we evaluate performance prospects of a new approach based on disordered superconducting loops with Josephson-junctions for energy efficient neuromorphic computing. Synaptic weights can be stored as internal trapped fluxon states of three superconducting loops connected with multiple Josephson-junctions (JJ) and modulated by input signals applied in the form of discrete fluxons (quantized flux) in a controlled manner. The stable trapped fluxon state directs the incoming flux through different pathways with the flow statistics representing different synaptic weights. We explore implementation of matrix–vector-multiplication (MVM) operations using arrays of these fluxon synapse devices. We investigate the energy efficiency of online-learning of MNIST dataset. Our results suggest that the fluxon synapse array can provide ~100× reduction in energy consumption compared to other state-of-the-art synaptic devices. This work presents a proof-of-concept that will pave the way for development of high-speed and highly energy efficient neuromorphic computing systems based on superconducting materials.

42 ENGINEERING↗

Quantifying Moss Response to Metal Contaminant Exposure Using Laser-Induced Fluorescence

Tracing sources of contamination, including potentially toxic elements (PTEs), has historically been achieved through sampling and analysis of soil or biota, which are labor-intensive, costly, and destructive methods. Thus, availability of a non-destructive in situ remote sensing method for monitoring metals deposited in biota is of great interest. Laser-induced fluorescence (LIF) is an emerging spectroscopic and imaging technique that documents changes in molecular energy level in plants as a biological response to metal contamination. For a proof-of-concept study and preliminary experiment, moss was selected for experimentation due to its long history of use in tracing atmospheric deposition of PTEs. Consecutive treatments of copper chloride (CuCl2) were administered to three moss samples, simulating wet deposition every 48 h over 10 days until reaching cumulative Cu concentrations of 2.690 to 8.075 μmol/cm2. While these Cu amounts are above environmentally relevant concentrations, they allowed the best conditions for testing and fine tuning of the imaging and data processing protocols presented in this paper. Moss fluorescence was induced using both 532 nm green and 355 nm UV lasers. A CMOS camera captured images of the LIF response, and red–green–blue (RGB) decimal code values were extracted for each pixel in the images, and pixel densities of color channels from treated and untreated moss samples were compared. Results show a shift towards lower color decimal codes corresponding to increased Cu concentration. We developed and contrasted multiple quantitative analyses of color distributions and demonstrated that LIF shows great promise for remote sensing of Cu accumulation in moss at μmol/cm2 levels. Though currently, the method would be limited to highly toxic sites, it illustrates the possibility and provides a framework for development of higher-sensitivity methods to detect nmol/cm2 that are viable for urban contamination level monitoring.

63 RADIATION, THERMAL, AND OTHER ENVIRON. POLLUTAN↗

Epitaxial Integration of Dirac Semimetals with Si(001)

Topological semimetals contain novel combinations of properties that make them useful in a variety of applications, including optoelectronics, spintronics and low energy computing, and catalysis. Although they have been grown with high quality as bulk single crystals, incorporation with semiconductor substrates will ultimately be required to maximize their technological reach. Here, epitaxial growth of the Dirac semimetal Cd3As2 on Si(001) is demonstrated through two routes. First, Cd3As2(112) epilayers are grown on Si(001) via an intermediate CdTe(111) buffer layer. Second, Cd3As2(112) is grown directly on Si(001). This work sets the foundation for integration of novel semimetal materials with existing CMOS technology.

36 MATERIALS SCIENCE↗

Monte Carlo Modeling and Design of Photon Energy Attenuation Layers for >10× Quantum Yield Enhancement in Si-Based Hard X-ray Detectors

High-energy (>20 keV) X-ray photon detection at high quantum yield, high spatial resolution, and short response time has long been an important area of study in physics. Scintillation is a prevalent method but limited in various ways. Directly detecting high-energy X-ray photons has been a challenge to this day, mainly due to low photon-to-photoelectron conversion efficiencies. Commercially available state-of-the-art Si direct detection products such as the Si charge-coupled device (CCD) are inefficient for >10 keV photons. Here, we present Monte Carlo simulation results and analyses to introduce a highly effective yet simple high-energy X-ray detection concept with significantly enhanced photon-to-electron conversion efficiencies composed of two layers: a top high-Z photon energy attenuation layer (PAL) and a bottom Si detector. We use the principle of photon energy down conversion, where high-energy X-ray photon energies are attenuated down to ≤10 keV via inelastic scattering suitable for efficient photoelectric absorption by Si. Our Monte Carlo simulation results demonstrate that a 10–30× increase in quantum yield can be achieved using PbTe PAL on Si, potentially advancing high-resolution, high-efficiency X-ray detection using PAL-enhanced Si CMOS image sensors.

47 OTHER INSTRUMENTATION↗

The SiD Digital ECal Based on Monolithic Active Pixel Sensors

The SiD detector concept capitalizes on high granularity in its tracker and calorimeter to achieve the momentum resolution and particle flow calorimetry physics goals in a compact design. The collaboration has had a long interest in the potential for improved granularity in both the tracker and ECal with an application of monolithic active pixel sensors (MAPS) and a study of MAPS in the SiD ECal was described in the ILC TDR. Work is progressing on the MAPS application in an upgraded SiD design with a prototyping design effort for a common SiD tracker/ECal design based on stitched reticules to achieve 10 × 10 cm2 sensors with 25 × 100 micron2 pixels. Application of large area MAPS in these systems would limit delicate and expensive bump-bonding, provide possibilities for better timing, and should be significantly cheaper than the TDR concept due to being a more conventional CMOS foundry process. The small pixels significantly improve shower separation. Recent simulation studies confirm previous performance projections, indicating electromagnetic energy resolution based on digital hit cluster counting provides better performance than the SiD TDR analog design based on 13 mm2 pixels. Furthermore, the two shower separation is excellent down to the millimeter scale. Geant4 simulation results demonstrate these expectations.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

PbE (E = S, Se) Colloidal Quantum Dot-Layered 2D Material Hybrid Photodetectors

Hybrid lead chalcogenide (PbE) (E = S, Se) quantum dot (QD)-layered 2D systems are an emerging class of photodetectors with unique potential to expand the range of current technologies and easily integrate into current complementary metal-oxide-semiconductor (CMOS)-compatible architectures. Herein, we review recent advancements in hybrid PbE QD-layered 2D photodetectors and place them in the context of key findings from studies of charge transport in layered 2D materials and QD films that provide lessons to be applied to the hybrid system. Photodetectors utilizing a range of layered 2D materials including graphene and transition metal dichalcogenides sensitized with PbE QDs in various device architectures are presented. Figures of merit such as responsivity (R) and detectivity (D*) are reviewed for a multitude of devices in order to compare detector performance. Finally, a look to the future considers possible avenues for future device development, including potential new materials and device treatment/fabrication options.

36 MATERIALS SCIENCE↗

Applications of LIF to Document Natural Variability of Chlorophyll Content and Cu Uptake in Moss

Chlorophyll has long been used as a natural indicator of plant health and photosynthetic efficiency. Laser-induced fluorescence (LIF) is an emerging technique for understanding broad spectrum organic processes and has more recently been used to monitor chlorophyll response in plants. Previous work has focused on developing a LIF technique for imaging moss mats to identify metal contamination with the current focus shifting toward application to moss fronds and aiding sample collection for chemical analysis. Two laser systems (CoCoBi a Nd:YGa pulsed laser system and Chl-SL with two blue continuous semiconductor diodes) were used to collect images of moss fronds exposed to increasing levels of Cu (1, 10, and 100 nmol/cm 2 ) using a CMOS camera. The best methods for the preprocessing of images were conducted before the analysis of fluorescence signatures were compared to a control. The Chl-SL system performed better than the CoCoBi, with dynamic time warping (DTW) proving the most effective for image analysis. Manual thresholding to remove lower decimal code values improved the data distributions and proved whether using one or two fronds in an image was more advantageous. A higher DTW difference from the control correlated to lower chlorophyll a/b ratios and a higher metal content, indicating that LIF, with the aid of image processing, can be an effective technique for identifying Cu contamination shortly after an event.

59 BASIC BIOLOGICAL SCIENCES↗

Dynamically Reconfigurable Data Readout of Pixel Detectors for Automatic Synchronization with Data Acquisition Systems

Reconfigurable detectors with dynamically selectable sensing and readout modes are highly desirable for implementing edge computing as well as enabling advanced imaging techniques such as foveation. The concept of a camera system capable of simultaneous passive imaging and dynamic ranging in different regions of the detector is presented. Such an adaptive-autonomous detector with both spatial and temporal control requires programmable window of exposure (time frames), ability to switch between readout modes such as full-frame imaging and zero-suppressed data, modification of the number of pixel data bits and independent programmability for distinct detector regions. In this work, a method is presented for seamlessly changing time frames and readout modes without data corruption while still ensuring that the data acquisition system (DAQ) does not need to stop and resynchronize at each change of setting, thus avoiding significant dead time. Data throughput is maximized by using a minimum unique data format, rather than lengthy frame headers, to differentiate between consecutive frames. A data control and transmitter (DCT) synchronizes data transfer from the pixel to the periphery, reconfigures the data to transmit it serially off-chip, while providing optimized decision support based on a DAQ definable mode. Measurements on a test structure demonstrate that the DCT can operate at 1 GHz in a 65 nm LP CMOS process.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

LGAD-Based Silicon Sensors for 4D Detectors

Low-Gain Avalanche Diodes (LGAD) are a class of silicon sensors developed for the fast detection of Minimum Ionizing Particles (MIPs). The development was motivated by the need of resolving piled-up tracks of charged particles emerging from several vertexes originating from the same bunch-crossing in High-Energy Physics (HEP) collider experiments, which, however, are separated not only in space but also in time by a few tens of picoseconds. Built on thin silicon substrates and featuring an internal moderate gain, they provide fast signals for excellent timing performance, which are therefore useful to distinguish the different tracks. Unfortunately, this comes at the price of poor spatial resolution. To overcome this limitation, other families of LGAD-based silicon sensors which can deliver in the same substrate both excellent timing and spatial information are under development. Such devices are, to name a few, capacitively coupled LGADs (AC-LGAD), deep-junction LGADs (DJ-LGAD) and trench-isolated LGADs (TI-LGADs). These devices can be fabricated by even small-scale research-focused clean rooms for faster development within the scientific community. However, to scale up production, efforts towards integrating these sensor concepts in CMOS substrates, with the obvious advantage of the possibility of integrating part of the read-out electronics in the same substrate, have begun.

spatial resolution↗

A Modular 512-Channel Neural Signal Acquisition ASIC for High-Density 4096 Channel Electrophysiology

The complexity of information processing in the brain requires the development of technologies that can provide spatial and temporal resolution by means of dense electrode arrays paired with high-channel-count signal acquisition electronics. In this work, we present an ultra-low noise modular 512-channel neural recording circuit that is scalable to up to 4096 simultaneously recording channels. The neural readout application-specific integrated circuit (ASIC) uses a dense 8.2 mm × 6.8 mm 2D layout to enable high-channel count, creating an ultra-light 350 mg flexible module. The module can be deployed on headstages for small animals like rodents and songbirds, and it can be integrated with a variety of electrode arrays. The chip was fabricated in a TSMC 0.18 µm 1.8 V CMOS technology and dissipates a total of 125 mW. Each DC-coupled channel features a gain and bandwidth programmable analog front-end along with 14 b analog-to-digital conversion at speeds up to 30 kS/s. Additionally, each front-end includes programmable electrode plating and electrode impedance measurement capability. We present both standalone and in vivo measurements results, demonstrating the readout of spikes and field potentials that are modulated by a sensory input.

47 OTHER INSTRUMENTATION↗

Low-Jitter Clock Receivers for Fast Timing Applications

Precision timing is a key requirement for emerging 4D particle tracking, Positron Emission Tomography (PET), beam and fusion plasma diagnostics, and other systems. Time-to-Digital Converters (TDCs) are commonly used to provide digital estimates of the relative timing between events, but the jitter performance of a TDC can be no better than the performance of the circuits that acquire the pulses and deliver them to the TDC. Several clock receiver and distribution circuits were evaluated, and a differential amplifier with resistive loads driving a pseudo-differential clock distribution network, developed using design guidelines for radiation tolerance and cryogenic compatibility, was fabricated as part of three prototypes: an analog front-end testbed chip for high-precision timing pixel readout, a dedicated TDC evaluation chip, and a Low-Gain Avalanche Detector (LGAD) readout circuit. Based on TDC measurements of the prototypes, we infer that the jitter added by the clock receiver and distribution circuits is less than 2.25 ps-rms. This performance meets the requirements of many future precision timing systems. The clock receiver and on-chip pseudo-differential driver were fabricated in commercial 28-nm CMOS technology and occupy 2288 µm 2 .

47 OTHER INSTRUMENTATION↗

Development of a plan for automating integrated circuit processing

The operations analysis and equipment evaluations pertinent to the design of an automated production facility capable of manufacturing beam-lead CMOS integrated circuits are reported. The overall plan shows approximate cost of major equipment, production rate and performance capability, flexibility, and special maintenance requirements. Direct computer control is compared with supervisory-mode operations. The plan is limited to wafer processing operations from the starting wafer to the finished beam-lead die after separation etching. The work already accomplished in implementing various automation schemes, and the type of equipment which can be found for instant automation are described. The plan is general, so that small shops or large production units can perhaps benefit. Examples of major types of automated processing machines are shown to illustrate the general concepts of automated wafer processing.

Source record↗