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At least 721 records · Page 40
All sourcesNASA NTRSDOE OSTI
NASA NTRS2007

An Evaluation of High Temperature Airframe Seals for Advanced Hypersonic Vehicles

High temperature seals are required for advanced hypersonic airframe applications. In this study, both spring tube thermal barriers and innovative wafer seal systems were evaluated under relevant hypersonic test conditions (temperatures, pressures, etc.) via high temperature compression testing and room temperature flow assessments. Thermal barriers composed of a Rene 41 spring tube filled with Saffil insulation and overbraided with a Nextel 312 sheath showed acceptable performance at 1500 F in both short term and longer term compression testing. Nextel 440 thermal barriers with Rene 41 spring tubes and Saffil insulation demonstrated good compression performance up to 1750 F. A silicon nitride wafer seal/compression spring system displayed excellent load performance at temperatures as high as 2200 F and exhibited room temperature leakage values that were only 1/3 those for the spring tube rope seals. For all seal candidates evaluated, no significant degradation in leakage resistance was noted after high temperature compression testing. In addition to these tests, a superalloy seal suitable for dynamic seal applications was optimized through finite element techniques.

DeMange, Jeffrey J.↗
NASA NTRS1988

Cross-contact chain

A system is provided for use with wafers that include multiple integrated circuits that include two conductive layers in contact at multiple interfaces. Contact chains are formed beside the integrated circuits, each contact chain formed of the same two layers as the circuits, in the form of conductive segments alternating between the upper and lower layers and with the ends of the segments connected in series through interfaces. A current source passes a current through the series-connected segments, by way of a pair of current tabs connected to opposite ends of the series of segments. While the current flows, voltage measurements are taken between each of a plurality of pairs of voltage tabs, the two tabs of each pair connected to opposite ends of an interface that lies along the series-connected segments. A plot of interface conductances on a normal probability chart, enables prediction of the yield of good integrated circuits from the wafer.

Lieneweg, Udo↗
NASA NTRS1996

Array of micro-machined mass energy micro-filters for charged particles

An energy filter for charged particles includes a stack of micro-machined wafers including plural apertures passing through the stack of wafers, focusing electrodes bounding charged particle paths through the apertures, an entrance orifice to each of the plural apertures and an exit orifice from each of the plural apertures and apparatus for biasing the focusing electrodes with an electrostatic potential corresponding to an energy pass band of the filter.

Stalder, Roland E.↗
NASA NTRS2004

Multi-functional micro electromechanical devices and method of bulk manufacturing same

A method of bulk manufacturing SiC sensors is disclosed and claimed. Materials other than SiC may be used as the substrate material. Sensors requiring that the SiC substrate be pierced are also disclosed and claimed. A process flow reversal is employed whereby the metallization is applied first before the recesses are etched into or through the wafer. Aluminum is deposited on the entire planar surface of the metallization. Photoresist is spun onto the substantially planar surface of the Aluminum which is subsequently masked (and developed and removed). Unwanted Aluminum is etched with aqueous TMAH and subsequently the metallization is dry etched. Photoresist is spun onto the still substantially planar surface of Aluminum and oxide and then masked (and developed and removed) leaving the unimidized photoresist behind. Next, ITO is applied over the still substantially planar surface of Aluminum, oxide and unimidized photoresist. Unimidized and exposed photoresist and ITO directly above it are removed with Acetone. Next, deep reactive ion etching attacks exposed oxide not protected by ITO. Finally, hot phosphoric acid removes the Al and ITO enabling wires to connect with the metallization. The back side of the SiC wafer may be also be etched.

Okojie, Robert S.↗
NASA NTRS1985

Method for making alignment-enhancing feed-through conductors for stackable silicon-on-sapphire

Alignment-enhancing electrically conductive feed-through paths are provided for the high-speed low-loss transfer of electrical signals between integrated circuits of a plurality of silicon-on-sapphire bodies arrayed in a stack. The alignment-enhancing feed-throughs are made by a process of this invention involving the drilling of holes through the body, double-sided sputtering, electroplating, and the filling of the holes with solder by capillary action. The alignment-enhancing feed-throughs are activated by forming a stack of wafers and remelting the solder whereupon the wafers, and the feed-through paths, are pulled into alignment by surface tension forces.

Anthony, Thomas R.↗
NASA NTRS1987

Broadband infrared electro-optic modulator having a buried microstrip network

A microwave infrared modulator having a novel three dimensional structure is presented. The modulator includes a waveguide and metal base with a dielectric wafer buried therebetween. The buried wafer allows for conventional microstrip structures to be employed with larger microstrip electrode dimensions than would otherwise be possible.

Cheo, Peter K.↗
NASA NTRS1990

Integrated circuit reliability testing

A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

Buehler, Martin G.↗
NASA NTRS2004

A Micromachined Geometric Moire Interferometric Floating-Element Shear Stress Sensor

This paper presents the development of a floating-element shear stress sensor that permits the direct measurement of skin friction based on geometric Moir interferometry. The sensor was fabricated using an aligned wafer-bond/thin-back process producing optical gratings on the backside of a floating element and on the top surface of the support wafer. Experimental characterization indicates a static sensitivity of 0.26 microns/Pa, a resonant frequency of 1.7 kHz, and a noise floor of 6.2 mPa/(square root)Hz.

Horowitz, S.↗
NASA NTRS2008

MEMS Microshutter Array System for James Webb Space Telescope

A complex MEMS microshutter array system has been developed at NASA Goddard Space Flight Center (GSFC) for use as a multi-object aperture array for a Near-Infrared Spectrometer (NIRSpec). The NIRSpec is one of the four major instruments carried by the James Webb Space Telescope (JWST), the next generation of space telescope after the Hubble Space Telescope retires. The microshutter arrays (MSAs) are designed for the selective transmission of light with high efficiency and high contrast. It is demonstrated in Figure 1 how a MSA is used as a multiple object selector in deep space. The MSAs empower the NIRSpec instrument simultaneously collect spectra from more than 100 targets therefore increases the instrument efficiency 100 times or more. The MSA assembly is one of three major innovations on JWST and the first major MEMS devices serving observation missions in space. The MSA system developed at NASA GSFC is assembled with four quadrant fully addressable 365x171 shutter arrays that are actuated magnetically, latched and addressed electrostatically. As shown in Figure 2, each MSA is fabricated out of a 4' silicon-on-insulator (SOI) wafer using MEMS bulk-micromachining technology. Individual shutters are close-packed silicon nitride membranes with a pixel size close to 100x200 pm (Figure 3). Shutters are patterned with a torsion flexure permitting shutters to open 90 degrees with a minimized mechanical stress concentration. In order to prevent light leak, light shields are made on to the surrounding frame of each shutter to cover the gaps between the shutters and the Game (Figure 4). Micro-ribs and sub-micron bumps are tailored on hack walls and light shields, respectively, to prevent sticktion, shown in Figures 4 and 5. JWST instruments are required to operate at cryogenic temperatures as low as 35K, though they are to be subjected to various levels of ground tests at room temperature. The shutters should therefore maintain nearly flat in the entire temperature range between 35K and 300K. Through intensive numerical simulations and experimental studies, an optically opaque and electrically conductive metal-nitride thin film was selected as a coating material deposited on the shutters with the best thermal-expansion match to silicon nitride - the shutter blade thin film material. A shutter image shown in Figure 6 was taken at room temperature, presenting shutters slightly bowing down as expected. Shutters become flat when the temperature decreases to 35K. The MSAs are then bonded to silicon substrates that are fabricated out of 6" single-silicon wafers in the thickness of 2mm. The bonding is conducted using a novel single-sided indium flip-chip bonding technology. Indium bumps fabricated on a substrate are shown in Figure 7. There are 180,000 indium bumps for bonding a flight format MSA array to its substrate. Besides a MSA, each substrate houses five customer-designed ASIC (Application Specific Integrated Circuit) multiplexer/address chips for 2-dimensional addressing, twenty capacitors, two temperature sensors, numbers of resistors and all necessary interconnects, as shown in Figure 8. Complete MSA quadrant assemblies have been successfully manufactured and fully functionally tested. The assemblies have passed a series of critical reviews required by JWST in satisfying all the design specifications. The qualification tests cover programmable 2-D addressing, life tests, optical contrast tests, and environmental tests including radiation, vibration, and acoustic tests. A 2-D addressing pattern with 'ESA' letters programmed in a MSA is shown in Figure 9. The MSAs passed 1 million cycle life tests and achieved high optical contrast over 10,000. MSA teams are now making progress in final fabrication, testing and assembly (Figure 10). The delivery of flight-format MSA system is scheduled at the end of 2008 for being integrated to the focal plane of the NIRSpec detectors.

Li, Mary J.↗
NASA NTRS2007

Indium Hybridization of Large Format TES Bolometer Arrays to Readout Multiplexers for Far-Infrared Astronomy

The advance of new detector technologies combined with enhanced fabrication methods has resulted in an increase in development of large format arrays. The next generation of scientific instruments will utilize detectors containing hundreds to thousands of elements providing a more efficient means to conduct large area sky surveys. Some notable detectors include a 32x32 x-ray microcalorimeter for Constellation-X, an infrared bolometer called SAFIRE to fly on the airborne observatory SOFIA, and the sub-millimeter bolometer SCUBA-2 to be deployed at the JCMT which will use more than 10,000 elements for two colors, each color using four 32x40 arrays. Of these detectors, SCUBA-2 is farthest along in development and uses indium hybridization to multiplexers for readout of the large number of elements, a technology that will be required to enable the next generation of large format arrays. Our current efforts in working toward large format arrays have produced GISMO, the Goddard IRAM Superconducting 2-Millimeter observer. GISMO is a far infrared instrument to be field tested later this year at the IRAM 30 meter telescope in Spain. GISMO utilizes transition edge sensor (TES) technology in an 8x16 filled array format that allows for typical fan-out wiring and wire-bonding to four 1x32 NIST multiplexers. GISMO'S electrical wiring is routed along the tops of 30 micron walls which also serve as the mechanical framework for the array. This architecture works well for the 128 element array, but is approaching the limit for routing the necessary wires along the surface while maintaining a high fill factor. Larger format arrays will benefit greatly from making electrical connections through the wafer to the backside, where they can be hybridized to a read-out substrate tailored to handling the wiring scheme. The next generation array we are developing is a 32x40 element array on a pitch of 1135 microns that conforms to the NIST multiplexer, already developed for the SCUBA-2 instrument This architecture will utilize electrical connections that route from the TES to the support frame and through the wafer. The detector chip will then be hybridized to the NIST multiplexer via indium bump bonding. In our development scheme we are using substrates that allow for diagnostic testing of electrical continuity across the entire array and we are testing our process to minimize or eliminate any contact resistance at metal interfaces. Our goal is hybridizing a fully functional 32x40 array of TES bolometers to a NIST multiplexer. The following work presents our current progress toward enabling this technology.

Miller, Timothy M.↗
NASA NTRS2008

NASA Tech Briefs, September 2008

Topics covered include: Nanotip Carpets as Antireflection Surfaces; Nano-Engineered Catalysts for Direct Methanol Fuel Cells; Capillography of Mats of Nanofibers; Directed Growth of Carbon Nanotubes Across Gaps; High-Voltage, Asymmetric-Waveform Generator; Magic-T Junction Using Microstrip/Slotline Transitions; On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz; Group-III Nitride Field Emitters; HEMT Amplifiers and Equipment for their On-Wafer Testing; Thermal Spray Formation of Polymer Coatings; Improved Gas Filling and Sealing of an HC-PCF; Making More-Complex Molecules Using Superthermal Atom/Molecule Collisions; Nematic Cells for Digital Light Deflection; Improved Silica Aerogel Composite Materials; Microgravity, Mesh-Crawling Legged Robots; Advanced Active-Magnetic-Bearing Thrust- Measurement System; Thermally Actuated Hydraulic Pumps; A New, Highly Improved Two-Cycle Engine; Flexible Structural-Health-Monitoring Sheets; Alignment Pins for Assembling and Disassembling Structures; Purifying Nucleic Acids from Samples of Extremely Low Biomass; Adjustable-Viewing-Angle Endoscopic Tool for Skull Base and Brain Surgery; UV-Resistant Non-Spore-Forming Bacteria From Spacecraft-Assembly Facilities; Hard-X-Ray/Soft-Gamma-Ray Imaging Sensor Assembly for Astronomy; Simplified Modeling of Oxidation of Hydrocarbons; Near-Field Spectroscopy with Nanoparticles Deposited by AFM; Light Collimator and Monitor for a Spectroradiometer; Hyperspectral Fluorescence and Reflectance Imaging Instrument; Improving the Optical Quality Factor of the WGM Resonator; Ultra-Stable Beacon Source for Laboratory Testing of Optical Tracking; Transmissive Diffractive Optical Element Solar Concentrators; Delaying Trains of Short Light Pulses in WGM Resonators; Toward Better Modeling of Supercritical Turbulent Mixing; JPEG 2000 Encoding with Perceptual Distortion Control; Intelligent Integrated Health Management for a System of Systems; Delay Banking for Managing Air Traffic; and Spline-Based Smoothing of Airfoil Curvatures.

Source record↗
NASA NTRS2008

Carbon nanotube switches for memory, RF communications and sensing applications, and methods of making the same

Switches having an in situ grown carbon nanotube as an element thereof, and methods of fabricating such switches. A carbon nanotube is grown in situ in mechanical connection with a conductive substrate, such as a heavily doped silicon wafer or an SOI wafer. The carbon nanotube is electrically connected at one location to a terminal. At another location of the carbon nanotube there is situated a pull electrode that can be used to elecrostatically displace the carbon nanotube so that it selectively makes contact with either the pull electrode or with a contact electrode. Connection to the pull electrode is sufficient to operate the device as a simple switch, while connection to a contact electrode is useful to operate the device in a manner analogous to a relay. In various embodiments, the devices disclosed are useful as at least switches for various signals, multi-state memory, computational devices, and multiplexers.

Kaul, Anupama B.↗
NASA NTRS2008

Method for implementation of back-illuminated CMOS or CCD imagers

A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

Pain, Bedabrata↗
NASA NTRS2008

Nano-Multiplication-Region Avalanche Photodiodes and Arrays

Nano-multiplication-region avalanche photodiodes (NAPDs), and imaging arrays of NAPDs integrated with complementary metal oxide/semiconductor (CMOS) active-pixel-sensor integrated circuitry, are being developed for applications in which there are requirements for high-sensitivity (including photoncounting) detection and imaging at wavelengths from about 250 to 950 nm. With respect to sensitivity and to such other characteristics as speed, geometric array format, radiation hardness, power demand of associated circuitry, size, weight, and robustness, NAPDs and arrays thereof are expected to be superior to prior photodetectors and arrays including CMOS active-pixel sensors (APSs), charge-coupled devices (CCDs), traditional APDs, and microchannelplate/ CCD combinations. Figure 1 depicts a conceptual NAPD array, integrated with APS circuitry, fabricated on a thick silicon-on-insulator wafer (SOI). Figure 2 presents selected aspects of the structure of a typical single pixel, which would include a metal oxide/semiconductor field-effect transistor (MOSFET) integrated with the NAPD. The NAPDs would reside in silicon islands formed on the buried oxide (BOX) layer of the SOI wafer. The silicon islands would be surrounded by oxide-filled insulation trenches, which, together with the BOX layer, would constitute an oxide embedding structure. There would be two kinds of silicon islands: NAPD islands for the NAPDs and MOSFET islands for in-pixel and global CMOS circuits. Typically, the silicon islands would be made between 5 and 10 m thick, but, if necessary, the thickness could be chosen outside this range. The side walls of the silicon islands would be heavily doped with electron-acceptor impurities (p+-doped) to form anodes for the photodiodes and guard layers for the MOSFETs. A nanoscale reach-through structure at the front (top in the figures) central position of each NAPD island would contain the APD multiplication region. Typically, the reach-through structure would be about 0.1 microns in diameter and between 0.3 and 0.4 nm high. The top layer in the reach-through structure would be heavily doped with electron-donor impurities (n+-doped) to make it act as a cathode. A layer beneath the cathode, between 0.1 and 0.2 nm thick, would be p-doped to a concentration .10(exp 17)cu cm. A thin n+-doped polysilicon pad would be formed on the top of the cathode to protect the cathode against erosion during a metal-silicon alloying step that would be part of the process of fabricating the array.

Zheng, Xinyu↗
NASA NTRS2009

Improved Starting Materials for Back-Illuminated Imagers

An improved type of starting materials for the fabrication of silicon-based imaging integrated circuits that include back-illuminated photodetectors has been conceived, and a process for making these starting materials is undergoing development. These materials are intended to enable reductions in dark currents and increases in quantum efficiencies, relative to those of comparable imagers made from prior silicon-on-insulator (SOI) starting materials. Some background information is prerequisite to a meaningful description of the improved starting materials and process. A prior SOI starting material, depicted in the upper part the figure, includes: a) A device layer on the front side, typically between 2 and 20 m thick, made of p-doped silicon (that is, silicon lightly doped with an electron acceptor, which is typically boron); b) A buried oxide (BOX) layer (that is, a buried layer of oxidized silicon) between 0.2 and 0.5 m thick; and c) A silicon handle layer (also known as a handle wafer) on the back side, between about 600 and 650 m thick. After fabrication of the imager circuitry in and on the device layer, the handle wafer is etched away, the BOX layer acting as an etch stop. In subsequent operation of the imager, light enters from the back, through the BOX layer. The advantages of back illumination over front illumination have been discussed in prior NASA Tech Briefs articles.

Pain, Bedabrata↗
NASA NTRS2009

Radiometer on a Chip

The radiometer on a chip (ROC) integrates whole wafers together to p rovide a robust, extremely powerful way of making submillimeter rece ivers that provide vertically integrated functionality. By integratin g at the wafer level, customizing the interconnects, and planarizing the transmission media, it is possible to create a lightweight asse mbly performing the function of several pieces in a more conventiona l radiometer.

Chattopadhyay, Goutam↗
NASA NTRS2010

A Two-Axis Direct Fluid Shear Stress Sensor

This innovation is a miniature or micro sized semiconductor sensor design that provides two axis direct non-intrusive measurement of skin friction or wall shear stress in fluid flow. The sensor is fabricated by micro-electro-mechanical system (MEMS) technology, enabling small size and low cost reproductions. The sensors have been fabricated by utilizing MEMS fabrication processes to bond a sensing element wafer to a fluid coupling wafer. This layering technique provides for an out of plane dimension that is on the same order of length as the inplane dimensions. The sensor design has the following characteristics: a shear force collecting plate with dimensions that can be tailored to various application specific requirements such as spatial resolution, temporal resolution and shear force range and resolution. This plate is located coplanar to both the sensor body and flow boundary, and is connected to a dual axis gimbal structure by a connecting column or lever arm. The dual axis gimbal structure has torsional hinges with embedded piezoresistive torsional strain gauges which provide a voltage output that is correlated to the applied shear stress (and excitation current) on force collection plate that is located on the flow boundary surface (hence the transduction method). This combination of design elements create a force concentration and resolution structure that enables the generation of a large stress on the strain gauge from the small shear stress on the flow boundary wall. This design as well as the use of back side electrical contacts establishes a non-intrusive method to quantitatively measure the shear force vector on aerodynamic bodies.

Adcock, Edward E.↗
NASA NTRS2010

Fabrication of Single, Vertically Aligned Carbon Nanotubes in 3D Nanoscale Architectures

Plasma-enhanced chemical vapor deposition (PECVD) and high-throughput manufacturing techniques for integrating single, aligned carbon nanotubes (CNTs) into novel 3D nanoscale architectures have been developed. First, the PECVD growth technique ensures excellent alignment of the tubes, since the tubes align in the direction of the electric field in the plasma as they are growing. Second, the tubes generated with this technique are all metallic, so their chirality is predetermined, which is important for electronic applications. Third, a wafer-scale manufacturing process was developed that is high-throughput and low-cost, and yet enables the integration of just single, aligned tubes with nanoscale 3D architectures with unprecedented placement accuracy and does not rely on e-beam lithography. Such techniques should lend themselves to the integration of PECVD grown tubes for applications ranging from interconnects, nanoelectromechanical systems (NEMS), sensors, bioprobes, or other 3D electronic devices. Chemically amplified polyhydroxystyrene-resin-based deep UV resists were used in conjunction with excimer laser-based (lambda = 248 nm) step-and-repeat lithography to form Ni catalyst dots = 300 nm in diameter that nucleated single, vertically aligned tubes with high yield using dc PECVD growth. This is the first time such chemically amplified resists have been used, resulting in the nucleation of single, vertically aligned tubes. In addition, novel 3D nanoscale architectures have been created using topdown techniques that integrate single, vertically aligned tubes. These were enabled by implementing techniques that use deep-UV chemically amplified resists for small-feature-size resolution; optical lithography units that allow unprecedented control over layer-to-layer registration; and ICP (inductively coupled plasma) etching techniques that result in near-vertical, high-aspect-ratio, 3D nanoscale architectures, in conjunction with the use of materials that are structurally and chemically compatible with the high-temperature synthesis of the PECVD-grown tubes. The techniques offer a wafer-scale process solution for integrating single PECVD-grown nanotubes into novel architectures that should accelerate their integration in 3D electronics in general. NASA can directly benefit from this technology for its extreme-environment planetary missions. Current Si transistors are inherently more susceptible to high radiation, and do not tolerate extremes in temperature. These novel 3D nanoscale architectures can form the basis for NEMS switches that are inherently less susceptible to radiation or to thermal extremes.

Kaul, Anupama B.↗