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An attempt is made to relate the electrical properties of silicon dioxide film to the process history. A model is proposed to explain some of the observed results. It is shown that with our present knowledge of the dielectric, silicon dioxide film shows a lot of promise for its use in surface passivation, both for its resistance to impurity diffusion and for its resistance to radiation damage effects.
Semiconductors made to accept precise etching after pretreatment. Combination of material destabilization and anisotropic etching permits formation of precise perpendicular-wall cavities in silicon wafers and other semiconductors. New technique extends capabilities of current micromachining technology to fabrication of submillimeter waveguide arrays and filters. Pre-etching process currently used to fabricate thin-walled arrays of submillimeter waveguides for use as dichroic bandpass filters. Possible applications include integration of sensor probes and processing of circuitry on same silicon chip.
Continued progress is reported toward development of a silicon on garnet technology which would allow fabrication of advanced detection and signal processing circuits on bubble memories. The first integrated detectors and propagation patterns have been designed and incorporated on a new mask set. In addition, annealing studies on spacer layers are performed. Based on those studies, a new double layer spacer is proposed which should reduce contamination of the silicon originating in the substrate. Finally, the magnetic sensitivity of uncontaminated detectors from the last lot of wafers is measured. The measured sensitivity is lower than anticipated but still higher than present magnetoresistive detectors.
The power requirements for specific float zone experiments in space are presented. Power figures for the Space Shuttle and projected available power for advanced vehicles are given. The following power related trends are derived: (1) float zone processing of up to 5 cm diameter silicon and 16.0 cm diameter cadmium telluride can be conducted on a Shuttle pallet mission; (2) float zone processing of up to 8.5 cm diameter silicon for 70% total heating efficiency can be conducted on the initial MEC/space platform; (3) projected available host vehicle power for float zone sample heating; (4) induction heating is found to be the most promising heating method; (5) process control and ease of equipment integration into the host vehicle influence heating method selection.
Open-circuit voltages as high as 0.645 V (AM0-25 C) have been obtained by a new process developed for low-resistivity silicon. The method utilizes high-dose phosphorus implantation, followed by furnace annealing and simultaneous oxide growth to form high-efficiency, shallow junctions. The effect of the thermally grown oxide is a reduction of surface recombination velocity; the oxide also acts as a moderately efficient AR coating. Boron doped silicon with resistivities from 0.1 to 0.3 ohm-cm has been processed according to this sequence; results show highest open-circuit voltage is attained with 0.1-ohm-cm starting material. The effects of bandgap narrowing, caused by high doping concentrations in the junction, were also investigated by implanting phosphorus over a wide range of dose levels.
Work is reported aimed at identifying and reducing sources of carrier recombination both in the starting web silicon material and in the processed cells. Cross-sectional transmission electron microscopy measurements of several web cells were made and analyzed. The effect of the heavily twinned region on cell efficiency was modeled, and the modeling results compared to measured values for processed cells. The effects of low energy, high dose hydrogen ion implantation on cell efficiency and diffusion length were examined. Cells were fabricated from web silicon known to have a high diffusion length, with a new double layer antireflection coating being applied to these cells. A new contact system, to be used with oxide passivated cells and which greatly reduces the area of contact between metal and silicon, was designed. The application of DLTS measurements to beveled samples was further investigated.
A folding, multi-platform assembly has been developed for the packaging of a multi-chip microinstrumentation system. The assembly includes three solid platforms connected by flexible micromachined ribbon cables and it can be populated by sensors and electronics from a variety of technologies including surface mount and integrated circuit (IC) processes. The entire structure is fabricated from a four-inch silicon wafer using a simple four mask process and a post-process EDP etch. The micromachined ribbon cables allow the platform assembly to be folded into a three level structure with control electronics on the bottom level, microsensors and interface electronics on the second level, and sensors that need environmental access on the top level. Using the silicon multi-platform assembly, a prototype microinstrumentation system has been developed that includes a microcontroller unit and sensors for measuring temperature, barometric pressure, humidity, altitude, and acceleration as well as a telemetry device for wireless communication. When folded in the three level structure, this microsystem occupies only 5 cc and can be placed in an outer case the size of a wristwatch.
Mackintosh et al. (1978) have reported on the development of a multiple ribbon furnace based on the 'edge defined film fed growth' (EFG) process for the fabrication of silicon ribbon. It has been demonstrated that this technology can meet the requirements for a silicon substrate material to be used in the manufacture of solar panels which can meet requirements regarding a selling price of $0.70/Wp when certain goals in terms of throughput and quality are achieved. These goals for the multiple ribbon technology using 10 cm wide ribbon require simultaneous growth of 12 ribbons by one operator at average speeds of 4 to 4.5 cm/min, and 13% efficient solar cells. A description is presented of the progress made toward achieving these goals. It is concluded that the required performance levels have now been achieved. The separate aspects of technology must now be integrated into a single prototype furnace.
Silicon-chlorine-argon (Si-Cl 2 -Ar) atomic layer etching (ALE) is simulated using classical molecular dynamics (MD). The simulations provide a detailed view into the near-surface region during ALE processing. Bombardment of Ar + ions creates a mixed amorphous region that significantly differs from the picture of ideal ALE. There is also a significant change in the Si etch yield and the etch product distribution as a function of Ar + ion fluence. The Si etch yield is the highest at the beginning of the bombardment step but eventually decays to the physical sputtering yield. Atomic Cl and silicon chlorides are major etch products at the start of an ion bombardment step, but quickly decay. Atomic Si yields remain relatively constant as a function of Ar + ion fluence. As a result, a new schematic of Si-Cl 2 -Ar ALE is presented in order to emphasize the complex behavior observed in MD simulations.
An automated process sequence, to manufacture photovoltaic modules at a capacity of approximately 500 MW per year at a cost of approximately $0.50 per peak watt is described. Verification tests were performed and are reported along with cost predictions.
The new metallization process based on Mo-Sn system was studied. The reaction mechanism of MoO3 and its mixture with Sn was examined. The basic ink composition was modified in order to obtain a low ohmic contact to the cell. The electrical characteristics of the cells were comparable with the existing metallization processes. However, in comparison with the standard processes using silver as the contacting metal, the saving obtained by the use of the new process was substantial.
Some of the noteworthy features of the processes developed in the fabrication of solar cell modules are the handling of long lengths of web, the use of cost effective dip coating of photoresist and antireflection coatings, selective electroplating of the grid pattern and ultrasonic bonding of the cell interconnect. Data on the cells is obtained by means of dark I-V analysis and deep level transient spectroscopy. A histogram of over 100 dentritic web solar cells fabricated in a number of runs using different web crystals shows an average efficiency of over 13%, with some efficiencies running above 15%. Lower cell efficiency is generally associated with low minority carrier time due to recombination centers sometimes present in the bulk silicon. A cost analysis of the process sequence using a 25 MW production line indicates a selling price of $0.75/peak watt in 1986. It is concluded that the efficiency of dentritic web cells approaches that of float zone silicon cells, reduced somewhat by the lower bulk lifetime of the former.
A new hardware approach to implementation of image processing algorithms is described. The approach is based on silicon devices which would permit an independent analog processing channel to be dedicated to evey pixel. A laminar architecture consisting of a stack of planar arrays of the device would form a two-dimensional array processor with a 2-D array of inputs located directly behind a focal plane detector array. A 2-D image data stream would propagate in neuronlike asynchronous pulse coded form through the laminar processor. Such systems would integrate image acquisition and image processing. Acquisition and processing would be performed concurrently as in natural vision systems. The research is aimed at implementation of algorithms, such as the intensity dependent summation algorithm and pyramid processing structures, which are motivated by the operation of natural vision systems. Implementation of natural vision algorithms would benefit from the use of neuronlike information coding and the laminar, 2-D parallel, vision system type architecture. Besides providing a neural network framework for implementation of natural vision algorithms, a 2-D parallel approach could eliminate the serial bottleneck of conventional processing systems. Conversion to serial format would occur only after raw intensity data has been substantially processed. An interesting challenge arises from the fact that the mathematical formulation of natural vision algorithms does not specify the means of implementation, so that hardware implementation poses intriguing questions involving vision science.
The goals for the fabrication of single crystal silicon instrument mirrors include the following: 1) Develop a process for fabricating lightweight mirrors from single crystal silicon (SCS); 2) Modest lightweighting: 3X to 4X less than equivalent solid mirror; 3) High surface quality, better than lambda/40 RMS @ 633nm; 4) Significantly less expensive than current technology; and 5) Negligible distortion when cooled to cryogenic temperatures.
Economical process produces high-purity silicon crystals suitable for use in solar cells. Reaction is strongly exothermic and can be initiated at relatively low temperature, making it potentially suitable for development into low-cost commercial process. Important advantages include exothermic character and comparatively low process temperatures. These could lead to significant savings in equipment and energy costs.
The goal of this research program was to develop a novel technique for focusing x-rays based on the optical system of a lobster's eye. A lobster eye employs many closely packed reflecting surfaces arranged within a spherical or cylindrical shell. These optics have two unique properties: they have unlimited fields of view and can be manufactured via replication of identical structures. Because the angular resolution is given by the ratio of the size of the individual optical elements to the focal length, optical elements with size on the order of one hundred microns are required to achieve good angular resolution with a compact telescope. We employed anisotropic etching of single crystal silicon wafers for the fabrication of micron-scale optical elements. This technique, commonly referred to as silicon micromachining, is based on silicon fabrication techniques developed by the microelectronics industry. We have succeeded in producing silicon lenses with a geometry suitable for a 1-d focusing x-ray optics. These lenses have an aspect ratio (40:1) suitable for x-ray reflection and have very good optical surface alignment. We have developed a number of process refinements which improved the quality of the lens geometry and the repeatability of the etch process. In addition to the silicon fabrication, an x-ray beam line was constructed at Columbia for testing the optics. Most recently, we have done several experiments to find the fundamental limits that the anisotropic etch process placed on the etched surface roughness.
The National Aeronautics and Space Administration (NASA) of the United States of America (US) has initiated the Artemis Moon to Mars program to send astronauts (the first woman and person of color) back to the lunar surface, create a sustainable human lunar exploration program, and lead the first human exploration mission to the Mars surface in the 2030’s. A major objective of this program is to characterize the resources that exist on the Moon and Mars, and learn how to utilize them for sustained and affordable exploration. Commonly known as In Situ Resource Utilization (ISRU), the search for, acquisition, and processing of resources in space has the potential to greatly reduce the dependency on transporting mission consumables and infrastructure from Earth, thereby reducing mission costs, risks, and dependency on Earth. Through the extraction and processing of resources into mission commodities such as rocket propellants, life support consumables, and fuel cell reactants, ISRU enhances and evolves the cis-lunar, lander, and surface transportation systems required for human exploration; expanding and ehancing HOW humans get to, explore, and return from the Moon. Through the extraction and processing of resources into metals, silicon, and other manufacturing and construction feedstock, ISRU enhances and allows for the expansion of critical infrastructure through in situ manufacturing and construction capabilities needed for WHAT humans do on the Moon and in cis-lunar space. Because of this, ISRU supports and enables commercial involvement beyond NASA and governmental agencies by both lowering the cost of sustained transportation to/from/on the Moon as well as supporting the market required for needing these transportation systems. To achieve this vision, NASA’s Space Technology Mission Directorate (STMD) ensures the coordinated development of ISRU and other critical space and surface infrastructure elements such as propulsion, power, manufacturing, construction, and robotics through the Strategic Technology Architecture Roundtable (STAR) process. Through STAR, an integrated framework and process has been created allowing for capabilities and technologies to be linked and assessed, gaps to be identified, specifications and metrics to be established, and provide a means to prioritize and implement technology development and missions. For lunar ISRU, three primary areas of development have been initiated, (1) understanding, mapping, extracting, and processing water and other volatiles found in polar permanently shadowed regions (PSRs), (2) methods, technologies to extract oxygen from regolith, and (3) methods, technologies, and use cases for metals, silicon, and other feedstock commodities extracted and produced from lunar resources. This presentation will briefly discuss the STAR process and elaborate on the current status and future plans for ISRU development, demonstration, and architecture implementation of NASA’s Envisioned Future Priorities plan for ISRU.
An innovation was created for the Cosmology Large Angular Scale Surveyor for integration of low-temperature detector chips with a silicon backshort and a silicon photonic choke through flipchip bonding. Indium bumps are typically patterned using liftoff processes, which require thick resist. In some applications, it is necessary to locate the bumps close to high-aspect-ratio structures such as wafer through-holes. In those cases, liftoff processes are challenging, and require complicated and time-consuming spray coating technology if the high-aspect-ratio structures are delineated prior to the indium bump process. Alternatively, processing the indium bumps first is limited by compatibility of the indium with subsequent processing. The present invention allows for locating bumps arbitrarily close to multiple-level high-aspect-ratio structures, and for indium bumps to be formed without liftoff resist. The process uses the poor step coverage of indium deposited on a silicon wafer that has been previously etched to delineate the location of the indium bumps. The silicon pattern can be processed through standard lithography prior to adding the high-aspect-ratio structures. Typically, high-aspectratio structures require a thick resist layer so this layer can easily cover the silicon topography. For multiple levels of topography, the silicon can be easily conformally coated through standard processes. A blanket layer of indium is then deposited onto the full wafer; bump bonding only occurs at the high points of the topography.