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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 721 records · Page 40
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

A Simple, Scalable, Script-based Science Processor

The production of Earth Science data from orbiting spacecraft is an activity that takes place 24 hours a day, 7 days a week. At the Goddard Earth Sciences Distributed Active Archive Center (GES DAAC), this results in as many as 16,000 program executions each day, far too many to be run by human operators. In fact, when the Moderate Resolution Imaging Spectroradiometer (MODIS) was launched aboard the Terra spacecraft in 1999, the automated commercial system for running science processing was able to manage no more than 4,000 executions per day. Consequently, the GES DAAC developed a lightweight system based on the popular Per1 scripting language, named the Simple, Scalable, Script-based Science Processor (S4P). S4P automates science processing, allowing operators to focus on the rare problems occurring from anomalies in data or algorithms. S4P has been reused in several systems ranging from routine processing of MODIS data to data mining and is publicly available from NASA.

Lynnes, Christopher↗
NASA NTRS2004

Performance Assessment of ISS Water Processor Assembly Reactor

Due to modifications to the ISS waste water composition, the concentration of volatile organics has significantly increased in the feed to the Water Processor Assembly (WPA). In parallel, the oxygen supply pressure increased, resulting in a higher flow rate of oxygen to the WPA. Preliminary testing at Hamilton Sund strand indicated that the higher oxygen flow rate would increase the WPA capacity for volatile organics. Following an analysis of the expected waste water composition, personnel at NASA MSFC and Hamilton Sundstrand conducted a test of a flight-like reactor to assess its capacity for the higher organic loads. The results of this test indicate the WPA can accommodate the expected organic load in the ISS waste water with margin.

Carter, Layne↗
NASA NTRS2004

A Discussion of Using a Reconfigurable Processor to Implement the Discrete Fourier Transform

This paper presents the design and implementation of the Discrete Fourier Transform (DFT) algorithm on a reconfigurable processor system. While highly applicable to many engineering problems, the DFT is an extremely computationally intensive algorithm. Consequently, the eventual goal of this work is to enhance the execution of a floating-point precision DFT algorithm by off loading the algorithm from the computing system. This computing system, within the context of this research, is a typical high performance desktop computer with an may of field programmable gate arrays (FPGAs). FPGAs are hardware devices that are configured by software to execute an algorithm. If it is desired to change the algorithm, the software is changed to reflect the modification, then download to the FPGA, which is then itself modified. This paper will discuss methodology for developing the DFT algorithm to be implemented on the FPGA. We will discuss the algorithm, the FPGA code effort, and the results to date.

White, Michael J.↗
NASA NTRS1999

Ion Thruster and Power Processor Developed for the Deep Space 1 Mission

The NASA Solar Electric Propulsion Technology Applications Readiness (NSTAR) Program has provided a single-string primary propulsion system to NASA's Deep Space 1 spacecraft. This spacecraft will carry about 81 kg of xenon propellant for the ion thruster, which can be throttled down from 2.3 to 0.5 kW as the spacecraft moves away from the Sun. The propellant load will provide about 20 months of propulsion at the one-half power throttle setpoint of 1.2 kW. This mission will validate the 2.5-kW ion propulsion system and will fly by the asteroid 1992 KD in 1999. If funding permits, Deep Space 1 also will encounter comets Wilson-Harrington and Borrelly in 2001. NASA Lewis Research Center's On-Board Propulsion Branch was responsible for the development of the 30-cm-diameter ion thruster, the 2.5-kW power processor unit (PPU), and the Digital Control and Interface Unit (DCIU) that controls the PPU/thruster/feed system and provides data and recovery from fault conditions. Lewis transferred the thruster and PPU technologies to the Hughes Electron Dynamics Division, which was selected to build two sets of flight thrusters, as well as the PPU's and DCIU's. Hughes subcontracted the DCIU development to Spectrum Astro Incorporated. The Jet Propulsion Laboratory (JPL) was primarily responsible for the NSTAR project management, thruster lifetests, the feed system, diagnostics, and the propulsion subsystem integration. A total of four engineering model thrusters and three breadboard PPU's were built, integrated, and tested. More than 50 development tests were conducted along with thruster design verification tests of 2000 and 1000 hours. In addition, an 8000-hr life demonstration test was successfully completed and demonstrated wear-rates consistent with full-power lifetimes in excess of 12,000 hours.

Sovey, James S.↗
NASA NTRS2005

Performance Qualification Test of the ISS Water Processor Assembly (WPA) Expendables

The Water Processor Assembly (WPA) for use on the International Space Station (ISS) includes various technologies for the treatment of waste water. These technologies include filtration, ion exchange, adsorption, catalytic oxidation, and iodination. The WPA hardware implementing portions of these technologies, including the Particulate Filter, Multifiltration Bed, Ion Exchange Bed, and Microbial Check Valve, was recently qualified for chemical performance at the Marshall Space Flight Center. Waste water representing the quality of that produced on the ISS was generated by test subjects and processed by the WPA. Water quality analysis and instrumentation data was acquired throughout the test to monitor hardware performance. This paper documents operation of the test and the assessment of the hardware performance.

Carter, Layne↗
NASA NTRS2005

Implementation of a High-Speed FPGA and DSP Based FFT Processor for Improving Strain Demodulation Performance in a Fiber-Optic-Based Sensing System

NASA's Aviation Safety and Security Program is pursuing research in on-board Structural Health Management (SHM) technologies for purposes of reducing or eliminating aircraft accidents due to system and component failures. Under this program, NASA Langley Research Center (LaRC) is developing a strain-based structural health-monitoring concept that incorporates a fiber optic-based measuring system for acquiring strain values. This fiber optic-based measuring system provides for the distribution of thousands of strain sensors embedded in a network of fiber optic cables. The resolution of strain value at each discrete sensor point requires a computationally demanding data reduction software process that, when hosted on a conventional processor, is not suitable for near real-time measurement. This report describes the development and integration of an alternative computing environment using dedicated computing hardware for performing the data reduction. Performance comparison between the existing and the hardware-based system is presented.

Farley, Douglas L.↗
NASA NTRS2002

High speed optical object recognition processor with massive holographic memory

Real-time object recognition using a compact grayscale optical correlator will be introduced. A holographic memory module for storing a large bank of optimum correlation filters, to accommodate the large data throughput rate needed for many real-world applications, has also been developed. System architecture of the optical processor and the holographic memory will be presented. Application examples of this object recognition technology will also be demonstrated.

512 X 512 grayscale optical correlator holographic↗
NASA NTRS2000

PTEP: the Parallel Telemetry Processor

The Parallel Telemetry Processor (PTEP), a high-speed, robust, and extensible telemetry processing system is discussed in this paper.

downloading telemetry processing operations↗
NASA NTRS1996

Optimization of Particle-in-Cell Codes on RISC Processors

General strategies are developed to optimize particle-cell-codes written in Fortran for RISC processors which are commonly used on massively parallel computers. These strategies include data reorganization to improve cache utilization and code reorganization to improve efficiency of arithmetic pipelines.

particle-cell-codes cache utilization code reorgan↗
NASA NTRS1996

The RADARSAT Geophysical Processor System

The RADARSAT Geophysical Processor System (RGPS) is a processing system dedicated to the analysis of Synthetic Aperture Radar (SAR) data of sea ice collected by the Canadian RADARSAT satellite (Raney et al., 1991).

radarsat ice sea ice polar ice arctic ocean sar sy↗
NASA NTRS2006

Texas Instruments-Digital Signal Processor(TI-DSP)SMJ320F20 SEL Testing

This viewgraph presentation reviews the testing of the Texas Instrument Digital Signal Processor(TI-DSP)SMJ320F20. Tests were performed to screen for susceptibility to Single Event Latchup (SEL) and measure sensitivity as a function of Linear Energy Transfer (LET) for an application specific test setup. The Heavy Ion Testing of two TI-DSP SMJ320F240 devices experienced Single Event Latchup (SEL) conditions at an LET of 1.8 MeV/(mg/square cm) The devices were exposed from a fluence of 1.76 x l0(exp 3) to 5.00 x 10(exp 6) particles/square cm of the Neon, Argon and Krypton ion beams. For DI(sub DD) an average latchup current occurred at about 700mA, which is a magnitude of 10 over the nominal current of 700mA.

Sanders, Anthony B.↗
NASA NTRS1993

Imer-product array processor for retrieval of stored images represented by bipolar binary (+1,-1) pixels using partial input trinary pixels represented by (+1,-1)

An inner-product array processor is provided with thresholding of the inner product during each iteration to make more significant the inner product employed in estimating a vector to be used as the input vector for the next iteration. While stored vectors and estimated vectors are represented in bipolar binary (1,-1), only those elements of an initial partial input vector that are believed to be common with those of a stored vector are represented in bipolar binary; the remaining elements of a partial input vector are set to 0. This mode of representation, in which the known elements of a partial input vector are in bipolar binary form and the remaining elements are set equal to 0, is referred to as trinary representation. The initial inner products corresponding to the partial input vector will then be equal to the number of known elements. Inner-product thresholding is applied to accelerate convergence and to avoid convergence to a negative input product.

Liu, Hua-Kuang↗
NASA NTRS1980

Sample processor for chemical analysis

An apparatus is provided which can process numerous samples that must be chemically analyzed by the application of fluids such as liquid reagents, solvents and purge gases, as well as the application of dumps for receiving the applied fluid after they pass across the sample, in a manner that permits numerous samples to be processed in a relatively short time and with minimal manpower. The processor includes a rotor which can hold numerous cartridges containing inert or adsorbent material for holding samples, and a pair of stators on opposite sides of the rotor. The stators form stations spaced along the path of the cartridges which lie in the rotor, and each station can include an aperture in one stator through which a fluid can be applied to a cartridge resting at that station, and an aperture in the other stator which can receive the fluid which has passed through the cartridge. The stators are sealed to the ends of the cartridges lying on the rotor, to thereby isolate the stations from one another.

Boettger, Heinz G.↗
NASA NTRS2006

Real Time Phase Noise Meter Based on a Digital Signal Processor

A digital signal-processing meter for phase noise measurement on sinusoidal signals is dealt with. It enlists a special hardware architecture, made up of a core digital signal processor connected to a data acquisition board, and takes advantage of a quadrature demodulation-based measurement scheme, already proposed by the authors. Thanks to an efficient measurement process and an optimized implementation of its fundamental stages, the proposed meter succeeds in exploiting all hardware resources in such an effective way as to gain high performance and real-time operation. For input frequencies up to some hundreds of kilohertz, the meter is capable both of updating phase noise power spectrum while seamlessly capturing the analyzed signal into its memory, and granting as good frequency resolution as few units of hertz.

phase noise↗
NASA NTRS2008

Impacts of the IBM Cell Processor to Support Climate Models

NASA is interested in the performance and cost benefits for adapting its applications to the IBM Cell processor. However, its 256KB local memory per SPE and the new communication mechanism, make it very challenging to port an application. We selected the solar radiation component of the NASA GEOS-5 climate model, which: (1) is representative of column physics (approximately 50% computational time), (2) has a high computational load relative to transferring data from and to main memory, (3) performs independent calculations across multiple columns. We converted the baseline code (single-precision, Fortran) to C and ported it with manually SIMDizing 4 independent columns and found that a Cell with 8 SPEs can process 2274 columns per second. Compared with the baseline results, the Cell is approximately 5.2X, approximately 8.2X, approximately 15.1X faster than a core on Intel Woodcrest, Dempsey, and Itanium2, respectively. We believe this dramatic performance improvement makes a hybrid cluster with Cell and traditional nodes competitive.

Zhou, Shujia↗
NASA NTRS2010

The Mission Assessment Post Processor (MAPP): A New Tool for Performance Evaluation of Human Lunar Missions

The National Aeronautics and Space Administration s (NASA) Constellation Program paves the way for a series of lunar missions leading to a sustained human presence on the Moon. The proposed mission design includes an Earth Departure Stage (EDS), a Crew Exploration Vehicle (Orion) and a lunar lander (Altair) which support the transfer to and from the lunar surface. This report addresses the design, development and implementation of a new mission scan tool called the Mission Assessment Post Processor (MAPP) and its use to provide insight into the integrated (i.e., EDS, Orion, and Altair based) mission cost as a function of various mission parameters and constraints. The Constellation architecture calls for semiannual launches to the Moon and will support a number of missions, beginning with 7-day sortie missions, culminating in a lunar outpost at a specified location. The operational lifetime of the Constellation Program can cover a period of decades over which the Earth-Moon geometry (particularly, the lunar inclination) will go through a complete cycle (i.e., the lunar nodal cycle lasting 18.6 years). This geometry variation, along with other parameters such as flight time, landing site location, and mission related constraints, affect the outbound (Earth to Moon) and inbound (Moon to Earth) translational performance cost. The mission designer must determine the ability of the vehicles to perform lunar missions as a function of this complex set of interdependent parameters. Trade-offs among these parameters provide essential insights for properly assessing the ability of a mission architecture to meet desired goals and objectives. These trades also aid in determining the overall usable propellant required for supporting nominal and off-nominal missions over the entire operational lifetime of the program, thus they support vehicle sizing.

Williams, Jacob↗
NASA NTRS2006

Programs for Testing Processor-in-Memory Computing Systems

The Multithreaded Microbenchmarks for Processor-In-Memory (PIM) Compilers, Simulators, and Hardware are computer programs arranged in a series for use in testing the performances of PIM computing systems, including compilers, simulators, and hardware. The programs at the beginning of the series test basic functionality; the programs at subsequent positions in the series test increasingly complex functionality. The programs are intended to be used while designing a PIM system, and can be used to verify that compilers, simulators, and hardware work correctly. The programs can also be used to enable designers of these system components to examine tradeoffs in implementation. Finally, these programs can be run on non-PIM hardware (either single-threaded or multithreaded) using the POSIX pthreads standard to verify that the benchmarks themselves operate correctly. [POSIX (Portable Operating System Interface for UNIX) is a set of standards that define how programs and operating systems interact with each other. pthreads is a library of pre-emptive thread routines that comply with one of the POSIX standards.]

Katz, Daniel S.↗