Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “out of memory”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 721 records · Page 40

Self-structured, current aperture approach for bubble memory

An approach to magnetic bubble memory which incorporates dual conductor current access drive with a self-structured (strongly interacting) bubble lattice is described. This is expected to provide higher operating speeds, defect tolerance, and higher bit density for a given bubble size as compared to present field access bubble devices. Bubble spacings of 2.5 bubble diameters are projected for a prototype device. Experimental work on device components including detectors, major/minor loops, and gates is described. Defect tolerance has also been demonstrated.

Nelson, G. L.↗

Short-term memory load and pronunciation rate

In a test of short-term memory recall, two subjects attempted to recall various lists. For unpracticed subjects, the time it took to read the list is a better predictor of immediate recall than the number of items on the list. For practiced subjects, the two predictors do about equally well. If the items that must be recalled are unfamiliar, it is advantageous to keep the items short to pronounce. On the other hand, if the same items will be encountered over and over again, it is advantageous to make them distinctive, even at the cost of adding to the number of syllables.

Schweickert, Richard↗

Quantification of the memory imprint effect for a charged particle environment

The effects of total accumulated dose on the single-event vulnerability of NMOS resistive-load SRAMs are investigated. The bias-dependent shifts in device parameters can imprint the memory state present during exposure or erase the imprinted state. Analysis of these effects is presented along with an analytic model developed for the quantification of these effects. The results indicate that the imprint effect is dominated by the difference in the threshold voltage of the n-channel devices.

Bhuva, B. L.↗

Parallel discrete event simulation using shared memory

With traditional event-list techniques, evaluating a detailed discrete-event simulation-model can often require hours or even days of computation time. By eliminating the event list and maintaining only sufficient synchronization to ensure causality, parallel simulation can potentially provide speedups that are linear in the numbers of processors. A set of shared-memory experiments, using the Chandy-Misra distributed-simulation algorithm, to simulate networks of queues is presented. Parameters of the study include queueing network topology and routing probabilities, number of processors, and assignment of network nodes to processors. These experiments show that Chandy-Misra distributed simulation is a questionable alternative to sequential-simulation of most queueing network models.

Reed, Daniel A.↗

Using data tagging to improve the performance of Kanerva's sparse distributed memory

The standard formulation of Kanerva's sparse distributed memory (SDM) involves the selection of a large number of data storage locations, followed by averaging the data contained in those locations to reconstruct the stored data. A variant of this model is discussed, in which the predominant pattern is the focus of reconstruction. First, one architecture is proposed which returns the predominant pattern rather than the average pattern. However, this model will require too much storage for most uses. Next, a hybrid model is proposed, called tagged SDM, which approximates the results of the predominant pattern machine, but is nearly as efficient as Kanerva's original formulation. Finally, some experimental results are shown which confirm that significant improvements in the recall capability of SDM can be achieved using the tagged architecture.

Rogers, David↗

Interfacing laboratory instruments to multiuser, virtual memory computers

Incentives, problems and solutions associated with interfacing laboratory equipment with multiuser, virtual memory computers are presented. The major difficulty concerns how to utilize these computers effectively in a medium sized research group. This entails optimization of hardware interconnections and software to facilitate multiple instrument control, data acquisition and processing. The architecture of the system that was devised, and associated programming and subroutines are described. An example program involving computer controlled hardware for ultrasonic scan imaging is provided to illustrate the operational features.

Generazio, Edward R.↗

Parallel Optical Random Access Memory (PORAM)

It is shown that the need to minimize component count, power and size, and to maximize packing density require a parallel optical random access memory to be designed in a two-level hierarchy: a modular level and an interconnect level. Three module designs are proposed, in the order of research and development requirements. The first uses state-of-the-art components, including individually addressed laser diode arrays, acousto-optic (AO) deflectors and magneto-optic (MO) storage medium, aimed at moderate size, moderate power, and high packing density. The next design level uses an electron-trapping (ET) medium to reduce optical power requirements. The third design uses a beam-steering grating surface emitter (GSE) array to reduce size further and minimize the number of components.

Alphonse, G. A.↗

Feedforward, high density, programmable read only neural network based memory system

Neural network-inspired, nonvolatile, programmable associative memory using thin-film technology is demonstrated. The details of the architecture, which uses programmable resistive connection matrices in synaptic arrays and current summing and thresholding amplifiers as neurons, are described. Several synapse configurations for a high-density array of a binary connection matrix are also described. Test circuits are evaluated for operational feasibility and to demonstrate the speed of the read operation. The results are discussed to highlight the potential for a read data rate exceeding 10 megabits/sec.

Daud, Taher↗

Isotopic anomalies - Chemical memory of Galactic evolution

New mechanisms for the chemical memory of isotopic anomalies are proposed which are based on the temporal change during the chemical evolution of the Galaxy of the isotopic composition of the mean ejecta from stars. Because of the differing temporal evolution of primary and secondary products of nucleosynthesis, the isotopic composition of the bulk interstellar medium changes approximately linearly with time, and thus any dust component having an age different from that of average dust will be isotopically anomalous. Special attention is given to C, O, Mg, Si, and isotopically heavy average-stellar condensates of SiC.

Clayton, Donald D.↗

Capacity for patterns and sequences in Kanerva's SDM as compared to other associative memory models

The information capacity of Kanerva's Sparse Distributed Memory (SDM) and Hopfield-type neural networks is investigated. Under the approximations used here, it is shown that the total information stored in these systems is proportional to the number connections in the network. The proportionality constant is the same for the SDM and Hopfield-type models independent of the particular model, or the order of the model. The approximations are checked numerically. This same analysis can be used to show that the SDM can store sequences of spatiotemporal patterns, and the addition of time-delayed connections allows the retrieval of context dependent temporal patterns. A minor modification of the SDM can be used to store correlated patterns.

Keeler, James D.↗

Terminal attractors for addressable memory in neural networks

A new type of attractors - terminal attractors - for an addressable memory in neural networks operating in continuous time is introduced. These attractors represent singular solutions of the dynamical system. They intersect (or envelope) the families of regular solutions while each regular solution approaches the terminal attractor in a finite time period. It is shown that terminal attractors can be incorporated into neural networks such that any desired set of these attractors with prescribed basins is provided by an appropriate selection of the weight matrix.

Zak, Michail↗

Total dose effect on soft error rate for dynamic metal-oxide-semiconductor memory cells

A simple model for the soft error rate for dynamic metal-oxide-semiconductor random access memories due to normal galactic radiation was devised and then used to calculate the rate of decrease of the single-event-upset rate with total radiation dose. The computation shows that the decrease in the soft error rate is less than 10 percent per day if the shielding is 0.5 g/sq cm and the spacecraft is in a geosynchronous orbit. The decrease is considerably less in a polar orbiting device.

Benumof, Reuben↗

An experimental study of memory fault latency

The difficulty with the measurement of fault latency is due to the lack of observability of the fault occurrence and error generation instants in a production environment. The authors describe an experiment, using data from a VAX 11/780 under real workload, to study fault latency in the memory subsystem accurately. Fault latency distributions are generated for stuck-at-zero (s-a-0) and stuck-at-one (s-a-1) permanent fault models. The results show that the mean fault latency of an s-a-0 fault is nearly five times that of the s-a-1 fault. An analysis of variance is performed to quantify the relative influence of different workload measures on the evaluated latency.

Chillarege, Ram↗

Asymmetric Memory Circuit Would Resist Soft Errors

Some nonlinear error-correcting codes more efficient in presence of asymmetry. Combination of circuit-design and coding concepts expected to make integrated-circuit random-access memories more resistant to "soft" errors (temporary bit errors, also called "single-event upsets" due to ionizing radiation). Integrated circuit of new type made deliberately more susceptible to one kind of bit error than to other, and associated error-correcting code adapted to exploit this asymmetry in error probabilities.

Buehler, Martin G.↗

Nonvolatile Ionic Two-Terminal Memory Device

Conceptual solid-state memory device nonvolatile and erasable and has only two terminals. Proposed device based on two effects: thermal phase transition and reversible intercalation of ions. Transfer of sodium ions between source of ions and electrical switching element increases or decreases electrical conductance of element, turning switch "on" or "off". Used in digital computers and neural-network computers. In neural networks, many small, densely packed switches function as erasable, nonvolatile synaptic elements.

Williams, Roger M.↗

Fast, Capacious Disk Memory Device

Device for recording digital data on, and playing back data from, memory disks has high recording or playback rate and utilizes available recording area more fully. Two disks, each with own reading/writing head, used to record data at same time. Head on disk A operates on one of tracks numbered from outside in; head on disk B operates on track of same number in sequence from inside out. Underlying concept of device applicable to magnetic or optical disks.

Muller, Ronald M.↗

Memory management in traceback Viterbi decoders

The new Viterbi decoder for long constraint length codes, under development for the Deep Space Network, stores path information according to an algorithm called traceback. The details of a particular implementation of this algorithm, based on three memory buffers, are described. The penalties in increased storage requirement and longer decoding delay are offset by the reduced amount of data that needs to be exchanged between processors, in a parallel architecture decoder.

Collins, O.↗

Development of shape memory metal as the actuator of a fail safe mechanism

A small, compact, lightweight device was developed using shape memory alloy (SMA) in wire form to actuate a pin-puller that decouples the flanges of two shafts. When the SMA is heated it contracts producing a useful force and stroke. As it cools, it can be reset (elongated in this case) by applying a relatively small force. Resistive heating is accomplished by running a current through the SMA wire for a controlled length of time. The electronics to drive the device are not elaborate or complicated, consisting of a timed current source. The total available contraction is 3 percent of the length of the wire. This device, the engineering properties of the SMA, and the tests performed to verify the design concept are described.

Ford, V. G.↗