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NASA NTRS2005

A Methodology for the Design and Verification of Globally Asynchronous/Locally Synchronous Architectures

Recent advanced in model-checking have made it practical to formally verify the correctness of many complex synchronous systems (i.e., systems driven by a single clock). However, many computer systems are implemented by asynchronously composing several synchronous components, where each component has its own clock and these clocks are not synchronized. Formal verification of such Globally Asynchronous/Locally Synchronous (GA/LS) architectures is a much more difficult task. In this report, we describe a methodology for developing and reasoning about such systems. This approach allows a developer to start from an ideal system specification and refine it along two axes. Along one axis, the system can be refined one component at a time towards an implementation. Along the other axis, the behavior of the system can be relaxed to produce a more cost effective but still acceptable solution. We illustrate this process by applying it to the synchronization logic of a Dual Fight Guidance System, evolving the system from an ideal case in which the components do not fail and communicate synchronously to one in which the components can fail and communicate asynchronously. For each step, we show how the system requirements have to change if the system is to be implemented and prove that each implementation meets the revised system requirements through modelchecking.

Miller, Steven P.↗
NASA NTRS2006

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.

Irom, Farokh↗
NASA NTRS2001

Kalman plus weights: a time scale algorithm

KPW is a time scale algorithm that combines Kalman filtering with the basic time scale equation (BTSE). A single Kalman filter that estimates all clocks simultaneously is used to generate the BTSE frequency estimates, while the BTSE weights are inversely proportional to the white FM variances of the clocks. Results from simulated clock ensembles are compared to previous simulation results from other algorithms.

time time scales stability Kalman filtering↗
NASA NTRS1993

Ultra low-noise charge coupled device

Special purpose CCD designed for ultra low-noise imaging and spectroscopy applications that require subelectron read noise floors, wherein a non-destructive output circuit operating near its 1/f noise regime is clocked in a special manner to read a single pixel multiple times. Off-chip electronics average the multiple values, reducing the random noise by the square-root of the number of samples taken. Noise floors below 0.5 electrons rms are possible in this manner. In a preferred embodiment of the invention, a three-phase CCD horizontal register is used to bring a pixel charge packet to an input gate adjacent a floating gate amplifier. The charge is then repeatedly clocked back and forth between the input gate and the floating gate. Each time the charge is injected into the potential well of the floating gate, it is sensed non-destructively. The floating gate amplifier is provided with a reference voltage of a fixed value and a pre-charge gate for resetting the amplifier between charge samples to a constant gain. After the charge is repeatedly sampled a selected number of times, it is transferred by means of output gates, back into the horizontal register, where it is clocked in a conventional manner to a diffusion MOSFET amplifier. It can then be either sampled (destructively) one more time or otherwise discarded.

Janesick, James R.↗
NASA NTRS1991

Front-illuminated CCD with open pinned-phase region and two-phase transfer gate regions

A front-illuminated CCD of relative high quantum efficiency (QE) and high charge transfer efficiency (CTE) utilizes an open-phase region for receiving photons and two-phase gate regions (.phi..sub.1 and .phi..sub.2) for transferring electrons collected in one pixel to the next. The open-phase region is implanted with additional n-type elements (phosphorus) in order to increase the potential of the CCD channel in the open-phase region for collection of electrons and additionally implanted with concentrated and very shallow p-type elements (boron) to pin the surface of the n-channel in the open-phase region to OV, while gate region .phi..sub.1 and .phi..sub.2 are biased to -3.5V and driven to +10V by a two-phase transfer clock. The open pinned-phase (OPP) region thus permits two-phase transfer clocking and optimum reception of photons during the integration periods between transfer clock pulses.

Janesick, James R.↗
NASA NTRS2004

Self regulating body bias generator

The back bias voltage on a functional circuit is controlled through a closed loop process. A delay element receives a clock pulse and produces a delay output. The delay element is advantageously constructed of the same materials as the functional circuit so that the aging and degradation of the delay element parallels the degradation of the functional circuit. As the delay element degrades, the transistor switching time increases, increasing the time delay of the delay output. An AND gate compares a clock pulse to an output pulse of the delay element, the AND output forming a control pulse. A duty cycle of the control pulse is determined by the delay time between the clock pulse and the delay element output. The control pulse is received at the input of a charge pump. The charge pump produces a back bias voltage which is then applied to the delay element and to the functional circuit. If the time delay produced by the delay element exceeds the optimal delay, the duty cycle of the control pulse is shortened, and the back bias voltage is lowered, thereby increasing the switching speed of the transistors in the delay element and reducing the time delay. If the throughput of the delay element is too fast, the duty cycle of the control pulse is lengthened, raising the back bias voltage produced by the charge pump. This, in turn, lowers the switching speed of the transistors in both the delay element and the functional circuit. The slower switching speed in the delay element increases time delay. In this manner, the switching speed of the delay element, and of the functional circuit, is maintained at a constant level over the life of the circuit.

Hass, Kenneth↗
NASA NTRS2009

Dynamic Self-Locking of an OEO Containing a VCSEL

A method of dynamic self-locking has been demonstrated to be effective as a means of stabilizing the wavelength of light emitted by a vertical-cavity surface-emitting laser (VCSEL) that is an active element in the frequency-control loop of an optoelectronic oscillator (OEO) designed to implement an atomic clock based on an electromagnetically- induced-transparency (EIT) resonance. This scheme can be considered an alternative to the one described in Optical Injection Locking of a VCSEL in an OEO (NPO-43454), NASA Tech Briefs, Vol. 33, No. 7 (July 2009), page 33. Both schemes are expected to enable the development of small, low-power, high-stability atomic clocks that would be suitable for use in applications involving precise navigation and/or communication. To recapitulate from the cited prior article: In one essential aspect of operation of an OEO of the type described above, a microwave modulation signal is coupled into the VCSEL. Heretofore, it has been well known that the wavelength of light emitted by a VCSEL depends on its temperature and drive current, necessitating thorough stabilization of these operational parameters. Recently, it was discovered that the wavelength also depends on the microwave power coupled into the VCSEL. This concludes the background information. From the perspective that led to the conception of the optical injection-locking scheme described in the cited prior article, the variation of the VCSEL wavelength with the microwave power circulating in the frequency-control loop is regarded as a disadvantage and optical injection locking is a solution of the problem of stabilizing the wavelength in the presence of uncontrolled fluctuations in the microwave power. The present scheme for dynamic self-locking emerges from a different perspective, in which the dependence of VCSEL wavelength on microwave power is regarded as an advantageous phenomenon that can be exploited as a means of controlling the wavelength. The figure schematically depicts an atomic-clock OEO of the type in question, wherein (1) the light from the VCSEL is used to excite an EIT resonance in selected atoms in a gas cell (e.g., 87Rb atoms in a low-pressure mixture of Ar and Ne) and (2) the power supplied to the VCSEL is modulated by a microwave signal that includes components at beat frequencies among the VCSEL wavelength and modulation sidebands. As the VCSEL wavelength changes, it moves closer to or farther from a nearby absorption spectral line, and the optical power transmitted through the cell (and thus the loop gain) changes accordingly. A change in the loop gain causes a change in the microwave power and, thus, in the VCSEL wavelength. It is possible to choose a set of design and operational parameters (most importantly, the electronic part of the loop gain) such that the OEO stabilizes itself in the sense that an increase in circulating microwave power causes the VCSEL wavelength to change in a direction that results in an increase in optical absorption and thus a decrease in circulating microwave power. Typically, such an appropriate choice of operational parameters involves setting the nominal VCSEL wavelength to a point on the shorter-wavelength wing of an absorption spectral line.

Strekalov, Dmitry↗
NASA NTRS2009

Hardware Implementation of a Bilateral Subtraction Filter

A bilateral subtraction filter has been implemented as a hardware module in the form of a field-programmable gate array (FPGA). In general, a bilateral subtraction filter is a key subsystem of a high-quality stereoscopic machine vision system that utilizes images that are large and/or dense. Bilateral subtraction filters have been implemented in software on general-purpose computers, but the processing speeds attainable in this way even on computers containing the fastest processors are insufficient for real-time applications. The present FPGA bilateral subtraction filter is intended to accelerate processing to real-time speed and to be a prototype of a link in a stereoscopic-machine- vision processing chain, now under development, that would process large and/or dense images in real time and would be implemented in an FPGA. In terms that are necessarily oversimplified for the sake of brevity, a bilateral subtraction filter is a smoothing, edge-preserving filter for suppressing low-frequency noise. The filter operation amounts to replacing the value for each pixel with a weighted average of the values of that pixel and the neighboring pixels in a predefined neighborhood or window (e.g., a 9 9 window). The filter weights depend partly on pixel values and partly on the window size. The present FPGA implementation of a bilateral subtraction filter utilizes a 9 9 window. This implementation was designed to take advantage of the ability to do many of the component computations in parallel pipelines to enable processing of image data at the rate at which they are generated. The filter can be considered to be divided into the following parts (see figure): a) An image pixel pipeline with a 9 9- pixel window generator, b) An array of processing elements; c) An adder tree; d) A smoothing-and-delaying unit; and e) A subtraction unit. After each 9 9 window is created, the affected pixel data are fed to the processing elements. Each processing element is fed the pixel value for its position in the window as well as the pixel value for the central pixel of the window. The absolute difference between these two pixel values is calculated and used as an address in a lookup table. Each processing element has a lookup table, unique for its position in the window, containing the weight coefficients for the Gaussian function for that position. The pixel value is multiplied by the weight, and the outputs of the processing element are the weight and pixel-value weight product. The products and weights are fed to the adder tree. The sum of the products and the sum of the weights are fed to the divider, which computes the sum of products the sum of weights. The output of the divider is denoted the bilateral smoothed image. The smoothing function is a simple weighted average computed over a 3 3 subwindow centered in the 9 9 window. After smoothing, the image is delayed by an additional amount of time needed to match the processing time for computing the bilateral smoothed image. The bilateral smoothed image is then subtracted from the 3 3 smoothed image to produce the final output. The prototype filter as implemented in a commercially available FPGA processes one pixel per clock cycle. Operation at a clock speed of 66 MHz has been demonstrated, and results of a static timing analysis have been interpreted as suggesting that the clock speed could be increased to as much as 100 MHz.

Huertas, Andres↗
NASA NTRS2011

Sensor web

A Sensor Web formed of a number of different sensor pods. Each of the sensor pods include a clock which is synchronized with a master clock so that all of the sensor pods in the Web have a synchronized clock. The synchronization is carried out by first using a coarse synchronization which takes less power, and subsequently carrying out a fine synchronization to make a fine sync of all the pods on the Web. After the synchronization, the pods ping their neighbors to determine which pods are listening and responded, and then only listen during time slots corresponding to those pods which respond.

Delin, Kevin A.↗
NASA NTRS2004

Scalable Multiprocessor for High-Speed Computing in Space

A report discusses the continuing development of a scalable multiprocessor computing system for hard real-time applications aboard a spacecraft. "Hard realtime applications" signifies applications, like real-time radar signal processing, in which the data to be processed are generated at "hundreds" of pulses per second, each pulse "requiring" millions of arithmetic operations. In these applications, the digital processors must be tightly integrated with analog instrumentation (e.g., radar equipment), and data input/output must be synchronized with analog instrumentation, controlled to within fractions of a microsecond. The scalable multiprocessor is a cluster of identical commercial-off-the-shelf generic DSP (digital-signal-processing) computers plus generic interface circuits, including analog-to-digital converters, all controlled by software. The processors are computers interconnected by high-speed serial links. Performance can be increased by adding hardware modules and correspondingly modifying the software. Work is distributed among the processors in a parallel or pipeline fashion by means of a flexible master/slave control and timing scheme. Each processor operates under its own local clock; synchronization is achieved by broadcasting master time signals to all the processors, which compute offsets between the master clock and their local clocks.

Lux, James↗
NASA NTRS2011

Molecular Mechanisms of Circadian Regulation During Spaceflight

Disruption of the regular environmental circadian cues in addition to stringent and demanding operational schedules are two main factors that undoubtedly impact sleep patterns and vigilant performance in the astronaut crews during spaceflight. Most research is focused on the behavioral aspects of the risk of circadian desynchronization, characterized by fatigue and health and performance decrement. A common countermeasure for circadian re-entrainment utilizes blue-green light to entrain the circadian clock and mitigate this risk. However, an effective countermeasure targeting the photoreceptor system requires that the basic circadian molecular machinery remains intact during spaceflight. The molecular clock consists of sets of proteins that perform different functions within the clock machinery: circadian oscillators (genes whose expression levels cycle during the day, keep the pass of cellular time and regulate downstream effector genes), the effector or output genes (those which impact the physiology of the tissue or organism), and the input genes (responsible for sensing the environmental cues that allow circadian entrainment). The main environmental cue is light. As opposed to the known photoreceptors (rods and cones), the non-visual light stimulus is received by a subset of the population of retinal ganglion cells called intrinsically photosensitive retinal ganglion cells (ipRGC) that express melanopsin (opsin 4 -Opn4-) as the photoreceptor. We hypothesize that spaceflight may affect ipRGC and melanopsin expression, which may be a contributing cause of circadian disruption during spaceflight. To answer this question, eyes from albino Balb/cJ mice aboard STS-133 were collected for histological analysis and gene expression profiling of the retina at 1 and 7 days after landing. Both vivarium and AEM (animal enclosure module) mice were used as ground controls. Opn4 expression was analyzed by real time RT/qPCR and retinal sections were stained for Opn4 immunofluorescence. Opn4 was decreased (abrogated in one case) in retinas that concurrently showed higher evidence of oxidative stress. We propose that oxidative stress can lead to a decrease in melanopsin expression, likely via ipRGC loss or impairment, and thus, it can be a contributing factor to circadian disruption during spaceflight. Countermeasures contemplating the use of light should therefore be complemented with melanopsin expression maintenance and/or reduction in oxidative stress.

Zanello, Susana↗
NASA NTRS2011

A Self-Stabilizing Synchronization Protocol for Arbitrary Digraphs

This paper presents a self-stabilizing distributed clock synchronization protocol in the absence of faults in the system. It is focused on the distributed clock synchronization of an arbitrary, non-partitioned digraph ranging from fully connected to 1-connected networks of nodes while allowing for differences in the network elements. This protocol does not rely on assumptions about the initial state of the system, other than the presence of at least one node, and no central clock or a centrally generated signal, pulse, or message is used. Nodes are anonymous, i.e., they do not have unique identities. There is no theoretical limit on the maximum number of participating nodes. The only constraint on the behavior of the node is that the interactions with other nodes are restricted to defined links and interfaces. This protocol deterministically converges within a time bound that is a linear function of the self-stabilization period. We present an outline of a deductive proof of the correctness of the protocol. A bounded model of the protocol was mechanically verified for a variety of topologies. Results of the mechanical proof of the correctness of the protocol are provided. The model checking results have verified the correctness of the protocol as they apply to the networks with unidirectional and bidirectional links. In addition, the results confirm the claims of determinism and linear convergence. As a result, we conjecture that the protocol solves the general case of this problem. We also present several variations of the protocol and discuss that this synchronization protocol is indeed an emergent system.

Malekpour, Mahyar R.↗
NASA NTRS2011

Jitter Controller Software

Sinusoidal jitter is produced by simply modulating a clock frequency sinusoidally with a given frequency and amplitude. But this can be expressed as phase jitter, frequency jitter, or cycle-to-cycle jitter, rms or peak, absolute units, or normalized to the base clock frequency. Jitter using other waveforms requires calculating and downloading these waveforms to an arbitrary waveform generator, and helping the user manage relationships among phase jitter crest factor, frequency jitter crest factor, and cycle-to-cycle jitter (CCJ) crest factor. Software was developed for managing these relationships, automatically configuring the generator, and saving test results documentation. Tighter management of clock jitter and jitter sensitivity is required by new codes that further extend the already high performance of space communication links, completely correcting symbol error rates higher than 10 percent, and therefore typically requiring demodulation and symbol synchronization hardware to operating at signal-to-noise ratios of less than one. To accomplish this, greater demands are also made on transmitter performance, and measurement techniques are needed to confirm performance. It was discovered early that sinusoidal jitter can be stepped on a grid such that one can connect points by constant phase jitter, constant frequency jitter, or constant cycle-cycle jitter. The tool automates adherence to a grid while also allowing adjustments off-grid. Also, the jitter can be set by the user on any dimension and the others are calculated. The calculations are all recorded, allowing the data to be rapidly plotted or re-plotted against different interpretations just by changing pointers to columns. A key advantage is taking data on a carefully controlled grid, which allowed a single data set to be post-analyzed many different ways. Another innovation was building a software tool to provide very tight coupling between the generator and the recorded data product, and the operator's worksheet. Together, these allowed the operator to sweep the jitter stimulus quickly along any of three dimensions and focus on the response of the system under test (response was jitter transfer ratio, or performance degradation to the symbol or codeword error rate). Additionally, managing multi-tone and noise waveforms automated a tedious manual process, and provided almost instantaneous decision- making control over test flow. The code was written in LabVIEW, and calls Agilent instrument drivers to write to the generator hardware.

Lansdowne, Chatwin↗
NASA NTRS2012

Development of Thermal Infrared Sensor to Supplement Operational Land Imager

The thermal infrared sensor (TIRS) is a quantum well infrared photodetector (QWIP)-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 m. The focal plane will contain three 640 ~512 QWIP arrays mounted onto a silicon substrate. The readout integrated circuit (ROIC) addresses each pixel on the QWIP arrays and reads out the pixel value (signal). The ROIC is controlled by the focal plane electronics (FPE) by means of clock signals and bias voltage value. The means of how the FPE is designed to control and interact with the TIRS focal plane assembly (FPA) is the basis for this work. The technology developed under the FPE is for the TIRS focal plane assembly (FPA). The FPE must interact with the FPA to command and control the FPA, extract analog signals from the FPA, and then convert the analog signals to digital format and send them via a serial link (USB) to a computer. The FPE accomplishes the described functions by converting electrical power from generic power supplies to the required bias power that is needed by the FPA. The FPE also generates digital clocking signals and shifts the typical transistor-to-transistor logic (TTL) to }5 V required by the FPA. The FPE also uses an application- specific integrated circuit (ASIC) named System Image, Digitizing, Enhancing, Controlling, And Retrieving (SIDECAR) from Teledyne Corp. to generate the clocking patterns commanded by the user. The uniqueness of the FPE for TIRS lies in that the TIRS FPA has three QWIP detector arrays, and all three detector arrays must be in synchronization while in operation. This is to avoid data skewing while observing Earth flying in space. The observing scenario may be customized by uploading new control software to the SIDECAR.

Shu, Peter↗
NASA NTRS2012

Radiation-Hard SpaceWire/Gigabit Ethernet-Compatible Transponder

A radiation-hard transponder was developed utilizing submicron/nanotechnology from IBM. The device consumes low power and has a low fabrication cost. This device utilizes a Plug-and-Play concept, and can be integrated into intra-satellite networks, supporting SpaceWire and Gigabit Ethernet I/O. A space-qualified, 100-pin package also was developed, allowing space-qualified (class K) transponders to be delivered within a six-month time frame. The novel, optical, radiation-tolerant transponder was implemented as a standalone board, containing the transponder ASIC (application specific integrated circuit) and optical module, with an FPGA (field-programmable gate array) friendly parallel interface. It features improved radiation tolerance; high-data-rate, low-power consumption; and advanced functionality. The transponder utilizes a patented current mode logic library of radiation-hardened-by-architecture cells. The transponder was developed, fabricated, and radhard tested up to 1 MRad. It was fabricated using 90-nm CMOS (complementary metal oxide semiconductor) 9 SF process from IBM, and incorporates full BIT circuitry, allowing a loop back test. The low-speed parallel LVCMOS (lowvoltage complementary metal oxide semiconductor) bus is compatible with Actel FPGA. The output LVDS (low-voltage differential signaling) interface operates up to 1.5 Gb/s. Built-in CDR (clock-data recovery) circuitry provides robust synchronization and incorporates two alarm signals such as synch loss and signal loss. The ultra-linear peak detector scheme allows on-line control of the amplitude of the input signal. Power consumption is less than 300 mW. The developed transponder with a 1.25 Gb/s serial data rate incorporates a 10-to-1 serializer with an internal clock multiplication unit and a 10-1 deserializer with internal clock and data recovery block, which can operate with 8B10B encoded signals. Three loop-back test modes are provided to facilitate the built-in-test functionality. The design is based on a proprietary library of differential current switching logic cells implemented in the standard 90-nm CMOS 9SF technology from IBM. The proprietary low-power LVDS physical interface is fully compatible with the SpaceWire standard, and can be directly connected to the SFP MSA (small form factor pluggable Multiple Source Agreement) optical transponder. The low-speed parallel interfaces are fully compatible with the standard 1.8 V CMOS input/output devices. The utilized proprietary annular CMOS layout structures provide TID tolerance above 1.2 MRad. The complete chip consumes less than 150 mW of power from a single 1.8-V positive supply source.

Katzman, Vladimir↗
NASA NTRS2012

Moon-to-Earth: Eavesdropping on the GRAIL Inter-Spacecraft Time-Transfer Link Using a Large Antenna and a Software Receiver

NASA's twin GRAIL [1] spacecraft (Ebb and Flow) arrived at Earth's Moon on New Year's Day, 2012. GRAIL's primary mission is to create a high-resolution map of the Moon's gravitational field by measuring very precisely the change in distance between the two spacecraft [2]. Each spacecraft transmits two signals to the other spacecraft, a PRN code modulated on a 2 GHz carrier (S-band), as well as an unmodulated carrier at roughly 33 GHz (Ka-band). Since it's not feasible to synchronize the two GRAIL spacecraft's clocks via GPS (as was done with GRACE), the S-band signals are used as a time-transfer link to synchronize either Ebb's clock to Flow or vice versa. As an independent measure to determine the clock offset of the GRAIL ultra-stable oscillators to UTC(NIST), an experiment was conducted where our JPL team used a large antenna on Earth to eavesdrop on the inter-spacecraft time-transfer link.

time-transfer subsystem (TTS)↗
NASA NTRS2016

New Approaches for Direct Current (DC) Balanced SpaceWire

Direct Current (DC) line balanced SpaceWire is attractive for a number of reasons. Firstly, a DC line balanced interface provides the ability to isolate the physical layer with either a transformer or capacitor to achieve higher common mode voltage rejection and or the complete galvanic isolation in the case of a transformer. And secondly, it provides the possibility to reduce the number of conductors and transceivers in the classical SpaceWire interface by half by eliminating the Strobe line. Depending on the modulator scheme the clock data recovery frequency requirements may be only twice that of the transmit clock, or even match the transmit clock: depending on the Field Programmable Gate Array (FPGA) decoder design. In this paper, several different implementation scenarios will be discussed. Two of these scenarios are backward compatible with the existing SpaceWire hardware standards except for changes at the character level. Three other scenarios, while decreasing by half the standard SpaceWire hardware components, will require changes at both the character and signal levels and work with fixed rates. Other scenarios with variable data rates will require an additional SpaceWire interface handshake initialization sequence.

Line encoding↗
NASA NTRS2016

New Approaches for DC Balanced SpaceWire

Direct Current (DC) line balanced SpaceWire is attractive for a number of reasons. Firstly, a DC line balanced interface provides the ability to isolate the physical layer with either a transformer or capacitor to achieve higher common mode voltage rejection and/or the complete galvanic isolation in the case of a transformer. Secondly, it provides the possibility to reduce the number of conductors and transceivers in the classical SpaceWire interface by half by eliminating the Strobe line. Depending on the modulator scheme - the clock data recovery frequency requirements may be only twice that of the transmit clock, or even match the transmit clock: depending on the Field Programmable Gate Array (FPGA) decoder design. In this paper, several different implementation scenarios will be discussed. Two of these scenarios are backward compatible with the existing SpaceWire hardware standards except for changes at the character level. Three other scenarios, while decreasing by half the standard SpaceWire hardware components, will require changes at both the character and signal levels and work with fixed rates. Other scenarios with variable data rates will require an additional SpaceWire interface handshake initialization sequence.

SpaceWire↗