Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “NaS”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 721 records · Page 40

Smallest Nanoelectronic with Atomic Devices with Precise Structures

Since its invention in 1948, the transistor has revolutionized our everyday life - transistor radios and TV's appeared in the early 1960s, personal computers came into widespread use in the mid-1980s, and cellular phones, laptops, and palm-sized organizers dominated the 1990s. The electronics revolution is based upon transistor miniaturization; smaller transistors are faster, and denser circuitry has more functionality. Transistors in current generation chips are 0.25 micron or 250 nanometers in size, and the electronics industry has completed development of 0.18 micron transistors which will enter production within the next few years. Industry researchers are now working to reduce transistor size down to 0.13 micron - a thousandth of the width of a human hair. However, studies indicate that the miniaturization of silicon transistors will soon reach its limit. For further progress in microelectronics, scientists have turned to nanotechnology to advance the science. Rather than continuing to miniaturize transistors to a point where they become unreliable, nanotechnology offers the new approach of building devices on the atomic scale [see sidebar]. One vision for the next generation of miniature electronics is atomic chain electronics, where devices are composed of atoms aligned on top of a substrate surface in a regular pattern. The Atomic Chain Electronics Project (ACEP) - part of the Semiconductor Device Modeling and Nanotechnology group, Integrated Product Team at the NAS Facility has been developing the theory of understanding atomic chain devices, and the author's patent for atomic chain electronics is now pending.

Yamada, Toshishige↗

Automatic Data Traffic Control on DSM Architecture

We study data traffic on distributed shared memory machines and conclude that data placement and grouping improve performance of scientific codes. We present several methods which user can employ to improve data traffic in his code. We report on implementation of a tool which detects the code fragments causing data congestions and advises user on improvements of data routing in these fragments. The capabilities of the tool include deduction of data alignment and affinity from the source code; detection of the code constructs having abnormally high cache or TLB misses; generation of data placement constructs. We demonstrate the capabilities of the tool on experiments with NAS parallel benchmarks and with a simple computational fluid dynamics application ARC3D.

Frumkin, Michael↗

Automatic Generation of OpenMP Directives and Its Application to Computational Fluid Dynamics Codes

The shared-memory programming model is a very effective way to achieve parallelism on shared memory parallel computers. As great progress was made in hardware and software technologies, performance of parallel programs with compiler directives has demonstrated large improvement. The introduction of OpenMP directives, the industrial standard for shared-memory programming, has minimized the issue of portability. In this study, we have extended CAPTools, a computer-aided parallelization toolkit, to automatically generate OpenMP-based parallel programs with nominal user assistance. We outline techniques used in the implementation of the tool and discuss the application of this tool on the NAS Parallel Benchmarks and several computational fluid dynamics codes. This work demonstrates the great potential of using the tool to quickly port parallel programs and also achieve good performance that exceeds some of the commercial tools.

Yan, Jerry↗

A Debugger for Computational Grid Applications

This viewgraph presentation gives an overview of a debugger for computational grid applications. Details are given on NAS parallel tools groups (including parallelization support tools, evaluation of various parallelization strategies, and distributed and aggregated computing), debugger dependencies, scalability, initial implementation, the process grid, and information on Globus.

Hood, Robert↗

The Automatic Parallelisation of Scientific Application Codes Using a Computer Aided Parallelisation Toolkit

The shared-memory programming model is a very effective way to achieve parallelism on shared memory parallel computers. Historically, the lack of a programming standard for using directives and the rather limited performance due to scalability have affected the take-up of this programming model approach. Significant progress has been made in hardware and software technologies, as a result the performance of parallel programs with compiler directives has also made improvements. The introduction of an industrial standard for shared-memory programming with directives, OpenMP, has also addressed the issue of portability. In this study, we have extended the computer aided parallelization toolkit (developed at the University of Greenwich), to automatically generate OpenMP based parallel programs with nominal user assistance. We outline the way in which loop types are categorized and how efficient OpenMP directives can be defined and placed using the in-depth interprocedural analysis that is carried out by the toolkit. We also discuss the application of the toolkit on the NAS Parallel Benchmarks and a number of real-world application codes. This work not only demonstrates the great potential of using the toolkit to quickly parallelize serial programs but also the good performance achievable on up to 300 processors for hybrid message passing and directive-based parallelizations.

Ierotheou, C.↗

Automation of Data Traffic Control on DSM Architecture

The design of distributed shared memory (DSM) computers liberates users from the duty to distribute data across processors and allows for the incremental development of parallel programs using, for example, OpenMP or Java threads. DSM architecture greatly simplifies the development of parallel programs having good performance on a few processors. However, to achieve a good program scalability on DSM computers requires that the user understand data flow in the application and use various techniques to avoid data traffic congestions. In this paper we discuss a number of such techniques, including data blocking, data placement, data transposition and page size control and evaluate their efficiency on the NAS (NASA Advanced Supercomputing) Parallel Benchmarks. We also present a tool which automates the detection of constructs causing data congestions in Fortran array oriented codes and advises the user on code transformations for improving data traffic in the application.

Frumkin, Michael↗

Automated Instrumentation and Monitoring of Data Movement for Parallel Programs

Writing efficient parallel programs is complicated by the need to select the right data structure alignments and distributions, which determine the nature and volume of inter-processor communications. A large number of performance tools for parallel programs have been developed recently to expose these inter-processor communications. However, none of them support performance views or provide statistics in terms of inter-processor data structure interactions. A performance tool that tracks the interaction between individual data structures and the context of these interactions is essential for understanding the performance of both explicit message passing programs and data-parallel languages such as HPF. In this paper we discuss the use of compiler front end tools for automatically tracking data structure movements in message passing programs, and low-overhead monitoring and postprocessing of such codes. We demonstrate that robust instrumentation and low overhead monitoring of inter-processor data structure movements is possible, with the use of a number of NAS benchmark codes, run on the i860 hypercube. We also show that the data so collected can be used effectively by post processing tools that expose performance bottlenecks using graphical displays and performance statistics.

Sarukkai, Sekhar↗

High Performance Programming Using Explicit Shared Memory Model on Cray T3D1

The Cray T3D system is the first-phase system in Cray Research, Inc.'s (CRI) three-phase massively parallel processing (MPP) program. This system features a heterogeneous architecture that closely couples DEC's Alpha microprocessors and CRI's parallel-vector technology, i.e., the Cray Y-MP and Cray C90. An overview of the Cray T3D hardware and available programming models is presented. Under Cray Research adaptive Fortran (CRAFT) model four programming methods (data parallel, work sharing, message-passing using PVM, and explicit shared memory model) are available to the users. However, at this time data parallel and work sharing programming models are not available to the user community. The differences between standard PVM and CRI's PVM are highlighted with performance measurements such as latencies and communication bandwidths. We have found that the performance of neither standard PVM nor CRI s PVM exploits the hardware capabilities of the T3D. The reasons for the bad performance of PVM as a native message-passing library are presented. This is illustrated by the performance of NAS Parallel Benchmarks (NPB) programmed in explicit shared memory model on Cray T3D. In general, the performance of standard PVM is about 4 to 5 times less than obtained by using explicit shared memory model. This degradation in performance is also seen on CM-5 where the performance of applications using native message-passing library CMMD on CM-5 is also about 4 to 5 times less than using data parallel methods. The issues involved (such as barriers, synchronization, invalidating data cache, aligning data cache etc.) while programming in explicit shared memory model are discussed. Comparative performance of NPB using explicit shared memory programming model on the Cray T3D and other highly parallel systems such as the TMC CM-5, Intel Paragon, Cray C90, IBM-SP1, etc. is presented.

Simon, Horst D.↗

Performance Metrics for Monitoring Parallel Program Executions

Existing tools for debugging performance of parallel programs either provide graphical representations of program execution or profiles of program executions. However, for performance debugging tools to be useful, such information has to be augmented with information that highlights the cause of poor program performance. Identifying the cause of poor performance necessitates the need for not only determining the significance of various performance problems on the execution time of the program, but also needs to consider the effect of interprocessor communications of individual source level data structures. In this paper, we present a suite of normalized indices which provide a convenient mechanism for focusing on a region of code with poor performance and highlights the cause of the problem in terms of processors, procedures and data structure interactions. All the indices are generated from trace files augmented with data structure information.. Further, we show with the help of examples from the NAS benchmark suite that the indices help in detecting potential cause of poor performance, based on augmented execution traces obtained by monitoring the program.

Sarukkai, Sekkar R.↗

Survey of Volumetric Grid Generators

This document is the result of an Internet Survey of Volumetric grid generators. As such we have included information from only the responses which were sent to us. After the initial publication and posting of this survey, we would encourage authors and users of grid generators to send further information. Here is the initial query posted to SIGGRID@nas and the USENET group sci.physics.computational.fluid-dynamics. Date: Sun, 30 Jan 94 11:37:52 -0800 From: woo (Alex Woo x6010 227-6 rm 315) Subject: Info Sought for Survey of Grid Generators I am collecting information and reviews of both government sponsored and commercial mesh generators for large scientific calculations, both block structured and unstructured. If you send me a review of a mesh generator, please indicate its availability and cost. If you are a commercial concern with information on a product, please also include references for possible reviewers. Please email to woo@ra-next.arc.nasa.gov. I will post a summary and probably write a short note for the IEEE Antennas and Propagation Magazine. Alex Woo, MS 227-6 woo@ames.arc.nasa.gov NASA Ames Research Center NASAMAIL ACWOO Moffett Field, CA 94035-1000 SPANET 24582::W00 (415) 604-6010 (FAX) 604-4357 fhplabs,decwrl,uunet)!ames!woo Disclaimer: These are not official statements of NASA or EMCC. We did not include all the submitted text here. Instead we have created a database entry in the freely available and widely used BIBTeX format which has an Uniform Resource Locator (URL) field pointing to more details. The BIBTeX database is modeled after those available from the BIBNET project at University of Utah.

Woo, Alex↗

High Performance Programming Using Explicit Shared Memory Model on the Cray T3D

The Cray T3D is the first-phase system in Cray Research Inc.'s (CRI) three-phase massively parallel processing program. In this report we describe the architecture of the T3D, as well as the CRAFT (Cray Research Adaptive Fortran) programming model, and contrast it with PVM, which is also supported on the T3D We present some performance data based on the NAS Parallel Benchmarks to illustrate both architectural and software features of the T3D.

Saini, Subhash↗

A Parallel Multigrid Solver for Viscous Flows on Anisotropic Structured Grids

This paper presents an efficient parallel multigrid solver for speeding up the computation of a 3-D model that treats the flow of a viscous fluid over a flat plate. The main interest of this simulation lies in exhibiting some basic difficulties that prevent optimal multigrid efficiencies from being achieved. As the computing platform, we have used Coral, a Beowulf-class system based on Intel Pentium processors and equipped with GigaNet cLAN and switched Fast Ethernet networks. Our study not only examines the scalability of the solver but also includes a performance evaluation of Coral where the investigated solver has been used to compare several of its design choices, namely, the interconnection network (GigaNet versus switched Fast-Ethernet) and the node configuration (dual nodes versus single nodes). As a reference, the performance results have been compared with those obtained with the NAS-MG benchmark.

Prieto, Manuel↗

Reducing Backups by Utilizing DMF

Although a filesystem may be migratable, for a period of time the data blocks are on disk only. When performing system dumps, these data blocks are backed up to tape. If the data blocks are offline or dual resident, then only the inode is backed up. If all online files are made dual resident prior to performing system dumps, the dump time and the amount of resources required can be significantly reduced. The High Speed Processors group at the Numerical Aerodynamics Simulation (NAS) Facility at NASA Ames Research Center developed a tool to make all online files dual resident. The result is that a file whose data blocks are on DMF tape and still assigned to the original inode. Our 150GB filesystem used to take 8 to 12 hours to backup and used 50 to 60 tapes. Now the backup is typically under 10 tapes and completes in under 2 hours. This paper discusses this new tool and advantages gained by using it.

Cardo, Nicholas P.↗

Performance Evaluation of Three Distributed Computing Environments for Scientific Applications

We present performance results for three distributed computing environments using the three simulated CFD applications in the NAS Parallel Benchmark suite. These environments are the DCF cluster, the LACE cluster, and an Intel iPSC/860 machine. The DCF is a prototypic cluster of loosely coupled SGI R3000 machines connected by Ethernet. The LACE cluster is a tightly coupled cluster of 32 IBM RS6000/560 machines connected by Ethernet as well as by either FDDI or an IBM Allnode switch. Results of several parallel algorithms for the three simulated applications are presented and analyzed based on the interplay between the communication requirements of an algorithm and the characteristics of the communication network of a distributed system.

Fatoohi, Rod↗

Backing up DMF Databases

A complete backup of the Cray Data Migration Facility (DMF) databases should include the data migration databases, all media specific process' (MSP's) databases, and the journal file. The backup should be able to accomplished without impacting users or stopping DMF. The High Speed Processors group at the Numerical Aerodynamics Simulation (NAS) Facility at NASA Ames Research Center undertook the task of finding an effective and efficient way to backup all DMF databases. This has been accomplished by taking advantage of new features introduced in DMF 2.0 and adding a minor modification to the dmdaemon. This paper discusses the investigation and the changes necessary to implement these enhancements.

Cardo, Nicholas P.↗

Batch Scheduling a Fresh Approach

The Network Queueing System (NQS) was designed to schedule jobs based on limits within queues. As systems obtain more memory, the number of queues increased to take advantage of the added memory resource. The problem now becomes too many queues. Having a large number of queues provides users with the capability to gain an unfair advantage over other users by tailoring their job to fit in an empty queue. Additionally, the large number of queues becomes confusing to the user community. The High Speed Processors group at the Numerical Aerodynamics Simulation (NAS) Facility at NASA Ames Research Center developed a new approach to batch job scheduling. This new method reduces the number of queues required by eliminating the need for queues based on resource limits. The scheduler examines each request for necessary resources before initiating the job. Also additional user limits at the complex level were added to provide a fairness to all users. Additional tools which include user job reordering are under development to work with the new scheduler. This paper discusses the objectives, design and implementation results of this new scheduler

Cardo, Nicholas P.↗

Beyond a Terabyte File System

The Numerical Aerodynamics Simulation Facility's (NAS) CRAY C916/1024 accesses a "virtual" on-line file system, which is expanding beyond a terabyte of information. This paper will present some options to fine tuning Data Migration Facility (DMF) to stretch the online disk capacity and explore the transitions to newer devices (STK 4490, ER90, RAID).

Powers, Alan K.↗

Scalability and Portability of Two Parallel Implementations of ADI

Two domain decompositions for the implementation of the NAS Scalar Penta-diagonal Parallel Benchmark on MIMD systems are investigated, namely transposition and multi-partitioning. Hardware platforms considered are the Intel iPSC/860 and Paragon XP/S-15, and clusters of SGI workstations on ethernet, communicating through PVM. It is found that the multi-partitioning strategy offers the kind of coarse granularity that allows scaling up to hundreds of processors on a massively parallel machine. Moreover, efficiency is retained when the code is ported verbatim (save message passing syntax) to a PVM environment on a modest size cluster of workstations.

Phung, Thanh↗