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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 721 records · Page 40
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Fault injection experiments using FIAT

The results of several experiments conducted using the fault-injection-based automated testing (FIAT) system are presented. FIAT is capable of emulating a variety of distributed system architectures, and it provides the capabilities to monitor system behavior and inject faults for the purpose of experimental characterization and validation of a system's dependability. The experiments consist of exhaustively injecting three separate fault types into various locations, encompassing both the code and data portions of memory images, of two distinct applications executed with several different data values and sizes. Fault types are variations of memory bit faults. The results show that there are a limited number of system-level fault manifestations. These manifestations follow a normal distribution for each fault type. Error detection latencies are found to be normally distributed. The methodology can be used to predict the system-level fault responses during the system design stage.

Barton, James H.↗
NASA NTRS1990

PCLIPS

CLIPS is an expert system, created specifically to allow rapid implementation of an expert system. CLIPS is written in C, and thus needs a very small amount of memory to run. Parallel CLIPS (PCLIPS) is an extension to CLIPS which is intended to be used in situations where a group of expert systems are expected to run simultaneously and occasionally communicate with each other on an integrated network. PCLIPS is a coarse-grained data distribution system. Its main goal is to take information in one knowledge base and distribute it to other knowledge bases so that all the executing expert systems are able to use that knowledge to solve their disparate problems.

Krolak, Patrick D.↗
NASA NTRS1994

Confessions of a robot lobotomist

Since its inception, numerically controlled (NC) machining methods have been used throughout the aerospace industry to mill, drill, and turn complex shapes by sequentially stepping through motion programs. However, the recent demand for more precision, faster feeds, exotic sensors, and branching execution have existing computer numerical control (CNC) and distributed numerical control (DNC) systems running at maximum controller capacity. Typical disadvantages of current CNC's include fixed memory capacities, limited communication ports, and the use of multiple control languages. The need to tailor CNC's to meet specific applications, whether it be expanded memory, additional communications, or integrated vision, often requires replacing the original controller supplied with the commercial machine tool with a more powerful and capable system. This paper briefly describes the process and equipment requirements for new controllers and their evolutionary implementation in an aerospace environment. The process of controller retrofit with currently available machines is examined, along with several case studies and their computational and architectural implications.

Gottshall, R. Marc↗
NASA NTRS1987

A neurocomputer based on an analog-digital hybrid architecture

A novel analog-digital hybrid architecture based on the utilization of high density digital random access memories for the storage of the synaptic weights of a neural network, and high speed analog hardware to perform neural computation is described. An electronic neurocomputer based on such an architecture is ideally suited for investigating the dynamics, associative recall properties, and computational capabilities of neural networks and provides significant speed improvement in comparison to conventional software based neural network simulations. As a demonstration of the feasibility of the hybrid architectural concept, a prototype breadboard hybrid neurocomputer system with 32 neurons has been designed and fabricated with off-the-shelf hardware components. The performance of the breadboard system has been tested for variety of applications including associative memory and combinatorial problem solving such as Graph Coloring, and is discussed in this paper.

Moopenn, A.↗
NASA NTRS2015

Self-Repairing Fatigue Damage in Metallic Structures for Aerospace Vehicles Using Shape Memory Alloy Self-healing (SMASH) Technology

This DAA is for the Phase II webinar presentation of the ARMD-funded SMASH technology. A self-repairing aluminum-based composite system has been developed using liquid-assisted healing theory in conjunction with the shape memory effect of wire reinforcements. The metal matrix composite was thermodynamically designed to have a matrix with a relatively even dispersion of low-melting phase, allowing for repair of cracks at a pre-determined temperature. Shape memory alloy wire reinforcements were used within the composite to provide crack closure. Investigators focused the research on fatigue cracks propagating through the matrix in order to optimize and computer model the SMASH technology for aeronautical applications.

fatigue↗
NASA NTRS1985

The system of EAS time analysis

The extensive air showers' (EAS) front shape, angle of incidence, disk thickness, particle distribution along the shower, on the delayed and EAS front advancing particles were determined. The suggested system of the EAS time analysis allows determination of the whole EAS longitudinal structure at the observation points. The information from the detectors is continuously recorded in the memory with the memory cell switching in 5 ns, this enables fixation of the moment of pulse input from the detector with an accuracy to + or - 2.5 ns. Along with the fast memory, a slow memory with the cell switching in 1 micron s is introduced in the system, this permits observation of relatively large time intervals with respect to the trigger pulse with an appropriately lower accuracy.

Khalafyan, A. Z.↗
NASA NTRS2002

Compositionally-Graded Shape Memory Film for Self-Deployment of Membrane Reflectors and Optics

The next generation of space systems will require large apertures in order to image faint targets or cover large areas of Earth. These large apertures must be able to fit inside a launch vehicle fairing, be light enough for launch into orbit, and deploy on orbit with repeatability and reliability. The current state-of-the-art in flight optics is represented by the 4 meter LAMP telescope, with an areal density of 10 km sq m. Development of a Beryllium mirror demonstration article for NGST (Next Generation Space Telescope) at the University of Arizona indicate areal densities of 0.5 kg sq m with flight hardware in the 12 meter range. With progressive improvements in existing deployment, packaging, and structural technologies, the size of optics and reflectors will continue to increase, while mass is reduced. However, without a breakthrough in materials, packaging and/or deployment technologies, the goal for Gossamer structures of 0.1 kg sq m is unachievable for the near and mid-term NASA missions. Membrane technology provides the best hope of achieving such low areal densities. In combination with advances in membrane materials and structures, development of revolutionary techniques for deployment systems can provide significant improvements in large aperture technology. In this paper, the results of a six-month Phase I research effort to demonstrate the application of thin film NiTi to aerospace-qualified membrane and mesh materials are presented. Deposition of shape memory thin film was achieved Astromesh (trademark) metal mesh and CP-1, and optical-quality polymer membrane. Not only was full-coating deposition demonstrated, but also small segment deposition which holds potential for local surface control. Deployment of these materials was also demonstrated, setting the stage for the development of a larger test article.

Hill, Lisa↗
NASA NTRS1989

Merlin - Massively parallel heterogeneous computing

Hardware and software for Merlin, a new kind of massively parallel computing system, are described. Eight computers are linked as a 300-MIPS prototype to develop system software for a larger Merlin network with 16 to 64 nodes, totaling 600 to 3000 MIPS. These working prototypes help refine a mapped reflective memory technique that offers a new, very general way of linking many types of computer to form supercomputers. Processors share data selectively and rapidly on a word-by-word basis. Fast firmware virtual circuits are reconfigured to match topological needs of individual application programs. Merlin's low-latency memory-sharing interfaces solve many problems in the design of high-performance computing systems. The Merlin prototypes are intended to run parallel programs for scientific applications and to determine hardware and software needs for a future Teraflops Merlin network.

Wittie, Larry↗
NASA NTRS1972

LSI computer fabrication - SUMC/DV.

The SUMC/DV (Space Ultrareliable Modular Computer Demonstration Vehicle), which required the design and fabrication of ten different array types, was designed, partitioned, assembled, tested, and made completely operational in less than one year. This paper describes the assembly, the physical and electrical characteristics, and the basic electrical testing procedures used on SUMC/DV. The paper includes a description of the packaging concepts, the physical assembly, the fabrication and testing of the various components including the LSI/CMOS arrays, the hierarchy of the memory complement, the clock generation and distribution scheme, additional system testing techniques, and the procedure employed in the electrical checkout of the system.

Feller, A.↗
NASA NTRS1975

Man-rated flight software for the F-8 DFBW program

The design, implementation, and verification of the flight control software used in the F-8 DFBW program are discussed. Since the DFBW utilizes an Apollo computer and hardware, the procedures, controls, and basic management techniques employed are based on those developed for the Apollo software system. Program Assembly Control, simulator configuration control, erasable-memory load generation, change procedures and anomaly reporting are discussed. The primary verification tools--the all-digital simulator, the hybrid simulator, and the Iron Bird simulator--are described, as well as the program test plans and their implementation on the various simulators. Failure-effects analysis and the creation of special failure-generating software for testing purposes are described. The quality of the end product is evidenced by the F-8 DFBW flight test program in which 42 flights, totaling 58 hours of flight time, were successfully made without any DFCS inflight software, or hardware, failures.

Bairnsfather, R. R.↗
NASA NTRS1975

Prepared to launch

The verification of the interface between the preflight prepare-to-launch and flight program, targeting load, and flight program initialization was described. This is done using the digital command system coupled with a flight program patch and a memory dump command, the 6D/LVDC simulator, and a program trace through phase 1 initialization.

Source record↗
NASA NTRS1976

Man-rated flight software for the F-8 DFBW program

The design, implementation, and verification of the flight control software used in the F-8 DFBW program are discussed. Since the DFBW utilizes an Apollo computer and hardware, the procedures, controls, and basic management techniques employed are based on those developed for the Apollo software system. Program assembly control, simulator configuration control, erasable-memory load generation, change procedures and anomaly reporting are discussed. The primary verification tools are described, as well as the program test plans and their implementation on the various simulators. Failure effects analysis and the creation of special failure generating software for testing purposes are described.

Bairnsfather, R. R.↗
NASA NTRS1975

Command and data handling of science signals on Spacelab

The Orbiter Avionics and the Spacelab Command and Data Management System (CDMS) combine to provide a relatively complete command, control, and data handling service to the instrument complement during a Shuttle Sortie Mission. The Spacelab CDMS services the instruments and the Orbiter in turn services the Spacelab. The CDMS computer system includes three computers, two I/O units, a mass memory, and a variable number of remote acquisition units. Attention is given to the CDMS high rate multiplexer, CDMS tape recorders, closed circuit television for the visual monitoring of payload bay and cabin area activities, methods of science data acquisition, questions of transmission and recording, CDMS experiment computer usage, and experiment electronics.

Mccain, H. G.↗
NASA NTRS1978

A cycle timer for testing electric vehicles

The paper presents a cycle timer which enables the accurate following and repetition of SAE driving schedules of stop and go cycles, for electric vehicles, by reducing the human factor. The system which consists of a programmable read-only memory (PROM) stores each of these cycles, which are detailed, on its own plug-in card. The actual vehicle speed, and the PROM indicated desired speed are displayed on a dual scale meter allowing the driver to match them. A speed change is preceded by a half second buzzer warning and a new cycle by a one second warning. The PROM controls the recycle start time as well as the buzzer activation. A 5 volt regulator providing logic power, and a 12 volt dc-dc converter providing analog and memory power are described.

Soltis, R. F.↗
NASA NTRS1981

SAR processing on the MPP

The processing of synthetic aperture radar (SAR) signals using the massively parallel processor (MPP) is discussed. The fast Fourier transform convolution procedures employed in the algorithms are described. The MPP architecture comprises an array unit (ARU) which processes arrays of data; an array control unit which controls the operation of the ARU and performs scalar arithmetic; a program and data management unit which controls the flow of data; and a unique staging memory (SM) which buffers and permutes data. The ARU contains a 128 by 128 array of bit-serial processing elements (PE). Two-by-four surarrays of PE's are packaged in a custom VLSI HCMOS chip. The staging memory is a large multidimensional-access memory which buffers and permutes data flowing with the system. Efficient SAR processing is achieved via ARU communication paths and SM data manipulation. Real time processing capability can be realized via a multiple ARU, multiple SM configuration.

Batcher, K. E.↗
NASA NTRS1986

Real-time garbage collection for list processing

In a list processing system, small reference counters are maintained in conjunction with memory cells for the purpose of identifying memory cells that become available for re-use. The counters are updated as references to the cells are created and destroyed, and when a counter of a cell is decremented to logical zero the cell is immediately returned to a list of free cells. In those cases where a counter must be incremented beyond the maximum value that can be represented in a small counter, the cell is restructured so that the additional reference count can be represented. The restructuring involves allocating an additional cell, distributing counter, tag, and pointer information among the two cells, and linking both cells appropriately into the existing list structure.

Shuler, R. L., Jr.↗
NASA NTRS1988

Parallel solution of triangular systems of equations

The solution on parallel computers of systems of equations Lx = b, where L is lower triangular, is considered. Some authors have suggested that it is difficult to solve such systems in parallel on message-passing, local-memory machines when L is stored by columns. It is shown here that this is not necessarily the case if the machine can accomplish fan-in communication with reasonable efficiency.

Romine, Charles H.↗