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NASA NTRS2008

25th Space Simulation Conference. Environmental Testing: The Earth-Space Connection

Topics covered include: Methods of Helium Injection and Removal for Heat Transfer Augmentation; The ESA Large Space Simulator Mechanical Ground Support Equipment for Spacecraft Testing; Temperature Stability and Control Requirements for Thermal Vacuum/Thermal Balance Testing of the Aquarius Radiometer; The Liquid Nitrogen System for Chamber A: A Change from Original Forced Flow Design to a Natural Flow (Thermo Siphon) System; Return to Mercury: A Comparison of Solar Simulation and Flight Data for the MESSENGER Spacecraft; Floating Pressure Conversion and Equipment Upgrades of Two 3.5kw, 20k, Helium Refrigerators; Affect of Air Leakage into a Thermal-Vacuum Chamber on Helium Refrigeration Heat Load; Special ISO Class 6 Cleanroom for the Lunar Reconnaissance Orbiter (LRO) Project; A State-of-the-Art Contamination Effects Research and Test Facility Martian Dust Simulator; Cleanroom Design Practices and Their Influence on Particle Counts; Extra Terrestrial Environmental Chamber Design; Contamination Sources Effects Analysis (CSEA) - A Tool to Balance Cost/Schedule While Managing Facility Availability; SES and Acoustics at GSFC; HST Super Lightweight Interchangeable Carrier (SLIC) Static Test; Virtual Shaker Testing: Simulation Technology Improves Vibration Test Performance; Estimating Shock Spectra: Extensions beyond GEVS; Structural Dynamic Analysis of a Spacecraft Multi-DOF Shaker Table; Direct Field Acoustic Testing; Manufacture of Cryoshroud Surfaces for Space Simulation Chambers; The New LOTIS Test Facility; Thermal Vacuum Control Systems Options for Test Facilities; Extremely High Vacuum Chamber for Low Outgassing Processing at NASA Goddard; Precision Cleaning - Path to Premier; The New Anechoic Shielded Chambers Designed for Space and Commercial Applications at LIT; Extraction of Thermal Performance Values from Samples in the Lunar Dust Adhesion Bell Jar; Thermal (Silicon Diode) Data Acquisition System; Aquarius's Instrument Science Data System (ISDS) Automated to Acquire, Process, Trend Data and Produce Radiometric System Assessment Reports; Exhaustive Thresholds and Resistance Checkpoints; Reconfigurable HIL Testing of Earth Satellites; FPGA Control System for the Automated Test of MicroShutters; Ongoing Capabilities and Developments of Re-Entry Plasma Ground Tests at EADS-ASTRIUM; Operationally Responsive Space Standard Bus Battery Thermal Balance Testing and Heat Dissipation Analysis; Galileo - The Serial-Production AIT Challenge; The Space Systems Environmental Test Facility Database (SSETFD), Website Development Status; Simulated Reentry Heating by Torching; Micro-Vibration Measurements on Thermally Loaded Multi-Layer Insulation Samples in Vacuum; High Temperature Life Testing of 80Ni-20Cr Wire in a Simulated Mars Atmosphere for the Sample Analysis at Mars (SAM) Instrument Suit Gas Processing System (GPS) Carbon Dioxide Scrubber; The Planning and Implementation of Test Facility Improvements; and Development of a Silicon Carbide Molecular Beam Nozzle for Simulation Planetary Flybys and Low-Earth Orbit.

Packard, Edward↗
NASA NTRS2009

NASA Tech Briefs, May 2009

Topics covered include: Valve-"Health"-Monitoring System; Microstrip Antenna for Remote Sensing of Soil Moisture and Sea Surface Salinity; Biomedical Wireless Ambulatory Crew Monitor; Wireless Avionics Packet to Support Fault Tolerance for Flight Applications; Aerobot Autonomy Architecture; Submillimeter Confocal Imaging Active Module; Traveling-Wave Maser for 32 GHz; System Synchronizes Recordings from Separated Video Cameras; Piecewise-Planar Parabolic Reflectarray Antenna; Reducing Interference in ATC Voice Communication; EOS MLS Level 1B Data Processing, Version 2.2; Auto-Generated Semantic Processing Services; Geospatial Authentication; Maneuver Automation Software; Event Driven Messaging with Role-Based Subscriptions; Estimating Relative Positions of Outer-Space Structures; Fabricating PFPE Membranes for Capillary Electrophoresis; Linear Actuator Has Long Stroke and High Resolution; Installing a Test Tap on a Metal Battery Case; Fabricating PFPE Membranes for Microfluidic Valves and Pumps; Room-Temperature-Cured Copolymers for Lithium Battery Gel Electrolytes; Catalysts for Efficient Production of Carbon Nanotubes; Amorphous Silk Fibroin Membranes for Separation of CO2; "Zero-Mass" Noninvasive Pressure Transducers; Radial-Electric-Field Piezoelectric Diaphragm Pumps; Ejector-Enhanced, Pulsed, Pressure-Gain Combustor; Suppressing Ghost Diffraction in E-Beam-Written Gratings; Target-Tracking Camera for a Metrology System; Polarimetric Imaging using Two Photoelastic Modulators; Miniature Wide-Angle Lens for Small-Pixel Electronic Camera; Modal Filters for Infrared Interferometry; Mo(3)Sb(7-x)Te(x) for Thermoelectric Power Generation; Two-Dimensional Quantum Model of a Nanotransistor; Scanning Miniature Microscopes without Lenses; Manipulating Neutral Atoms in Chip-Based Magnetic Traps; Expansion Compression Contacts for Thermoelectric Legs; Processing Electromyographic Signals to Recognize Words; Physical Principle for Generation of Randomness; DSN Beowulf Cluster-Based VLBI Correlator; Hybrid NN/SVM Computational System for Optimizing Designs; Criteria for Modeling in LES of Multicomponent Fuel Flow; Computerized Machine for Cutting Space Shuttle Thermal Tiles; Orbiting Depot and Reusable Lander for Lunar Transportation; FPGA-Based Networked Phasemeter for a Heterodyne Interferometer; Aquarius Digital Processing Unit; Three-Dimensional Optical Coherence Tomography; Benchtop Antigen Detection Technique using Nanofiltration and Fluorescent Dyes; Isolation of Precursor Cells from Waste Solid Fat Tissue; Identification of Bacteria and Determination of Biological Indicators; Further Development of Scaffolds for Regeneration of Nerves; Chemically Assisted Photocatalytic Oxidation System; Use of Atomic Oxygen for Increased Water Contact Angles of Various Polymers for Biomedical Applications; Crashworthy Seats Would Afford Superior Protection; Open-Access, Low-Magnetic-Field MRI System for Lung Research; Microfluidic Mixing Technology for a Universal Health Sensor; Microfluidic Extraction of Biomarkers using Water as Solvent; Microwell Arrays for Studying Many Individual Cells; Droplet-Based Production of Liposomes; and Identifying and Inactivating Bacterial Spores

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NASA NTRS2009

Wireless Avionics Packet to Support Fault Tolerance for Flight Applications

In this protocol and packet format, data traffic is monitored by all network interfaces to determine the health of transmitter and subsystems. When failures are detected, the network inter face applies its recover y policies to provide continued service despite the presence of faults. The protocol, packet format, and inter face are independent of the data link technology used. The current demonstration system supports both commercial off-the-shelf wireless connections and wired Ethernet connections. Other technologies such as 1553 or serial data links can be used for the network backbone. The Wireless Avionics packet is divided into three parts: a header, a data payload, and a checksum. The header has the following components: magic number, version, quality of service, time to live, sending transceiver, function code, payload length, source Application Data Interface (ADI) address, destination ADI address, sending node address, target node address, and a sequence number. The magic number is used to identify WAV packets, and allows the packet format to be updated in the future. The quality of service field allows routing decisions to be made based on this value and can be used to route critical management data over a dedicated channel. The time to live value is used to discard misrouted packets while the source transceiver is updated at each hop. This information is used to monitor the health of each transceiver in the network. To identify the packet type, the function code is used. Besides having a regular data packet, the system supports diagnostic packets for fault detection and isolation. The payload length specifies the number of data bytes in the payload, and this supports variable-length packets in the network. The source ADI is the address of the originating interface. This can be used by the destination application to identify the originating source of the packet where the address consists of a subnet, subsystem class within the subnet, a subsystem unit, and the local ADI number. The destination ADI is used to route the packet to its ultimate destination. At each hop, the sending interface uses the destination address to determine the next node for the data. The sending node is the node address of the interface that is broadcasting the packet. This field is used to determine the health of the subsystem that is sending the packet. In the case of a packet that traverses several intermediate nodes, it may be the node address of the intermediate node. The target node is the node address of the next hop for the packet. It may be an intermediate node, or the final destination for the packet. The sequence number is used to identify duplicate packets. Because each interface has multiple transceivers, the same packet will appear at both receivers. The sequence number allows the interface to correlate the reception and forward a single, unique packet for additional processing. The subnet field allows data traffic to be partitioned into segregated local networks to support large networks while keeping each subnet at a manageable size. This also keeps the routing table small enough so routing can be done by a simple table lookup in an FPGA device. The subsystem class identifies members of a set of redundant subsystems, and, in a hot standby configuration, all members of the subsystem class will receive the data packets. Only the active subsystem will generate data traffic. Specific units in a class of redundant units can be identified and, if the hot standby configuration is not used, packets will be directed to a specific subsystem unit.

Block, Gary L.↗
NASA NTRS2008

GPS Metric Tracking Unit

As Global Positioning Satellite (GPS) applications become more prevalent for land- and air-based vehicles, GPS applications for space vehicles will also increase. The Applied Technology Directorate of Kennedy Space Center (KSC) has developed a lightweight, low-cost GPS Metric Tracking Unit (GMTU), the first of two steps in developing a lightweight, low-cost Space-Based Tracking and Command Subsystem (STACS) designed to meet Range Safety's link margin and latency requirements for vehicle command and telemetry data. The goals of STACS are to improve Range Safety operations and expand tracking capabilities for space vehicles. STACS will track the vehicle, receive commands, and send telemetry data through the space-based asset, which will dramatically reduce dependence on ground-based assets. The other step was the Low-Cost Tracking and Data Relay Satellite System (TDRSS) Transceiver (LCT2), developed by the Wallops Flight Facility (WFF), which allows the vehicle to communicate with a geosynchronous relay satellite. Although the GMTU and LCT2 were independently implemented and tested, the design collaboration of KSC and WFF engineers allowed GMTU and LCT2 to be integrated into one enclosure, leading to the final STACS. In operation, GMTU needs only a radio frequency (RF) input from a GPS antenna and outputs position and velocity data to the vehicle through a serial or pulse code modulation (PCM) interface. GMTU includes one commercial GPS receiver board and a custom board, the Command and Telemetry Processor (CTP) developed by KSC. The CTP design is based on a field-programmable gate array (FPGA) with embedded processors to support GPS functions.

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NASA NTRS2009

NASA Tech Briefs, August 2009

Topics covered include: Aligning a Receiving Antenna Array to Reduce Interference; Collecting Ground Samples for Balloon-Borne Instruments; Tethered Pyrotechnic Apparatus for Acquiring a Ground Sample; Enhanced Video-Oculography System; Joint Carrier-Phase Synchronization and LDPC Decoding; Dual-Polarization, Sideband-Separating, Balanced Receiver for 1.5 THz Modular Battery Charge Controller; Efficient Multiplexer FPGA Block Structures Based on G4FETs; VLSI Microsystem for Rapid Bioinformatic Pattern Recognition; Low-Noise Amplifier for 100 to 180 GHz; Improved Fabrication of Ceramic Matrix Composite/Foam Core Integrated Structures; Inert Welding/Brazing Gas Filters and Dryers; Fabricating Copper Nanotubes by Electrodeposition; Reducing Aerodynamic Drag on Empty Open Cargo Vehicles; Rotary Percussive Auto-Gopher for Deep Drilling and Sampling; More About Reconfigurable Exploratory Robotic Vehicles; Thermostatic Valves Containing Silicone-Oil Actuators; Improving Heat Flux Performance of Flat Surface in Spray-Cooling Systems; Treating Fibrous Insulation to Reduce Thermal Conductivity; Silica-Aerogel Composites Opacified with La(sub0.7)Sr(sub0.3)MnO3; Cyclic Oxidation Behavior of CuCrAl Cold-Sprayed Coatings for Reusable Launch Vehicles; Ceramic Fiber Structures for Cryogenic Load-Bearing Applications; Elastomer Reinforced with Carbon Nanotubes; Biologically Inspired Purification and Dispersion of SWCNTs; A Technique for Adjusting Eigenfrequencies of WGM Resonators; Low-Pressure, Field-Ionizing Mass Spectrometer; Modifying Operating Cycles to Increase Stability in a LITS; Chamber for Simulating Martian and Terrestrial Environments; Algorithm for Detecting a Bright Spot in an Image; Extreme Programming: Maestro Style; Adaptive Behavior for Mobile Robots; Protocol for Communication Networking for Formation Flying; Planning Complex Sequences Using Compressed Representations; and Self-Supervised Learning of Terrain Traversability from Proprioceptive Sensors.

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NASA NTRS2009

XML Translator for Interface Descriptions

A computer program defines an XML schema for specifying the interface to a generic FPGA from the perspective of software that will interact with the device. This XML interface description is then translated into header files for C, Verilog, and VHDL. User interface definition input is checked via both the provided XML schema and the translator module to ensure consistency and accuracy. Currently, programming used on both sides of an interface is inconsistent. This makes it hard to find and fix errors. By using a common schema, both sides are forced to use the same structure by using the same framework and toolset. This makes for easy identification of problems, which leads to the ability to formulate a solution. The toolset contains constants that allow a programmer to use each register, and to access each field in the register. Once programming is complete, the translator is run as part of the make process, which ensures that whenever an interface is changed, all of the code that uses the header files describing it is recompiled.

Boroson, Elizabeth R.↗
NASA NTRS2009

Solder Joint Health Monitoring Testbed System

The density and pin count for Field Programmable Gate Arrays (FPGAs) has been increasing, and has exceeded current methods of solder joint inspection, making early detection of failures more problematic. These failures are a concern for both flight safety and maintenance in commercial aviation. Ridgetop Group, Inc. has developed a method for detecting solder joint failures in real time. The NASA Dryden Flight Research Center is developing a set of boards to test this method in ground environmental and accelerated testing as well as flight test on a Dryden F-15 or F-18 research aircraft. In addition to detecting intermittent and total solder joint failures, environmental data on the boards, such as temperature and vibration, will be collected and time-correlated to aircraft state data. This paper details the technical approach involved in the detection process, and describes the design process and products to date for Dryden s FPGA failure detection boards.

Delaney, Michael M.↗
NASA NTRS2009

Solder Joint Health Monitoring Testbed

A method of monitoring the health of selected solder joints, called SJ-BIST, has been developed by Ridgetop Group Inc. under a Small Business Innovative Research (SBIR) contract. The primary goal of this research program is to test and validate this method in a flight environment using realistically seeded faults in selected solder joints. An additional objective is to gather environmental data for future development of physics-based and data-driven prognostics algorithms. A test board is being designed using a Xilinx FPGA. These boards will be tested both in flight and on the ground using a shaker table and an altitude chamber.

Delaney, Michael M.↗
NASA NTRS2009

LDPC Codes with Minimum Distance Proportional to Block Size

Low-density parity-check (LDPC) codes characterized by minimum Hamming distances proportional to block sizes have been demonstrated. Like the codes mentioned in the immediately preceding article, the present codes are error-correcting codes suitable for use in a variety of wireless data-communication systems that include noisy channels. The previously mentioned codes have low decoding thresholds and reasonably low error floors. However, the minimum Hamming distances of those codes do not grow linearly with code-block sizes. Codes that have this minimum-distance property exhibit very low error floors. Examples of such codes include regular LDPC codes with variable degrees of at least 3. Unfortunately, the decoding thresholds of regular LDPC codes are high. Hence, there is a need for LDPC codes characterized by both low decoding thresholds and, in order to obtain acceptably low error floors, minimum Hamming distances that are proportional to code-block sizes. The present codes were developed to satisfy this need. The minimum Hamming distances of the present codes have been shown, through consideration of ensemble-average weight enumerators, to be proportional to code block sizes. As in the cases of irregular ensembles, the properties of these codes are sensitive to the proportion of degree-2 variable nodes. A code having too few such nodes tends to have an iterative decoding threshold that is far from the capacity threshold. A code having too many such nodes tends not to exhibit a minimum distance that is proportional to block size. Results of computational simulations have shown that the decoding thresholds of codes of the present type are lower than those of regular LDPC codes. Included in the simulations were a few examples from a family of codes characterized by rates ranging from low to high and by thresholds that adhere closely to their respective channel capacity thresholds; the simulation results from these examples showed that the codes in question have low error floors as well as low decoding thresholds. As an example, the illustration shows the protograph (which represents the blueprint for overall construction) of one proposed code family for code rates greater than or equal to 1.2. Any size LDPC code can be obtained by copying the protograph structure N times, then permuting the edges. The illustration also provides Field Programmable Gate Array (FPGA) hardware performance simulations for this code family. In addition, the illustration provides minimum signal-to-noise ratios (Eb/No) in decibels (decoding thresholds) to achieve zero error rates as the code block size goes to infinity for various code rates. In comparison with the codes mentioned in the preceding article, these codes have slightly higher decoding thresholds.

Divsalar, Dariush↗
NASA NTRS2007

Advanced High-Definition Video Cameras

A product line of high-definition color video cameras, now under development, offers a superior combination of desirable characteristics, including high frame rates, high resolutions, low power consumption, and compactness. Several of the cameras feature a 3,840 2,160-pixel format with progressive scanning at 30 frames per second. The power consumption of one of these cameras is about 25 W. The size of the camera, excluding the lens assembly, is 2 by 5 by 7 in. (about 5.1 by 12.7 by 17.8 cm). The aforementioned desirable characteristics are attained at relatively low cost, largely by utilizing digital processing in advanced field-programmable gate arrays (FPGAs) to perform all of the many functions (for example, color balance and contrast adjustments) of a professional color video camera. The processing is programmed in VHDL so that application-specific integrated circuits (ASICs) can be fabricated directly from the program. ["VHDL" signifies VHSIC Hardware Description Language C, a computing language used by the United States Department of Defense for describing, designing, and simulating very-high-speed integrated circuits (VHSICs).] The image-sensor and FPGA clock frequencies in these cameras have generally been much higher than those used in video cameras designed and manufactured elsewhere. Frequently, the outputs of these cameras are converted to other video-camera formats by use of pre- and post-filters.

Glenn, William↗
NASA NTRS2009

Spacesuit Data Display and Management System

A prototype embedded avionics system has been designed for the next generation of NASA extra-vehicular-activity (EVA) spacesuits. The system performs biomedical and other sensor monitoring, image capture, data display, and data transmission. An existing NASA Phase I and II award winning design for an embedded computing system (ZIN vMetrics - BioWATCH) has been modified. The unit has a reliable, compact form factor with flexible packaging options. These innovations are significant, because current state-of-the-art EVA spacesuits do not provide capability for data displays or embedded data acquisition and management. The Phase 1 effort achieved Technology Readiness Level 4 (high fidelity breadboard demonstration). The breadboard uses a commercial-grade field-programmable gate array (FPGA) with embedded processor core that can be upgraded to a space-rated device for future revisions.

Hall, David G.↗
NASA NTRS2009

On DESTINY Science Instrument Electrical and Electronics Subsystem Framework

Future space missions are going to require large focal planes with many sensing arrays and hundreds of millions of pixels all read out at high data rates'' . This will place unique demands on the electrical and electronics (EE) subsystem design and it will be critically important to have high technology readiness level (TRL) EE concepts ready to support such missions. One such omission is the Joint Dark Energy Mission (JDEM) charged with making precise measurements of the expansion rate of the universe to reveal vital clues about the nature of dark energy - a hypothetical form of energy that permeates all of space and tends to increase the rate of the expansion. One of three JDEM concept studies - the Dark Energy Space Telescope (DESTINY) was conducted in 2008 at the NASA's Goddard Space Flight Center (GSFC) in Greenbelt, Maryland. This paper presents the EE subsystem framework, which evolved from the DESTINY science instrument study. It describes the main challenges and implementation concepts related to the design of an EE subsystem featuring multiple focal planes populated with dozens of large arrays and millions of pixels. The focal planes are passively cooled to cryogenic temperatures (below 140 K). The sensor mosaic is controlled by a large number of Readout Integrated Circuits and Application Specific Integrated Circuits - the ROICs/ASICs in near proximity to their sensor focal planes. The ASICs, in turn, are serviced by a set of "warm" EE subsystem boxes performing Field Programmable Gate Array (FPGA) based digital signal processing (DSP) computations of complex algorithms, such as sampling-up-the-ramp algorithm (SUTR), over large volumes of fast data streams. The SUTR boxes are supported by the Instrument Control/Command and Data Handling box (ICDH Primary and Backup boxes) for lossless data compression, command and low volume telemetry handling, power conversion and for communications with the spacecraft. The paper outlines how the JDEM DESTINY concept instrument EE subsystem can be built now, a design; which is generally U.S. Government work not protected by U.S. copyright IEEEAC paper # 1429. Version 4. Updated October 19, 2009 applicable to a wide variety of missions using large focal planes with lar ge mosaics of sensors.

Kizhner, Semion↗
NASA NTRS2007

NASA Tech Briefs, June 2007

Topics covered include: High-Accuracy, High-Dynamic-Range Phase-Measurement System; Simple, Compact, Safe Impact Tester; Multi-Antenna Radar Systems for Doppler Rain Measurements; 600-GHz Electronically Tunable Vector Measurement System; Modular Architecture for the Measurement of Space Radiation; VLSI Design of a Turbo Decoder; Architecture of an Autonomous Radio Receiver; Improved On-Chip Measurement of Delay in an FPGA or ASIC; Resource Selection and Ranking; Accident/Mishap Investigation System; Simplified Identification of mRNA or DNA in Whole Cells; Printed Multi-Turn Loop Antennas for RF Biotelemetry; Making Ternary Quantum Dots From Single-Source Precursors; Improved Single-Source Precursors for Solar-Cell Absorbers; Spray CVD for Making Solar-Cell Absorber Layers; Glass/BNNT Composite for Sealing Solid Oxide Fuel Cells; A Method of Assembling Compact Coherent Fiber-Optic Bundles; Manufacturing Diamond Under Very High Pressure; Ring-Resonator/Sol-Gel Interferometric Immunosensor; Compact Fuel-Cell System Would Consume Neat Methanol; Algorithm Would Enable Robots to Solve Problems Creatively; Hypothetical Scenario Generator for Fault-Tolerant Diagnosis; Smart Data Node in the Sky; Pseudo-Waypoint Guidance for Proximity Spacecraft Maneuvers; Update on Controlling Herds of Cooperative Robots; and Simulation and Testing of Maneuvering of a Planetary Rover.

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NASA NTRS2010

Radiation-Hardened Solid-State Drive

A method is provided for a radiationhardened (rad-hard) solid-state drive for space mission memory applications by combining rad-hard and commercial off-the-shelf (COTS) non-volatile memories (NVMs) into a hybrid architecture. The architecture is controlled by a rad-hard ASIC (application specific integrated circuit) or a FPGA (field programmable gate array). Specific error handling and data management protocols are developed for use in a rad-hard environment. The rad-hard memories are smaller in overall memory density, but are used to control and manage radiation-induced errors in the main, and much larger density, non-rad-hard COTS memory devices. Small amounts of rad-hard memory are used as error buffers and temporary caches for radiation-induced errors in the large COTS memories. The rad-hard ASIC/FPGA implements a variety of error-handling protocols to manage these radiation-induced errors. The large COTS memory is triplicated for protection, and CRC-based counters are calculated for sub-areas in each COTS NVM array. These counters are stored in the rad-hard non-volatile memory. Through monitoring, rewriting, regeneration, triplication, and long-term storage, radiation-induced errors in the large NV memory are managed. The rad-hard ASIC/FPGA also interfaces with the external computer buses.

Sheldon, Douglas J.↗
NASA NTRS2010

Reconfigurable Hardware for Compressing Hyperspectral Image Data

High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including Context Modeler for Wavelet Compression of Hyperspectral Images (NPO-43239) and ICER-3D Hyperspectral Image Compression Software (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs). The design takes advantage of industry- standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes. The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W. The reconfigurability (by means of reprogramming) of the FPGAs makes it possible to effectively alter the design to some extent to satisfy different requirements without adding hardware. The implementation could be easily propagated to future FPGA generations and/or to custom application-specific integrated circuits.

Aranki, Nazeeh↗
NASA NTRS2010

Compact Ku-Band T/R Module for High-Resolution Radar Imaging of Cold Land Processes

Global measurement of terrestrial snow cover is critical to two of the NASA Earth Science focus areas: (1) climate variability and change and (2) water and energy cycle. For radar backscatter measurements, Ku-band frequencies, scattered mainly within the volume of the snowpack, are most suitable for the SWE (snow-water equivalent) measurements. To isolate the complex effects of different snowpack (density and snowgrain size), and underlying soil properties and to distinctly determine SWE, the space-based synthetic aperture radar (SAR) system will require a dual-frequency (13.4 and 17.2 GHz) and dual polarization approach. A transmit/receive (T/R) module was developed operating at Ku-band frequencies to enable the use of active electronic scanning phased-array antenna for wide-swath, high-resolution SAR imaging of terrestrial snow cover. The T/R module has an integrated calibrator, which compensates for all environmental- and time-related changes, and results in very stable power and amplitude characteristics. The module was designed to operate over the full frequency range of 13 to 18 GHz, although only the two frequencies, 13.4 GHz and 17.2 GHz, will be used in this SAR radar application. Each channel of the transmit module produces > 4 W (35 dbm) over the operating bandwidth of 20 MHz. The stability requirements of <0.1 dB receive gain accuracy and <0.1 dB transmit power accuracy over a wide temperature range are achieved using a self-correction scheme, which does real-time amplitude calibration so that the module characteristics are continually corrected. All the calibration circuits are within the T/R module. The timing and calibration sequence is stored in a control FPGA (field-programmable gate array) while an internal 128K 8bit high-speed RAM (random access memory) stores all the calibration values. The module was designed using advanced components and packaging techniques to achieve integration of the electronics in a 2 x6.5x1-in. (5x17x2.5-cm) package. The module size allows 4 T/R modules to feed the 16 16-element subarray on an antenna panel. The T/R module contains four transmit channels and eight receive channels (horizontal and vertical polarizations).

Andricos, Constantine↗
NASA NTRS2006

Programmable Pulse-Position-Modulation Encoder

A programmable pulse-position-modulation (PPM) encoder has been designed for use in testing an optical communication link. The encoder includes a programmable state machine and an electronic code book that can be updated to accommodate different PPM coding schemes. The encoder includes a field-programmable gate array (FPGA) that is programmed to step through the stored state machine and code book and that drives a custom high-speed serializer circuit board that is capable of generating subnanosecond pulses. The stored state machine and code book can be updated by means of a simple text interface through the serial port of a personal computer.

Zhu, David↗
NASA NTRS2006

Orbiting GPS Receiver Modified to Track New L2C Signal

The L2C signal is a great step forward for civil applications of GPS, enabling high-accuracy dual-frequency measurements. Engineers from the Jet Propulsion Laboratory and ITT teamed to reprogram FPGA firmware and add tracking software on an orbiting receiver to track the new GPS L2C signal from SAC-C. SAC-C is an Argentinean science satellite and was launched in November 2000 with a BlackJack GPS receiver. This is a dual-frequency digital receiver with 48 tracking channels and four antennas. On SAC-C, it provides precise orbits, atmospheric occultation data, tests of GPS surface reflections, and serves as an orbiting test bed for new GPS development such as the L2C tracking reported here.

GPS receiver↗