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Digital phase-shift standard used in combination with oscillator to calibrate other phase standards and phase-angle voltmeters. Phase-shifter circuit provides two square-wave outputs, A and B, with phase difference between them selectable in 30 degrees increments. Circuit is used with input signals as low as 1 volt rms, in almost any waveform.
The measurement of atmospheric water vapor is very important for understanding the Earth's climate and water cycle. The lidar atmospheric sensing experiment (LASE) is an instrument designed and operated by the Langley Research Center for high precision water vapor measurements. The design details of a new water vapor lidar detection system that improves the measurement sensitivity of the LASE instrument by a factor of 10 are discussed. The new system consists of an advanced, very low noise, avalanche photodiode (APD) and a state-of-the-art signal processing circuit. The new low-power system is also compact and lightweight so that it would be suitable for space flight and unpiloted atmospheric vehicles (UAV) applications. The whole system is contained on one small printed circuit board (9 x 15 sq cm). The detection system is mounted at the focal plane of a lidar receiver telescope, and the digital output is read by a personal computer with a digital data acquisition card.
A computer program provides a high-level C-language interface to electronics circuitry that controls a SpaceWire interface in a system based on a space qualified version of the ADSP-21020 digital signal processor (DSP). SpaceWire is a spacecraft-oriented standard for packet-switching data-communication networks that comprise nodes connected through bidirectional digital serial links that utilize low-voltage differential signaling (LVDS). The software is tailored to the SMCS-332 application-specific integrated circuit (ASIC) (also available as the TSS901E), which provides three highspeed (150 Mbps) serial point-to-point links compliant with the proposed Institute of Electrical and Electronics Engineers (IEEE) Standard 1355.2 and equivalent European Space Agency (ESA) Standard ECSS-E-50-12. In the specific application of this software, the SpaceWire ASIC was combined with the DSP processor, memory, and control logic in a Multi-Chip Module DSP (MCM-DSP). The software is a collection of low-level driver routines that provide a simple message-passing application programming interface (API) for software running on the DSP. Routines are provided for interrupt-driven access to the two styles of interface provided by the SMCS: (1) the "word at a time" conventional host interface (HOCI); and (2) a higher performance "dual port memory" style interface (COMI).
Development of thermometer to provide quick and accurate temperature readings using thermal resistance probe as temperature-to-resistance transducer is discussed. Details of construction and operations are described. Illustration of circuit and components is provided.
A low phase noise frequency divider composed of a grating arrangement is disclosed. The grating arrangement supplies selected portions of an input reference signal to be divided to a tuned circuit without any phase noise due to the grating action. The arrangement which in one embodiment consists of an FET is connected to the tuned circuit input to short out the input except when the input reference signal amplitude crosses ground level in a positive direction and a gate enabling signal is present at the gate electrode of the FET. The gate enabling signal alone does not decouple the tuned circuit input from ground, therefore phase noise, due to the leading and trailing edges of each gate-enabling signal, is substantially eliminated.
Switches, electrical components that either permit or prevent the flow of electricity, are the most important and widely used electrical devices in integrated circuits. In microwave systems, switches are required for switching between the transmitter and receiver; in communication systems, they are needed for phase shifters in phased-array antennas, for radar and communication systems, and for the new class of digital or software definable radios. Ideally, switches would be lossless devices that did not depend on the electrical signal's frequency or power, and they would not consume electrical power to change from OFF to ON or to maintain one of these two states. Reality is quite different, especially at microwave frequencies. Typical switches in microwave integrated circuits are pin diodes or gallium arsenide (GaAs) field-effect transistors that are nonlinear, with characteristics that depend on the power of the signal. In addition, they are frequency-dependent, lossy, and require electrical power to maintain a certain state. A new type of component has been developed that overcomes most of these technical difficulties. Microelectromechanical (MEMS) switches rely on mechanical movement as a response to an applied electrical force to either transmit or reflect electrical signal power. The NASA Glenn Research Center has been actively developing MEMS for microwave applications for over the last 5 years. Complete fabrication procedures have been developed so that the moving parts of the switch can be released with near 100-percent yield. Moreover, the switches fabricated at Glenn have demonstrated state-of-the-art performance. A typical MEMS switch is shown. The switch extends over the signal and ground lines of a finite ground coplanar waveguide, a commonly used microwave transmission line. In the state shown, the switch is in the UP state and all the microwave power traveling along the transmission line proceeds unimpeded. When a potential difference is applied between the cantilever and the transmission line, the cantilever is pulled downward until it connects the signal line to the ground planes, creating a short circuit. In this state, all the microwave power is reflected. The graph shows the measured performance of the switch, which has less than 0.1 dB of insertion loss and greater than 30dB of isolation. These switches consume negligible electrical power and are extremely linear. Additional research is required to address reliability and to increase the switching speed.
A command interface application-specific integrated circuit (ASIC) and an analog interface ASIC have been developed as a chip set for remote actuation and monitoring of a collection of switches, which can be used to control generic loads, pyrotechnic devices, and valves in a high-radiation environment. The command interface ASIC (CIA) can be used alone or in combination with the analog interface ASIC (AIA). Designed primarily for incorporation into spacecraft control systems, they are also suitable for use in high-radiation terrestrial environments (e.g., in nuclear power plants and facilities that process radioactive materials). The primary role of the CIA within a spacecraft or other power system is to provide a reconfigurable means of regulating the power bus, actuating all valves, firing all pyrotechnic devices, and controlling the switching of power to all switchable loads. The CIA is a mixed-signal (analog and digital) ASIC that includes an embedded microcontroller with supporting fault-tolerant switch control and monitoring circuitry that is capable of connecting to a redundant set of interintegrated circuit (I(sup 2)C) buses. Commands and telemetry requests are communicated to the CIA. Adherence to the I(sup 2)C bus standard helps to reduce development costs by facilitating the use of previously developed, commercially available components. The AIA is a mixed-signal ASIC that includes the analog circuitry needed to connect the CIA to a custom higher powered version of the I(sup 2)C bus. The higher-powered version is designed to enable operation with bus cables longer than those contemplated in the I(sup 2)C standard. If there are multiple higher-power I(sup 2)C-like buses, then there must an AIA between the CIA and each such bus. The AIA includes two identical interface blocks: one for the side-A I(sup 2)C clock and data buses and the other for the side B buses. All the AIAs on each side are powered from a common power converter module (PCM). Sides A and B of the I(sup 2)C buses are electrically isolated from each other (see figure). They are also isolated from the CIA by use of transformer coupling of signals between the AIA blocks and the CIA.
At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.
A speech compression project has recently been completed to develop a speech coding algorithm suitable for operation in a mobile satellite environment aimed at providing telephone quality natural speech at 4.8 kbps. The work has resulted in two alternative techniques which achieve reasonably good communications quality at 4.8 kbps while tolerating vehicle noise and rather severe channel impairments. The algorithms are embodied in a compact self-contained prototype consisting of two AT and T 32-bit floating-point DSP32 digital signal processors (DSP). A Motorola 68HC11 microcomputer chip serves as the board controller and interface handler. On a wirewrapped card, the prototype's circuit footprint amounts to only 200 sq cm, and consumes about 9 watts of power.
Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.
Circuit designed for measurement of dc current-versus-voltage characteristics of semiconductor devices. Operates in conjunction with x-y pen plotter or digital storage oscilloscope, which records data. Includes large feedback resistors to prevent high currents damaging device under test. Principal virtues: low cost, simplicity, and compactness. Also used to evaluate diodes and transistors.
Improved design for modulator and demodulator in offset-quaternary-phase-key-shifting (OQPSK) communication system enables receiver to resolve ambiguity in estimated phase of received signal. Features include unique-code-word modulation and detection and digital implementation of Costas loop in carrier-recovery subsystem. Enchances performance of carrier-recovery subsystem, reduces complexity of receiver by removing redundant circuits from previous design, and eliminates dependence of timing in receiver upon parallel-to-serial-conversion clock.
This paper presents approaches for on-focal-plane analog-to-digital conversion (ADC). Common approaches and architectures for ADC and their utility for on-focal-plane integration are discussed. Candidate approaches are analyzed with respect to required amplifier gain, bandwidth, capacitance matching, noise and offsets as a function of ADC resolution. A column-parallel ADC architecture appears to be an effective compromise of chip area, power, circuit speed and ADC resolution. The discussion is valid for both infrared focal-plane arrays (FPAs) and visible image sensors.
A digital communication system is reported for parallel operation of 16 or more transceiver units with the use of only four interconnecting wires. A remote synchronization circuit produces unit address control words sequentially in data frames of 16 words. Means are provided in each transceiver unit to decode calling signals and to transmit calling and data signals. The transceivers communicate with each other over one data line. The synchronization unit communicates the address control information to the transceiver units over an address line and further provides the timing information over a clock line. A reference voltage level or ground line completes the interconnecting four wire hookup.
Methods of decoding a digital word to display alpha-numeric characters for driving a standard seven-segment LED display have been devised for Omega station identification. The circuit could replace the system now being used in Ohio University's Omega receivers, which lights one of eight LED's to signify the Omega time slot being received. The letters A through H, representing the Omega stations, can be read directly from the seven-segment display.
Digital phase-shifting network is used as synchronous frequency multiplier for applications such as phase-locking two signals that may differ in frequency. Circuit has various phase-shift capability. Possible applications include data-communication systems and hybrid digital/analog phase-locked loops.
A proof-of-concept computer program called IGGLOSS (Interim Generalized Gate Logic Software Simulator) was developed and is discussed. The simulator engine was designed to perform stochastic estimation of self test coverage (fault-detection latency times) of digital computers or systems. A major attribute of the IGGLOSS is its high-speed simulation: 9.5 x 1,000,000 gates/cpu sec for nonfaulted circuits and 4.4 x 1,000,000 gates/cpu sec for faulted circuits on a VAX 11/780 host computer.
This system provides a portable means to detect gas flow through a thin-walled tube without breaking into the tubing system. The flow detection system was specifically designed to detect flow through two parallel branches of a manifold with only one inlet and outlet, and is a means for verifying a space shuttle program requirement that saves time and reduces the risk of flight hardware damage compared to the current means of requirement verification. The prototype Purge Vent and Drain Window Cavity Conditioning System (PVD WCCS) Flow Detection System consists of a heater and a temperature-sensing thermistor attached to a piece of Velcro to be attached to each branch of a WCCS manifold for the duration of the requirement verification test. The heaters and thermistors are connected to a shielded cable and then to an electronics enclosure, which contains the power supplies, relays, and circuit board to provide power, signal conditioning, and control. The electronics enclosure is then connected to a commercial data acquisition box to provide analog to digital conversion as well as digital control. This data acquisition box is then connected to a commercial laptop running a custom application created using National Instruments LabVIEW. The operation of the PVD WCCS Flow Detection System consists of first attaching a heater/thermistor assembly to each of the two branches of one manifold while there is no flow through the manifold. Next, the software application running on the laptop is used to turn on the heaters and to monitor the manifold branch temperatures. When the system has reached thermal equilibrium, the software application s graphical user interface (GUI) will indicate that the branch temperatures are stable. The operator can then physically open the flow control valve to initiate the test flow of gaseous nitrogen (GN2) through the manifold. Next, the software user interface will be monitored for stable temperature indications when the system is again at thermal equilibrium with the test flow of GN2. The temperature drop of each branch from its "no flow" stable temperature peak to its stable "with flow" temperature will allow the operator to determine whether a minimum level of flow exists. An alternative operation has the operator turning on the software only long enough to record the ambient temperature of the tubing before turning on the heaters and initiating GN2 flow. The stable temperature of the heated tubing with GN2 flow is then compared with the ambient tubing temperature to determine if flow is present in each branch. To help quantify the level of flow in the manifolds, each branch will be bench calibrated to establish its thermal properties using the flow detection system and different flow rates. These calibration values can then be incorporated into the software application to provide more detailed flow rate information.