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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 721 records · Page 40
All sourcesNASA NTRSDOE OSTI
NASA NTRS1995

The Effect of Interrupts on Software Pipeline Execution on Message-Passing Architectures

Pipelining is a common strategy for extracting parallelism from a collection of independent computational tasks, each of which is spread among a number of processors and has an implied data dependence. When implemented on MIMD parallel computers with finite process interrupt times, pipeline algorithms suffer from slowdown--in addition to the expected pipeline fill time--due to a wave-like propagation of delays. This phenomenon, which has been observed experimentally using the performance monitoring system AIMS, is investigated analytically, and an optimal correction is derived to eliminate the wave. Efficiency increase through the correction is verified experimentally.

VanderWijngaart, Rob F.↗
NASA NTRS1997

Charon Toolkit for Parallel, Implicit Structured-Grid Computations: Functional Design

In a previous report the design concepts of Charon were presented. Charon is a toolkit that aids engineers in developing scientific programs for structured-grid applications to be run on MIMD parallel computers. It constitutes an augmentation of the general-purpose MPI-based message-passing layer, and provides the user with a hierarchy of tools for rapid prototyping and validation of parallel programs, and subsequent piecemeal performance tuning. Here we describe the implementation of the domain decomposition tools used for creating data distributions across sets of processors. We also present the hierarchy of parallelization tools that allows smooth translation of legacy code (or a serial design) into a parallel program. Along with the actual tool descriptions, we will present the considerations that led to the particular design choices. Many of these are motivated by the requirement that Charon must be useful within the traditional computational environments of Fortran 77 and C. Only the Fortran 77 syntax will be presented in this report.

VanderWijngaart, Rob F.↗
NASA NTRS2006

Real-time software receiver

A real-time software receiver that executes on a general purpose processor. The software receiver includes data acquisition and correlator modules that perform, in place of hardware correlation, baseband mixing and PRN code correlation using bit-wise parallelism.

Ledvina, Brent M.↗
NASA NTRS2007

Real-time software receiver

A real-time software receiver that executes on a general purpose processor. The software receiver includes data acquisition and correlator modules that perform, in place of hardware correlation, baseband mixing and PRN code correlation using bit-wise parallelism.

Ledvina, Brent M.↗
NASA NTRS2008

NASA Tech Briefs, March 2008

Topics covered include: WRATS Integrated Data Acquisition System; Breadboard Signal Processor for Arraying DSN Antennas; Digital Receiver Phase Meter; Split-Block Waveguide Polarization Twist for 220 to 325 GHz; Nano-Multiplication-Region Avalanche Photodiodes and Arrays; Tailored Asymmetry for Enhanced Coupling to WGM Resonators; Disabling CNT Electronic Devices by Use of Electron Beams; Conical Bearingless Motor/Generators; Integrated Force Method for Indeterminate Structures; Carbon-Nanotube-Based Electrodes for Biomedical Applications; Compact Directional Microwave Antenna for Localized Heating; Using Hyperspectral Imagery to Identify Turfgrass Stresses; Shaping Diffraction-Grating Grooves to Optimize Efficiency; Low-Light-Shift Cesium Fountain without Mechanical Shutters; Magnetic Compensation for Second-Order Doppler Shift in LITS; Nanostructures Exploit Hybrid-Polariton Resonances; Microfluidics, Chromatography, and Atomic-Force Microscopy; Model of Image Artifacts from Dust Particles; Pattern-Recognition System for Approaching a Known Target; Orchestrator Telemetry Processing Pipeline; Scheme for Quantum Computing Immune to Decoherence; Spin-Stabilized Microsatellites with Solar Concentrators; Phase Calibration of Antenna Arrays Aimed at Spacecraft; Ring Bus Architecture for a Solid-State Recorder; and Image Compression Algorithm Altered to Improve Stereo Ranging.

Source record↗
NASA NTRS2006

Partial Automation of Requirements Tracing

Requirements Tracing on Target (RETRO) is software for after-the-fact tracing of textual requirements to support independent verification and validation of software. RETRO applies one of three user-selectable information-retrieval techniques: (1) term frequency/inverse document frequency (TF/IDF) vector retrieval, (2) TF/IDF vector retrieval with simple thesaurus, or (3) keyword extraction. One component of RETRO is the graphical user interface (GUI) for use in initiating a requirements-tracing project (a pair of artifacts to be traced to each other, such as a requirements spec and a design spec). Once the artifacts have been specified and the IR technique chosen, another component constructs a representation of the artifact elements and stores it on disk. Next, the IR technique is used to produce a first list of candidate links (potential matches between the two artifact levels). This list, encoded in Extensible Markup Language (XML), is optionally processed by a filtering component designed to make the list somewhat smaller without sacrificing accuracy. Through the GUI, the user examines a number of links and returns decisions (yes, these are links; no, these are not links). Coded in XML, these decisions are provided to a "feedback processor" component that prepares the data for the next application of the IR technique. The feedback reduces the incidence of erroneous candidate links. Unlike related prior software, RETRO does not require the user to assign keywords, and automatically builds a document index.

Hayes, Jane↗
NASA NTRSDate not supplied

BRAINSTACK – A Platform for Artificial Intelligence & Machine Learning Collaborative Experiments on a Nano-Satellite

As space missions continue to become more ambitious, complex, and distant to Earth, the need for advanced on-board intelligent decision making to guide everything from mission operations to fault detection and recovery has become a major front of space research. While the prevalence of research on such Artificial Intelligence / Machine Learning (AI/ML) modules has exploded, the capacity to experimentally validate such modules in space in a rapid and inexpensive format has not. To this end, the Nano Orbital Workshop (NOW) group at NASA Ames Research Center has been at the forefront of performing initial flight evaluation tests of ‘commercially’ available AI/ML computational platforms via the TechEdSat (TES-n) flight series as part of what is programmatically referred to as the BRAINSTACK. BRAINSTACK will provide an orbital AI/ML evaluation laboratory where computational experiments are pre-loaded into memory prior to launch, and then executed as desired during the mission, with results reported back and program tweaks or new data sets uploaded as needed. Processors selected as part of the BRAINSTACK are of ideal size, packaging, and power consumption for easy integration into a cube satellite structure. These experiments have included the evaluation of small, high-performance GPUs and more recently, neuromorphic processors in LEO operations. Neuromorphic processors are of particular interest due to their superior computational power efficiency over GPUs. The first TES-n flight test of an Intel first-generation Loihi neuromorphic processor launched on January 13, 2022 and continues to operate in orbit despite almost no space environment modifications. The Intel Loihi Gen-1 is characterized by a 14nm 128-core Spiking Neural Network (SNN) able to support on-chip training. This experiment utilized a Loihi packaged in the ‘Kapoho Bay’ USB module, providing a relatively straight-forward interface to the bus avionics system. The Kapoho Bay was in turn managed by a host Intel Pentium single-board computer to handle scheduling of the AI/ML application payloads, and communications with the satellite vehicle manager. The recently released Intel Loihi Gen-2, able to support integer-valued spike payloads and produced using 7nm process, will form part of the basis of the evolving BRAINSTACK in the upcoming three TES-n/NOW flights. Additionally, it is planned to measure the radiation environment these processors experience to understand any degradation or computational artifacts caused by long term space radiation exposure on these novel architectures. This evolving flexible and collaborative environment involving various research teams across NASA and other organizations is intended to be a convenient orbital test platform from which many anticipated future space AI/ML applications may be initially tested.

Artificial Intelligence↗
NASA NTRSDate not supplied

BRAINSTACK – A Platform for Artificial Intelligence & Machine Learning Collaborative Experiments on a Nano-Satellite

As space missions continue to become more ambitious, complex, and distant to Earth, the need for advanced on-board intelligent decision making to guide everything from mission operations to fault detection and recovery has become a major front of space research. While the prevalence of research on such Artificial Intelligence / Machine Learning (AI/ML) modules has exploded, the capacity to experimentally validate such modules in space in a rapid and inexpensive format has not. To this end, the Nano Orbital Workshop (NOW) group at NASA Ames Research Center has been at the forefront of performing initial flight evaluation tests of ‘commercially’ available AI/ML computational platforms via the TechEdSat (TES-n) flight series as part of what is programmatically referred to as the BRAINSTACK. BRAINSTACK will provide an orbital AI/ML evaluation laboratory where computational experiments are pre-loaded into memory prior to launch, and then executed as desired during the mission, with results reported back and program tweaks or new data sets uploaded as needed. Processors selected as part of the BRAINSTACK are of ideal size, packaging, and power consumption for easy integration into a cube satellite structure. These experiments have included the evaluation of small, high-performance GPUs and more recently, neuromorphic processors in LEO operations. Neuromorphic processors are of particular interest due to their superior computational power efficiency over GPUs. The first TES-n flight test of an Intel first-generation Loihi neuromorphic processor launched on January 13, 2022 and continues to operate in orbit despite almost no space environment modifications. The Intel Loihi Gen-1 is characterized by a 14nm 128-core Spiking Neural Network (SNN) able to support on-chip training. This experiment utilized a Loihi packaged in the ‘Kapoho Bay’ USB module, providing a relatively straight-forward interface to the bus avionics system. The Kapoho Bay was in turn managed by a host Intel Pentium single-board computer to handle scheduling of the AI/ML application payloads, and communications with the satellite vehicle manager. The recently released Intel Loihi Gen-2, able to support integer-valued spike payloads and produced using 7nm process, will form part of the basis of the evolving BRAINSTACK in the upcoming three TES-n/NOW flights. Additionally, it is planned to measure the radiation environment these processors experience to understand any degradation or computational artifacts caused by long term space radiation exposure on these novel architectures. This evolving flexible and collaborative environment involving various research teams across NASA and other organizations is intended to be a convenient orbital test platform from which many anticipated future space AI/ML applications may be initially tested.

Artificial Intelligence↗
DOE OSTI2014

Isotopic Analysis of Spent Nuclear Fuel with an Ultra-High Rate HPGe Spectrometer

A longstanding challenge is the assay of spent nuclear fuel (SNF). Determining the isotopic content of SNF requires gamma-ray spectroscopy. PNNL has developed new digital filtering and analysis techniques to produce an ultra high-rate gamma-ray spectrometer from a standard coaxial high-purity germanium (HPGe) crystal. This ~40% efficient detector has been operated for SNF measurements at a throughput of about 400k gamma-ray counts per second (kcps) at an input rate of 1.3 Mcps. Optimized filtering algorithms preserve the spectroscopic capability of the system even at these high rates. This talk will present the results of a SNF measurement with aged SNF pellets at PNNL’s Radiochemical Processing Laboratory, first results with a FPGA front end processor capable of processing the data in real time, and the development path toward a multi-element system to assay fuel assemblies.

Fast, James E.↗
DOE OSTI2021

Methods and devices for preventing computationally explosive calculations in a computer for model parameters distributed on a hierarchy of geometric simplices

A computer-implemented method of preventing computationally explosive calculations. The method includes obtaining, by a processor of the computer, measured data of one of a physical process or a physical object; performing hierarchical numerical modeling of a physical process inclusive of an Earth model containing at least one of (a) infrastructure in the ground and (b) a formation feature in the ground, wherein predicted data is generated; comparing the measured data to the predicted data to calculate an estimated error; analyzing the estimated error via an inversion process to update the at least one of the Earth model and infrastructure model so as to reduce the estimated error and to determine a final composite Earth model of at least one of the infrastructure and the feature; and using the final composite Earth model to characterize at least one of the process and the physical object.

Source record↗
DOE OSTI2016

High-performance epistasis detection in quantitative trait GWAS

epiSNP is a program for identifying pairwise single nucleotide polymorphism (SNP) interactions (epistasis) in quantitative-trait genome-wide association studies (GWAS). A parallel MPI version (EPISNPmpi) was created in 2008 to address this computationally expensive analysis on large data sets with many quantitative traits and SNP markers. However, the falling cost of genotyping has led to an explosion of large-scale GWAS data sets that challenge EPISNPmpi’s ability to compute results in a reasonable amount of time. Therefore, we optimized epiSNP for modern multi-core and highly parallel many-core processors to efficiently handle these large data sets. This paper describes the serial optimizations, dynamic load balancing using MPI-3 RMA operations, and shared-memory parallelization with OpenMP to further enhance load balancing and allow execution on the Intel Xeon Phi coprocessor (MIC). For a large GWAS data set, our optimizations provided a 38.43× speedup over EPISNPmpi on 126 nodes using 2 MICs on TACC’s Stampede Supercomputer. We also describe a Coarray Fortran (CAF) version that demonstrates the suitability of PGAS languages for problems with this computational pattern. We show that the Coarray version performs competitively with the MPI version on the NERSC Edison Cray XC30 supercomputer. Finally, the performance benefits of hyper-threading for this application on Edison (average 1.35× speedup) are demonstrated.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1992

Implementation and performance of the Magellan digital correlator subsystem

The Magellan synthetic aperture radar (SAR) produces Venus surface images from data collected by the SAR carried on board the Magellan spacecraft. The core of the primary Magellan SAR processor is the digital correlator subsystem (DCS). The pipeline DSC architecture enables the Magellan primary SAR processor (PSP) to achieve real-time data processing capability. The implementation and performance of the DSC are described. Hardware (H/W) constraints that influenced the processing algorithm design are highlighted.

Chen, M.↗
DOE OSTI2019

Network-aware cache coherence protocol enhancement

A non-uniform memory access system includes several nodes that each have one or more processors, caches, local main memory, and a local bus that connects a node's processor(s) to its memory. The nodes are coupled to one another over a collection of point-to-point interconnects, thereby permitting processors in one node to access data stored in another node. Memory access time for remote memory takes longer than local memory because remote memory accesses have to travel across a communications network to arrive at the requesting processor. In some embodiments, inter-cache and main-memory-to-cache latencies are measured to determine whether it would be more efficient to satisfy memory access requests using cached copies stored in caches of owning nodes or from main memory of home nodes.

Roberts, David A.↗
NASA NTRS1980

Mark 3 correlator hardware and software

The Mark 3 correlator system is described in some detail. The correlator system is based on a modular philosophy. Each correlator module independently processes the data from one track pair. Therefore, 28 modules are necessary to complete a full one baseline processor and 84 modules for a full 3 baseline processor. Each correlator module has two interfaces: (1) data and clock from each of the two tracks to be correlated and (2) Computer Automated Measurement and Control (CAMAC) dataway interface to the computer. The processor is organized around the IEEE CAMAC standard architecture, housing 15 correlator modules in each of 6 crates. This allows one pass processing of a full 3 baseline 28 track observation or a 6 baseline (4 station) 14 track observation. The correlator architecture allows easy expansion for up to 8 stations. The computer system is an HP 1000 system utilizing a 16 bit minicomputer with disc and tape peripherals. The processing software is also organized in a modular fashion with many independent but cooperative programs controlling the operation of the Mark 3 processor. Processing time through the correlator is normally real time or faster, with graphics displays providing real time monitor and control of the processing operation.

Whitney, A. R.↗
DOE OSTI2022

Deep learning to estimate permeability using geophysical data

Time-lapse electrical resistivity tomography (ERT) is a popular geophysical method to estimate three-dimensional (3D) permeability fields from electrical potential difference measurements. Traditional inversion and data assimilation methods are used to ingest this ERT data into hydrogeophysical models to estimate permeability. Due to ill-posedness and the curse of dimensionality, existing inversion strategies provide poor estimates and low resolution of the 3D permeability field. Recent advances in deep learning provide us with powerful algorithms to overcome this challenge. This paper presents a deep learning (DL) framework to estimate the 3D subsurface permeability from time-lapse ERT data. To test the feasibility of the proposed framework, we train DL-enabled inverse models on simulation data. Each measurement in both synthetic and field data is standardized by removing the mean and scaling the time-series to unit variance. This pre-processing step is necessary to bring simulation data closer to field observations. Subsurface process models based on hydrogeophysics are used to generate this synthetic data. Training performed on limited simulation data resulted in the DL model over-fitting. An advanced data augmentation based on mixup is implemented to generate additional training samples to overcome this issue. This mixup technique creates weakly labeled (low-fidelity) samples from strongly labeled (high-fidelity) data. The weakly labeled training data is then used to develop DL-enabled inverse models and reduce over-fitting. As both time-lapse ERT (1133048 features/realization) and 3D permeability (585453 features/realization) data samples are from a high-dimensional space, principal component analysis (PCA) is employed to reduce dimensionality. Encoded ERT and encoded permeability are generated using the trained PCA estimators. A deep neural network is then trained to map the encoded ERT to encoded permeability. This mixup training and unsupervised learning allowed us to build a fast and reasonably accurate DL-based inverse model under limited simulation data. Results show that proposed weak supervised learning can capture salient spatial features in the 3D permeability field. Quantitatively, the average mean squared error (in terms of the natural log) on the strongly labeled training, validation, and test datasets is less than 0.5. The R 2 -score (global metric) is greater than 0.75, and the percent error in each cell (local metric) is less than 10%. Finally, an added benefit in terms of computational cost is that the proposed DL-based inverse model is at least O(10 4 ) times faster than running a forward model once it is trained. Data generation, DL model training, and hyperparameter tuning to identify optimal neural network architectures utilized high-performance computing resources while the DL inference is performed on a standard laptop. Approximately, O(10 5 ) processor hours are used for generating data and DL tuning and training. We acknowledge that the data generation and DL model development are expensive. But once a DL model is trained, it can be re-used for inversion rapidly for the given system, with set physics and domain. Note that traditional inversion may require multiple forward model simulations (e.g., in the order of 10 to 1000), which are very expensive. This computational savings ≈ O(10 5 ) – O(10 7 )) makes the proposed DL-based inverse model attractive for subsurface imaging and real-time ERT monitoring applications due to fast and yet reasonably accurate estimations of permeability field.

58 GEOSCIENCES↗
NASA NTRS1988

TRAPEDS: Producing traces for multicomputers via execution-driven simulation

Trace-driven simulation is an important aid in performance analysis of computer systems. Capturing address traces for these simulations is a difficult problem for single processors and particularly for multicomputers. Even when existing trace methods can be used on multicomputers, the amount of collected data typically grows with the number of processors, so I/O and trace storage costs increase. A new technique is presented which modifies the executable code to dynamically collect the address trace from the user code and analyzes this trace during the execution of the program. This method helps resolve the I/O and storage problems and facilitates parallel analysis of the address trace. If a trace stored on disk is desired, the generated trace information can also be written to files during execution, with a resultant drop in program execution speed. An initial implementation on the Intel iPSC/2 hypercube multicomputer is detailed, and sample simulation results are presented. The effect of this trace collection method on execution time is illustrated.

Stunkel, Craig B.↗