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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS2006

On-wafer vector network analyzer measurements in the 220-325 Ghz frequency band

We report on a full two-port on-wafer vector network analyzer test set for the 220-325 GHz (WR3) frequency band. The test set utilizes Oleson Microwave Labs frequency extenders with the Agilent 8510C network analyzer. Two port on-wafer measurements are made with GGB Industries coplanar waveguide (CPW) probes. With this test set we have measured the WR3 band S-parameters of amplifiers on-wafer, and the characteristics of the CPW wafer probes. Results for a three stage InP HEMT amplifier show 10 dB gain at 235 GHz [1], and that of a single stage amplifier, 2.9 dB gain at 231 GHz. The approximate upper limit of loss per CPW probe range from 3.0 to 4.8 dB across the WR3 frequency band.

coplanar waveguides↗
NASA NTRS2009

Silicon Wafer-Scale Substrate for Microshutters and Detector Arrays

The silicon substrate carrier was created so that a large-area array (in this case 62,000+ elements of a microshutter array) and a variety of discrete passive and active devices could be mounted on a single board, similar to a printed circuit board. However, the density and number of interconnects far exceeds the capabilities of printed circuit board technology. To overcome this hurdle, a method was developed to fabricate this carrier out of silicon and implement silicon integrated circuit (IC) technology. This method achieves a large number of high-density metal interconnects; a 100-percent yield over a 6-in. (approximately equal to 15-cm) diameter wafer (one unit per wafer); a rigid, thermally compatible structure (all components and operating conditions) to cryogenic temperatures; re-workability and component replaceability, if required; and the ability to precisely cut large-area holes through the substrate. A method that would employ indium bump technology along with wafer-scale integration onto a silicon carrier was also developed. By establishing a silicon-based version of a printed circuit board, the objectives could be met with one solution. The silicon substrate would be 2 mm thick to survive the environmental loads of a launch. More than 2,300 metal traces and over 1,500 individual wire bonds are required. To mate the microshutter array to the silicon substrate, more than 10,000 indium bumps are required. A window was cut in the substrate to allow the light signal to pass through the substrate and reach the microshutter array. The substrate was also the receptacle for multiple unpackaged IC die wire-bonded directly to the substrate (thus conserving space over conventionally packaged die). Unique features of this technology include the implementation of a 2-mmthick silicon wafer to withstand extreme mechanical loads (from a rocket launch); integrated polysilicon resistor heaters directly on the substrate; the precise formation of an open aperture (approximately equal to 3x3cm) without any crack propagation; implementation of IR transmission blocking techniques; and compatibility with indium bump bonding. Although designed for the microshutter arrays for the NIRSpec instrument on the James Webb Space Telescope, these substrates can be linked to microshutter applications in the photomask generation and stepper equipment used to make ICs and microelectromechanical system (MEMS) devices.

Jhabvala, Murzy↗
NASA NTRS2011

On-Wafer S-Parameter Measurements in the 325-508-GHz Band

New circuits have been designed and fabricated with operating frequencies over 325 GHz. In order to measure S-parameters of these circuits, an extensive process of wafer dicing and packaging, and waveguide transition design, fabrication, and packaging would be required. This is a costly and time-consuming process before the circuit can be tested in waveguide. The new probes and calibration procedures will simplify the testing process. New on-wafer probes, and a procedure for their calibration, have been developed that allow fast and inexpensive S-parameter characterization of circuits in the 325 -508 -GHz frequency band. The on-wafer probes transition from rectangular waveguide to coplanar waveguide probe tips with 40- m nominal signal-to-ground pin pitch so as to allow for probing circuits on a wafer. The probes with bias tees have been optimized for minimal insertion loss and maximum return loss when placed on 50-ohm structures to allow for calibration. The calibration process has been developed using the Thru-Reflect-Line Agilent algorithm with JPL determined calibration structures and calibration coefficients for the algorithm. This new test capability is presently unique to JPL. With it, researchers will be able to better develop circuits such as low-noise amplifiers, power amplifiers, multipliers, and mixers for heterodyne receivers in the 325-508-GHz frequency band for remote sensing/spectroscopy.

Fung, King Man↗
DOE OSTI2022

Multiplication of freestanding III-V semiconductor membranes from a single wafer by alternating growth with amorphous graphene interlayer

Freestanding single-crystalline III-V compound semiconductors are important building blocks for functional devices due to their high electron mobilities, a wide range of bandgaps, and excellent optoelectronic properties. Despite efforts to produce such membranes by detaching epitaxial layers from donor wafers, current methods suffer from either slow processes or poor material quality. Here, we demonstrate a technique to grow and harvest multiple epitaxial membranes with extremely high throughput at the wafer scale. For this, a process to directly grow amorphous graphene on III-V substrates in metal-organic chemical vapor deposition reactors is developed, which enables an advanced remote epitaxy scheme comprised of multiple alternating layers of amorphous graphene and III-V epitaxial layers that can be formed by a single epitaxy run. Each epilayer in the multi-stack structure is then harvested by layer-by-layer peeling, producing multiple freestanding membranes with unprecedented throughput from a single wafer. Because amorphous graphene provides a weak van der Waals interface that allows peeling at the interface without damaging the epilayer or the substrate, wafers can be reused for subsequent membrane production. Therefore, this work represents a meaningful step toward high-throughput and low-cost production of single-crystal membranes that can be heterointegrated.

Han, Ne Myo↗
DOE OSTI2024

Trap Passivation for Reducing On-Resistance and Saturation Voltage in Wafer-Bonded InGaAs-Channel/GaN-Drain Vertical FETs

High frequency and high power are the driving forces behind semiconductor transistor technology. However, conventional devices have the tradeoff of either being high speed or high breakdown—but not both. Wafer-bonded current aperture vertical electron transistors (BAVETs) help eliminate the tradeoff by combining a high-speed III-As channel to a high-breakdown III-N drift region. The device presented herein comprises of an InAlAs gate-barrier/InGaAs channel, wafer-bonded to an InGaN/GaN drift region, with the InGaAs/InGaN interface referred to as the wafer-bonded interface (WBI). The electronic behavior of WBIs is yet less known but necessary in realizing the potential of a BAVET. Herein, strong trap activity at the WBI is shown to be the cause of abnormally high saturation voltage ( V DS_SAT ) in BAVETs. The traps cause unintentional space charge (SC) region in the drain region of the device. This causes a drain resistance, a higher ON-resistance ( R ON ), and a higher V DS_SAT . Here, the challenge is overcome by hydrogen passivation of traps at WBI by using a p-doping for the InAlAs layer, which reduces the trap-charge concentration at the WBI. Consequently, the width of the SC region is reduced and a reduction in V DS_SAT is demonstrated, wherein it reduces from >12 to 5 V.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Nanosecond Laser Drying in Wafer Foundries for Significant Energy Efficiency Improvement

Surface drying is a critical process in microelectronics wafer fabrication. In order to reduce and eliminate watermarks, many surface drying processes have been studied and used. Most of the wafer foundries currently use drying processes based on Isopropyl Alcohol (IPA), which causes serious safety (fire), health, environmental, and energy efficiency issues. The long-term goal of this project is to develop a fast, effective, chemical-free, and extremely energy efficient wafer drying technology that employs nanosecond laser-induced sub-surface evaporation and explosion. The objectives of this project are to 1) experimentally develop and verify the laser surface drying method, explore and identify how and to what extent various physical parameters influence the drying efficiency and effectiveness; and 2) understand and optimize the underlying thermodynamics in the proposed laser surface drying, including micro/nanoscale sub-surface superheating, evaporation, explosion, and photo/thermochemical bond breaking via atomistic modeling and experimental characterization. Toward these objectives, five tasks have been accomplished successfully, including 1) develop in-lab laser surface drying setup and study the effect of varied laser parameters, 2) use multiscale hybrid-modeling to study and understand the physics of water behavior during drying toward process optimization, 3) investigate the effect of drying conditions on the drying effectiveness, 4) develop a large-scale laser drying scanning system with automatic scanning, and 5) conduct large-scale simulation to study the effect of dopant level and develop strategies for system development toward industry deployment.

42 ENGINEERING↗
DOE OSTI2025

Hexagonal Boron Nitride: Physical Properties, Hydride Vapor‐Phase Epitaxy Growth of Large‐Diameter Quasi‐Bulk Wafers and Applications

Hexagonal boron nitride ( h ‐BN), with its ultrawide bandgap and 2D structure, holds an immense promise for advanced semiconductor applications. Scaling bulk crystals to large‐diameter wafers, crucial for complex device fabrication, remains a challenge with high temperature, high pressure, and metal flux solution methods. To address this, recent efforts have focused on hydride vapor‐phase epitaxy (HVPE) for producing large diameter thick h ‐BN quasi‐bulk wafers, reaching hundreds of micrometers. These HVPE‐grown quasi‐bulk crystals exhibit excellent c ‐axis long‐range order. Notably, the in‐plane mobility‐lifetime products for both electrons and holes surpass 10 −4 cm 2 V −1 , which are two orders of magnitude greater than the out‐of‐plane (vertical) values, highlighting the potential for high‐performance devices leveraging superior lateral transport. Lateral detectors fabricated from 100 μm thick B‐10 enriched h‐ BN wafers have achieved a record 60% thermal neutron detection efficiency. Based on its physical properties, h‐ BN appears to be an outstanding material of choice for light‐triggered electronic power switches capable of supporting high ‐ voltage and high ‐ power operations. These recent advancements in large‐diameter h ‐BN quasi‐bulk crystal growth, enabled by HVPE, pave the way for applications spanning deep UV photonics, high‐power electronics, high‐efficiency neutron detection, and quantum information technologies, establishing h ‐BN as both a versatile active semiconductor and an ideal substrate.

Jiang, Hongxing [Department of Electrical and Comp↗
DOE OSTI2020

Sub-micrometer random-pyramid texturing of silicon solar wafers with excellent surface passivation and low reflectance

Select emerging solar cell technologies, ranging from very narrow screen-printed fingers to perovskite/silicon tandems, would benefit from a reduction of the height of the standard pyramidal texture of monocrystalline silicon wafers to below 1 μm. However, fabricating such small surface features usually compromises the requisite low reflectance and high passivation quality. Through systematic design of experiments, we demonstrate that conventional alkaline-based wet-chemical etching processes can be tuned to produce dense, spatially homogeneous, and uniformly sized sub-micrometer pyramids. Precise texture size can be further controlled by adding potassium silicate to the texturing solution to effectively slow the pyramid growth rate and promote nucleation. With pyramid size distribution data—extracted from multiple atomic force microscopy images across each wafer—we demonstrate 16 nanotextures with average pyramid sizes ranging from 62 to 512 nm, with the largest having only 0.3% of its pyramids taller than 1 μm. Six of the nanotextures exhibit light trapping and surface defect densities comparable to state-of-the-art microtextured wafers. In conclusion, the best nanotexture achieved an AM1.5G-weighted reflectance of 11.8% and a minority-carrier lifetime of 3.4 ms after passivation with amorphous silicon, demonstrating that smaller textures need not deteriorate solar cell performance.

14 SOLAR ENERGY↗
DOE OSTI2025

Broadband unidirectional visible imaging using wafer-scale nano-fabrication of multi-layer diffractive optical processors

We present a broadband and polarization-insensitive unidirectional imager that operates at the visible part of the spectrum, where image formation occurs in one direction, while in the opposite direction, it is blocked. This approach is enabled by deep learning-driven diffractive optical design with wafer-scale nano-fabrication using high-purity fused silica to ensure optical transparency and thermal stability. Our design achieves unidirectional imaging across three visible wavelengths (covering red, green, and blue parts of the spectrum), and we experimentally validated this broadband unidirectional imager by creating high-fidelity images in the forward direction and generating weak, distorted output patterns in the backward direction, in alignment with our numerical simulations. This work demonstrates wafer-scale production of diffractive optical processors, featuring 16 levels of nanoscale phase features distributed across two axially aligned diffractive layers for visible unidirectional imaging. This approach facilitates mass-scale production of ~0.5 billion nanoscale phase features per wafer, supporting high-throughput manufacturing of hundreds to thousands of multi-layer diffractive processors suitable for large apertures and parallel processing of multiple tasks. Beyond broadband unidirectional imaging in the visible spectrum, this study establishes a pathway for artificial-intelligence-enabled diffractive optics with versatile applications, signaling a new era in optical device functionality with industrial-level, massively scalable fabrication.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Role of humidity and surface roughness on direct wafer bonding

Bodies made from elastically stiff material usually bind very weakly unless the surfaces are flat and extremely smooth. In direct wafer bonding flat surfaces bind by capillary bridges and by the van der Waals interaction, which act between all solid objects. Here we study the dependency of the work of adhesion on the humidity and surface roughness in hydrophilic direct wafer bonding. We show that the long-wavelength roughness (usually denoted waviness) has a negligible influence on the strength of wafer bonding (the work of adhesion) from the menisci that form from capillary condensation of water vapor.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2021

High-Efficiency, Low-Cost III-V Solar Cells by Dynamic Hydride Vapor Phase Epitaxy Coupled with Rapid, Polishing-Free Wafer Reuse through Orientation-Optimized (110) Spalling

We demonstrated (110) GaAs solar cells grown by D-HVPE with equivalent performance and material quality relative to (100) devices. Also, we developed a procedure for repeatable wafer-scale spalling of (110) GaAs. Spalled surfaces were free of the facets founds in (100) GaAs spalling, the large arrest lines found in (100) Ge spalling, and surface features greater than 3 µm in peak-to-valley height, which can otherwise degrade the efficiency of regrown III-V devices. A sub-µm step-terrace morphology was discovered on the post-spall wafer surface, resulting from the restricted cleavage system of GaAs, but we developed understanding of the factors that determine the resulting morphology, enabling ample opportunity for optimization of morphologies suitable for device growth and spall depth waste minimization on (110) GaAs. Lastly, we demonstrated a device grown on a previously spalled surface with only 8% relative efficiency difference to a cell grown on a new unspalled wafer. Significant optimization of the substrate regrowth conditions are required to enable higher efficiency, but these results highlight the promise of (110)-oriented devices coupled with substrate reuse by spalling as a pathway for low-cost III-V photovoltaics.

14 SOLAR ENERGY↗
DOE OSTI2020

Dielectrophoresis-Based Positioning of Carbon Nanotubes for Wafer-Scale Fabrication of Carbon Nanotube Devices

In this paper, we report the wafer-scale fabrication of carbon nanotube field-effect transistors (CNTFETs) with the dielectrophoresis (DEP) method. Semiconducting carbon nanotubes (CNTs) were positioned as the active channel material in the fabrication of carbon nanotube field-effect transistors (CNTFETs) with dielectrophoresis (DEP). The drain-source current (IDS) was measured as a function of the drain-source voltage (VDS) and gate-source voltage (VGS) from each CNTFET on the fabricated wafer. The IDS on/off ratio was derived for each CNTFET. It was found that 87% of the fabricated CNTFETs was functional, and that among the functional CNTFETs, 30% of the CNTFETs had an IDS on/off ratio larger than 20 while 70% of the CNTFETs had an IDS on/off ratio lower than 20. The highest IDS on/off ratio was about 490. The DEP-based positioning of carbon nanotubes is simple and effective, and the DEP-based device fabrication steps are compatible with Si technology processes and could lead to the wafer-scale fabrication of CNT electronic devices.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2020

Multi-Level Information Storage Using Engineered Electromechanical Resonances of Piezoelectric Wafers: A Concept Piezoelectric Quick Response (PQR) Code

A piezoelectric-based method for information storage is presented. It involves engineering the polarization profiles of multiple piezoelectric wafers to enhance/suppress specific electromechanical resonances. These enhanced/suppressed resonances can be used to represent multiple frequency-dependent bits, thus enabling multi-level information storage. This multi-level information storage is demonstrated by achieving three information states for a ternary encoding. Using the three information states, we present an approach to encode and decode information from a 2-by-3 array of piezoelectric wafers that we refer to as a concept Piezoelectric Quick Response (PQR) code. The scaling relation between the number of wafers used and the cumulative number of information states that can be achieved with the proposed methodology is briefly discussed. Potential applications of this methodology include tamper-evident devices, embedded product tags in manufacturing/inventory tracking, and additional layers of security with existing information storage technologies.

47 OTHER INSTRUMENTATION↗
NASA NTRS1978

Silicon crystals: Process for manufacturing wafer-like silicon crystals with a columnar structure

Wafer-like crystals suitable for making solar cells are formed by pouring molten Si containing suitable dopants into a mold of the desired shape and allowing it to solidify in a temperature gradient, whereby the large surface of the melt in contact with the mold is kept at less than 200 D and the free surface is kept at a temperature of 200-1000 D higher, but below the melting point of Si. The mold can also be made in the form of a slit, whereby the 2 sides of the mold are kept at different temperatures. A mold was milled in the surface of a cylindrical graphite block 200 mm in diameter. The granite block was induction heated and the bottom of the mold was cooled by means of a water-cooled Cu plate, so that the surface of the mold in contact with one of the largest surfaces of the melt was held at approximately 800 D. The free surface of the melt was subjected to thermal radiation from a graphite plate located 2 mm from the surface and heated to 1500 D. The Si crystal formed after slow cooling to room temperature had a columnar structure and was cut with a diamond saw into wafers approximately 500 mm thick. Solar cells prepared from these wafers had efficiencies of 10 to 11%.

Authier, B.↗
NASA NTRS1979

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

Jones, G. T.↗
NASA NTRS1980

Development of megasonic cleaning for silicon wafers

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Mayer, A.↗