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At least 73 records · Page 4

A study of charged particles/radiation damage to VLSI device materials

Future spacecraft systems such as the manned space station will be subjected to low-dose long term radiation particles. Most electronic systems are affected by such particles. There is therefore a great need to understand device physics and failure mechanisms affected by radiation and to design circuits that would be less susceptible to radiation. Using 2 MeV electron radiation and bias temperature aging, it was found that MOS capacitors that were prepositively biased have lower flatband voltage shift and lesser increase in density of surface state charge than those that were not prepositively biased. In addition, it was shown that there is continued recovery of flatband voltage and density of state charge in irradiated capacitors during both room temperature anneal and 137 degree anneal. When nMOS transistors were subjected to 1 MeV proton radiation, charge pumping and current versus voltage measurements indicated that transconductance degradation, threshold voltage shifts and changes in interface states density may be the primary cause of nMOS transistor failure after radiation. Simulation studies using SPICE were performed on CMOS SRAM cells of various transistor sizes. It is shown that transistor sizing affects the noise margins of CMOS SRAM cells, and that as the beta ratio of the transistors of the CMOS SRAM cell decreases, the effective noise margin of the SRAM cell increases. Some suggestions were made in connection with the design of CMOS SRAMS that are hardened against single event upsets.

Okyere, John G.↗

On Possible Arc Inception on Low Voltage Solar Array

Recent analysis of spacecraft failures during the period of 1990-2013 demonstrated clearly that electrostatic discharges caused more than 8 of all registered failures and anomalies, and comprised the most costly losses (25) for operating companies and agencies. The electrostatic discharges on spacecraft surfaces are the results of differential charging above some critical (threshold) voltages. The mechanisms of differential charging are well known, and various methods have been developed to prevent a generation of significant electric fields in areas of triple junctions. For example, low bus voltages in Low Earth Orbit plasma environment and slightly conducting layer over coverglass (ITO) in Geosynchronous Orbit surroundings are believed to be quite reliable measures to prevent discharges on respective surfaces. In most cases, the vulnerable elements of spacecraft (solar arrays, diode boards, etc.) go through comprehensive ground tests in vacuum chambers. However, tests articles contain the miniscule fragments of spacecraft components such as 10-30 solar cells of many thousands deployed on spacecraft in orbit. This is one reason why manufacturing defects may not be revealed in ground tests but expose themselves in arcing on array surface in space. The other reason for ineffectiveness of discharge preventive measures is aging of all materials in harsh orbital environments. The expected life time of modern spacecraft varies within the range of five-fifteen years, and thermal cycling, radiation damages, and mechanical stresses can result in surface erosion on conductive layers and microscopic cracks in coverglass sheets and adhesive films. These possible damages may cause significant increases in local electric field strengths and subsequent discharges. The primary discharges may or may not be detrimental to spacecraft operation, but they can produce the necessary conditions for sustained arcs initiation. Multiple measures were developed to prevent sustained discharges between adjacent strings, and many ground tests were performed to determine threshold parameters (voltage and current) for sustained arcs. And again, manufacturing defects and aging in space environments may result in considerable decrease of critical threshold parameters. This paper is devoted to the analysis of possible reasons behind arcing on spacecraft with low bus voltages.

plasma interaction↗

On Possible Arc Inception on Low Voltage Solar Array

Recent analysis of spacecraft failures during the period of 1990-2013 demonstrated clearly that electrostatic discharges caused more than 8 percent of all registered failures and anomalies, and comprised the most costly losses (25 percent) for operating companies and agencies. The electrostatic discharges on spacecraft surfaces are the results of differential charging above some critical (threshold) voltages. The mechanisms of differential charging are well known, and various methods have been developed to prevent a generation of significant electric fields in areas of triple junctions. For example, low bus voltages in Low Earth Orbit plasma environment and slightly conducting layer over cover-glass (ITO) in Geosynchronous Orbit surroundings are believed to be quite reliable measures to prevent discharges on respective surfaces. In most cases, the vulnerable elements of spacecraft (solar arrays, diode boards, etc.) go through comprehensive ground tests in vacuum chambers. However, tests articles contain the miniscule fragments of spacecraft components such as 10-30 solar cells of many thousands deployed on spacecraft in orbit. This is one reason why manufacturing defects may not be revealed in ground tests but expose themselves in arcing on array surface in space. The other reason for ineffectiveness of discharge preventive measures is aging of all materials in harsh orbital environments. The expected life time of modern spacecraft varies within the range of five-fifteen years, and thermal cycling, radiation damages, and mechanical stresses can result in surface erosion on conductive layers and microscopic cracks in cover-glass sheets and adhesive films. These possible damages may cause significant increases in local electric field strengths and subsequent discharges. The primary discharges may or may not be detrimental to spacecraft operation, but they can produce the necessary conditions for sustained arcs initiation. Multiple measures were developed to prevent sustained discharges between adjacent strings, and many ground tests were performed to determine threshold parameters (voltage and current) for sustained arcs. And again, manufacturing defects and aging in space environments may result in considerable decrease of critical threshold parameters. This paper is devoted to the analysis of possible reasons behind arcing on spacecraft with low bus voltages.

low voltage solar array↗

Design, production, and testing of field effect transistors

Cryogenic MOSFETS (CRYOFETS), specifically designed for low temperature preamplifier application with infrared extrinsic detectors were produced and comparatively tested with p-channel MOSFETs under matched conditions. The CRYOFETs exhibit lower voltage thresholds, high source-follower gains at lower bias voltage, and lower dc offset source voltage. The noise of the CRYOFET is found to be 2 to 4 times greater than the MOSFET with a correspondingly lower figure of merit (which is established for source-follower amplifiers). The device power dissipation at a gain of 0.98 is some two orders of magnitude lower than for the MOSFET. Further, CRYOFETs are free of low temperature I vs V character hysteresis and balky conduction turn-on effects and operate effectively in the 2.4 to 20 K range. These devices have promise for use on long term duration sensor missions and for on-focal-plane signal processing at low temperatures.

Sclar, N.↗

Response of a metal-oxide-semiconductor field-effect transistor to a cosmic-ray ion track

A cosmic-ray ion track passing perpendicularly through the oxide layer of an enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET) forms a conducting path, the resistance of which is proportional to the stopping power of the cosmic ion and independent of the cross-sectional area of the ion track. The voltage across the oxide capacitance may drop below the threshold voltage if the gate bias is sufficiently low or if the external resistance in the gate-source circuit is sufficiently high. The first of a pair of MOSFETs forming a flip-flop circuit may thus be turned off, and the second transitor may turn on, providing it has a sufficiently short delay time, thereby completing a single-event upset.

Benumof, Reuben↗

High-Voltage Switch Containing (DI)2 Devices

Series switching diodes triggered on by passing above threshold voltage. High-voltage switch made by connecting multitude of deep-impurity, double-injection devices in series with each other and with another, triggerable high-voltage device such as thyristor. Device operates near ground potential to avoid insulation problems in triggering circuit.

Hanes, Maurice H.↗

Measuring Input Thresholds on an Existing Board

A critical PECL (positive emitter-coupled logic) interface to Xilinx interface needed to be changed on an existing flight board. The new Xilinx input interface used a CMOS (complementary metal-oxide semiconductor) type of input, and the driver could meet its thresholds typically, but not in worst-case, according to the data sheet. The previous interface had been based on comparison with an external reference, but the CMOS input is based on comparison with an internal divider from the power supply. A way to measure what the exact input threshold was for this device for 64 inputs on a flight board was needed. The measurement technique allowed an accurate measurement of the voltage required to switch a Xilinx input from high to low for each of the 64 lines, while only probing two of them. Directly driving an external voltage was considered too risky, and tests done on any other unit could not be used to qualify the flight board. The two lines directly probed gave an absolute voltage threshold calibration, while data collected on the remaining 62 lines without probing gave relative measurements that could be used to identify any outliers. The PECL interface was forced to a long-period square wave by driving a saturated square wave into the ADC (analog to digital converter). The active pull-down circuit was turned off, causing each line to rise rapidly and fall slowly according to the input s weak pull-down circuitry. The fall time shows up as a change in the pulse width of the signal ready by the Xilinx. This change in pulse width is a function of capacitance, pulldown current, and input threshold. Capacitance was known from the different trace lengths, plus a gate input capacitance, which is the same for all inputs. The pull-down current is the same for all inputs including the two that are probed directly. The data was combined, and the Excel solver tool was used to find input thresholds for the 62 lines. This was repeated over different supply voltages and temperatures to show that the interface had voltage margin under all worst case conditions. Gate input thresholds are normally measured at the manufacturer when the device is on a chip tester. A key function of this machine was duplicated on an existing flight board with no modifications to the nets to be tested, with the exception of changes in the FPGA program.

Kuperman, Igor↗

Digitally controlled pulse-level discriminator operates over wide voltage range

Low power drain discriminator circuit generates an output pulse when an input pulse exceeds a discrete digitally controlled threshold voltage. The discriminator operates over a wide linear or nonlinear range of threshold levels. It uses several amplifier stages ahead of a fixed-reference threshold detector.

Cancro, C. A.↗

A tunable CMOS constant current source

A constant current source has been designed which makes use of on chip electrically erasable memory to adjust the magnitude and temperature coefficient of the output current. The current source includes a voltage reference based on the difference between enhancement and depletion transistor threshold voltages. Accuracy is +/- 3% over the full range of power supply, process variations, and temperature using eight bits for tuning.

Thelen, D.↗

Neutron and gamma irradiation effects on power semiconductor switches

The performance characteristics of high power semiconductor switches subjected to high levels of neutron fluence and gamma dose must be known by the designer of the power conditioning, control and transmission subsystem of space nuclear power systems. Location and the allowable shielding mass budget will determine the level of radiation tolerance required by the switches to meet performance and reliability requirements. Neutron and gamma ray interactions with semiconductor materials and how these interactions affect the electrical and switching characteristics of solid state power switches is discussed. The experimental measurement system and radiation facilities are described. Experimental data showing the effects of neutron and gamma irradiation on the performance characteristics are given for power-type NPN Bipolar Junction Transistors (BJTs), and Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs). BJTs show a rapid decrease in gain, blocking voltage, and storage time for neutron irradiation, and MOSFETs show a rapid decrease in the gate threshold voltage for gamma irradiation.

Schwarze, G. E.↗

Neutron and gamma irradiation effects on power semiconductor switches

The performance characteristics of high-power semiconductor switches subjected to high levels of neutron fluence and gamma dose must be known by the designer of the power conditioning, control and transmission subsystem of space nuclear power systems. Location and the allowable shielding mass budget will determine the level of radiation tolerance required by the switches to meet performance and reliability requirements. Neutron and gamma ray interactions with semiconductor materials and how these interactions affect the electrical and switching characteristics of solid state power switches is discussed. The experimental measurement system and radiation facilities are described. Experimental data showing the effects of neutron and gamma irradiation on the performance characteristics are given for power-type NPN Bipolar Junction Transistors (BJTs), and Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs). BJTs show a rapid decrease in gain, blocking voltage, and storage time for neutron irradiation, and MOSFETs show a rapid decrease in the gate threshold voltage for gamma irradiation.

Schwarze, G. E.↗

Addressable inverter matrix for process and device characterization

The addressable inverter matrix consists of 222 inverters each accessible with the aid of a shift register. The structure has proven useful in characterizing the variability of inverter transfer curves and in diagnosing processing faults. For good 3-micron CMOS bulk inverters investigated, the percent standard deviation of the inverter threshold voltage was less than one percent and the inverter gain (the slope of the inverter transfer curve at the inverter threshold vltage) was less than 3 percent. The average noise margin for the inverters was near 2 volts for a power supply voltage of 5 volts. The specific faults studied included undersize pull-down transistor widths and various open contacts in the matrix.

Buehler, M. G.↗

Broad beam ion source operation with four common gases

A Kaufman-type broad beam ion source, used for sputtering and etching purposes, has been operated with Ar, Kr, O2 and N2 gas inputs over a wide range of beam energies (200-1200 eV) and gas flow rates (1-10 sccm). The maximum ion beam current density for each gas saturates at about 2.5 mA/sq cm as gas flow is increased. The discharge threshold voltage necessary to produce a beam and the beam efficiency (beam current/molecular current), however, varied considerably. Kr had the lowest threshold and highest efficiency, Ar next, then N2 and O2. The ion beam current varied only weakly with beam energy for low gas flow rates, but showed a factor of two increase when the gas flow was higher.

Pak, S.↗

An Active Substrate Driver for Enabling Mixed-Voltage SOI Systems-On-A-Chip

The current trend for space application systems is towards fully integrated systems-on-a-chip. To facilitate this drive, high-voltage transistors must reside on the same substrate as low-voltage transistors. These systems must also be radiation tolerant, particularly for space missions such as the Europa Lander and Titan Explorer. SOI CMOS technology offers high levels of radiation hardness. As a result, a high-voltage lateral MOSFET has been developed in a partially-depleted (PD) SOI technology. Utilizing high voltages causes a parasitic transistor to have non-negligible effects on a circuit. Several circuit architectures have been used to compensate for the radiation induced threshold voltage shift of the parasitic back-channel transistor. However, a new architecture for high-voltage systems must be employed to bias the substrate to voltage levels insuring all parasitic transistors remain off. An active substrate driver has been developed to accomplish task. Additional information is contained in the original extended abstract.

Jackson, S. A.↗

Simulation-based Study of Single-Event Burnout in 4H-SiC High-Voltage Vertical Superjunction DMOSFET: Physical Failure Mechanism and Robustness vs. Performance Tradeoffs

We explore and elucidate physical failure mechanisms in a 4H-SiC, high voltage, superjunction (SJ) vertical DMOSFET from a single heavy ion strike using three-dimensional electro-thermal transient simulations. The single-event burnout (SEB) failure is thermal runaway from second breakdown, initiated by impact ionization and terminated with mesoplasma formation, at the center of the P-pillar/N+ substrate interface. We also demonstrate that the SEB performance of this SiC SJ DMOSFET is insensitive to the pillar width but sensitive to the strike location with ion strike at the P-pillar causing SEB at a lower blocking voltage than at the N-pillar. Compared to commercially available 1.2 kV blocking-rated non-SJ DMOSFETs, which have been demonstrated to survive SEB up to 525 V, the SJ DMOSFET increases SEB survival threshold voltage (VSEB) by a factor of 2.2, making it close to 1200 V, while the on-resistance is increased by only 11%. Using our recently developed figure of merit (FoM), which considers the trade-off between VSEB and on-state performance, we find that the SiC SJ DMOSFET achieves a FoM that is 14 times better, making it superior to conventional 1.2 kV SiC DMOSFETs for long-term radiation-tolerant operation in space applications.

Silicon Carbide↗

Arcing and discharges in high-voltage subsystems of Space Station

Arcing and other types of electrical discharges are likely to occur in high-voltage subsystems of the Space Station. Results from ground and space experiments on the arcing of solar cell arrays are briefly reviewed, showing that the arcing occurs when the conducting interconnects in the arrays are at negative potential above a threshold, which decreases with the increasing plasma density. Furthermore, above the threshold voltages the arcing rate increases with the plasma density. At the expected operating voltages (approximately 200 V) in the solar array for the space station, arcing is expected to occur even in the ambient ionospheric plasma. If the ionization of the contaminants increases the plasma density near the high-voltage systems, the adverse effects of arcing on the solar arrays and the space station are likely to be enhanced, In addition to arcing other discharge processes are likely to occur in high-voltage subsystems. For example, Paschen discharge is likely to occur when the neutral density N sub n greater that 10 to the 12th cu cm, the corresponding neutral pressure P greater than 3 x 10 to the -5 Torr.

Singh, N.↗