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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Study on fault-tolerant processors for advanced launch system

Issues related to the reliability of a redundant system with large main memory are addressed. The Fault-Tolerant Processor (FTP) for the Advanced Launch System (ALS) is used as a basis for the presentation. When the system is free of latent faults, the probability of system crash due to multiple channel faults is shown to be insignificant even when voting on the outputs of computing channels is infrequent. Using channel error maskers (CEMs) is shown to improve reliability more effectively than increasing redundancy or the number of channels for applications with long mission times. Even without using a voter, most memory errors can be immediately corrected by those CEMs implemented with conventional coding techniques. In addition to their ability to enhance system reliability, CEMs (with a very low hardware overhead) can be used to dramatically reduce not only the need of memory realignment, but also the time required to realign channel memories in case, albeit rare, such a need arises. Using CEMs, two different schemes were developed to solve the memory realignment problem. In both schemes, most errors are corrected by CEMs, and the remaining errors are masked by a voter.

Shin, Kang G.↗
NASA NTRS1972

Plated wire memory subsystem

The work performed entailed the design, development, construction and testing of a 4000 word by 18 bit random access, NDRO plated wire memory for use in conjunction with a spacecraft imput/output unit and central processing unit. The primary design parameters, in order of importance, were high reliability, low power, volume and weight. A single memory unit, referred to as a qualification model, was delivered.

Reynolds, L.↗
NASA NTRS1996

Smart Material Demonstrators Based on Shape Memory Alloys and Electroceramics

This paper describes the development and characterization of two technology demonstrators that were produced under the auspices of an ARPA sponsored smart materials synthesis and processing effort. The ARPA Smart Materials and Synthesis (SMS) Program was a 2 year, $10M partnership led by Martin Marietta Laboratories - Baltimore and included Lockheed Missiles & Space Co., NRL, AVX Corp., Martin Marietta Astronautics Groups, BDM Federal, Inc., Virginia Tech, Clemson, University of Maryland, Denver University, and The Johns Hopkins University. In order to demonstrate the usefulness of magnetron sputtered shape memory foil and the manufacturability of reliable, reproducible electrostrictive actuators, the team designed a broadband active vibration cancellation device for suppressing the vibration load on delicate instruments and precision pointing devices mounted on orbiting satellites and spacecraft. The results of extensive device characterization and bench testing are discussed. Initial simulation results show excellent control authority and amplitude attenuation over the range of anticipated disturbance frequencies. The SMS Team has also developed an active 1-3 composite comprising micro-electrostrictive actuators embedded in a polymeric matrix suitable for underwater applications such as sonar quieting and listening arrays, and for medical imaging. Follow-on programs employing these technologies are also described.

Cooke, Arther V.↗
NASA NTRS2002

Evaluation of Data Retention and Imprint Characteristics of FRAMs Under Environmental Stresses for NASA Applications

A major reliability issue for all advanced nonvolatile memory (NVM) technology devices including FRAMs is the data retention characteristics over extended period of time, under environmental stresses and exposure to total ionizing dose (TID) radiation effects. For this testing, 256 Kb FRAMs in 28-pin plastic DIPS, rated for industrial grade temperature range of -40 C to +85 C, were procured. These are two-transistor, two-capacitor (2T-2C) design FRAMs. In addition to data retention characteristics, the parts were also evaluated for imprint failures, which are defined as the failure of cells to change from a "preferred" state, where it has been for a significant period of time to an opposite state (e.g., from 1 to 0, or 0 to 1). These 256 K FRAMs were subjected to scanning acoustic microscopy (C-SAM); 1,000 temperature cycles from -65 C to +150 C; high temperature aging at 150 C, 175 C, and 200 C for 1,000 hours; highly accelerated stress test (HAST) for 500 hours; 1,000 hours of operational life test at 125 C; and total ionizing dose radiation testing. As a preconditioning, 10 K read/write cycles were performed on all devices. Interim electrical measurements were performed throughout this characterization, including special imprint testing and final electrical testing. Some failures were observed during high temperature aging test at 200 C, during HAST testing, and during 1,000 hours of operational life at 125 C. The parts passed 10 Krad exposure, but began showing power supply current increases during the dose increment from 10 Krad to 30 Krad, and at 40 Krad severe data retention and parametric failures were observed. Failures from various environmental group testing are currently being analyzed.

Sharma, Asbok K.↗
NASA NTRS2000

Evaluation of Data Retention and Imprint Characteristics of FRAMs Under Environmental Stresses for NASA Applications

A major reliability issue for all advanced nonvolatile memory (NVM) technology devices including FRAMs (Ferroelectric random access memories) is the data retention characteristics over extended period of time, under environmental stresses and exposure to total ionizing dose (TID) radiation effects. For this testing, 256 Kb FRAMs in 28-pin plastic DIPS, rated for industrial grade temperature range of -40 C to +85 C, were procured. These are two-transistor, two-capacitor (2T-2C) design FRAMs. In addition to data retention characteristics, the parts were also evaluated for imprint failures, which are defined as the failure of cells to change from a "preferred" state, where it has been for a significant period of time to an opposite state (e.g., from 1 to 0, or 0 to 1). These 256 K FRAMs were subjected to scanning acoustic microscopy (C-SAM); 1,000 temperature cycles from -65 C to +150 C; high temperature aging at 150 C, 175 C, and 200 C for 1,000 hours; highly accelerated stress test (HAST) for 500 hours; 1,000 hours of operational life test at 125 C; and total ionizing dose radiation testing. As a preconditioning, 10 K read/write cycles were performed on all devices. Interim electrical measurements were performed throughout this characterization, including special imprint testing and final electrical testing. Some failures were observed during high temperature aging test at 200 C, during HAST testing, and during 1,000 hours of operational life at 125 C. The parts passed 10 Krad exposure, but began showing power supply current increases during the dose increment from 10 Krad to 30 Krad, and at 40 Krad severe data retention and parametric failures were observed. Failures from various environmental group testing are currently being analyzed.

Sharma, Ashok K.↗
NASA NTRS1972

Conceptual design of a 10 to the 8th power bit magnetic bubble domain mass storage unit and fabrication, test and delivery of a feasibility model

The conceptual design of a highly reliable 10 to the 8th power-bit bubble domain memory for the space program is described. The memory has random access to blocks of closed-loop shift registers, and utilizes self-contained bubble domain chips with on-chip decoding. Trade-off studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit-per-chip basis. The final design has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a 16-adjacent code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (equal to or less than, 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 msec to an 800-word block and an additional 4 msec (average) to a word. The fabrication and operation are also described for a 64-bit bubble domain memory chip designed to test the concept of on-chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble.

Source record↗
NASA NTRS2004

Potential bio-medical and commercial applications of cold hibernated elastic memory (CHEM) self-deployable foam structures

A cold hibernated elastic memory (CHEM) foam structure is one of the most recent results of the quest for simple, reliable and low-cost expandable space structures. The CHEM technology utilizes shape memory polymers in open cellular (foam) structure or sandwich structures made of shape memory polymer foam cores and polymeric composite skins. It takes advantage of the polymer’s heat activated shape memory in addition to the foam’s elastic recovery to deploy a compacted structure. The glass transition temperature, Tg is tailored to rigidize the structure in the fully deployed configuration.

Sokolowski, Witold↗
DOE OSTI2024

Selective consolidation of learning and memory via recall-gated plasticity

In a variety of species and behavioral contexts, learning and memory formation recruits two neural systems, with initial plasticity in one system being consolidated into the other over time. Moreover, consolidation is known to be selective; that is, some experiences are more likely to be consolidated into long-term memory than others. Here, we propose and analyze a model that captures common computational principles underlying such phenomena. The key component of this model is a mechanism by which a long-term learning and memory system prioritizes the storage of synaptic changes that are consistent with prior updates to the short-term system. This mechanism, which we refer to as recall-gated consolidation, has the effect of shielding long-term memory from spurious synaptic changes, enabling it to focus on reliable signals in the environment. We describe neural circuit implementations of this model for different types of learning problems, including supervised learning, reinforcement learning, and autoassociative memory storage. These implementations involve synaptic plasticity rules modulated by factors such as prediction accuracy, decision confidence, or familiarity. We then develop an analytical theory of the learning and memory performance of the model, in comparison to alternatives relying only on synapse-local consolidation mechanisms. We find that recall-gated consolidation provides significant advantages, substantially amplifying the signal-to-noise ratio with which memories can be stored in noisy environments. We show that recall-gated consolidation gives rise to a number of phenomena that are present in behavioral learning paradigms, including spaced learning effects, task-dependent rates of consolidation, and differing neural representations in short- and long-term pathways.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2024

Selective consolidation of learning and memory via recall-gated plasticity

In a variety of species and behavioral contexts, learning and memory formation recruits two neural systems, with initial plasticity in one system being consolidated into the other over time. Moreover, consolidation is known to be selective; that is, some experiences are more likely to be consolidated into long-term memory than others. Here, we propose and analyze a model that captures common computational principles underlying such phenomena. The key component of this model is a mechanism by which a long-term learning and memory system prioritizes the storage of synaptic changes that are consistent with prior updates to the short-term system. This mechanism, which we refer to as recall-gated consolidation, has the effect of shielding long-term memory from spurious synaptic changes, enabling it to focus on reliable signals in the environment. We describe neural circuit implementations of this model for different types of learning problems, including supervised learning, reinforcement learning, and autoassociative memory storage. These implementations involve synaptic plasticity rules modulated by factors such as prediction accuracy, decision confidence, or familiarity. We then develop an analytical theory of the learning and memory performance of the model, in comparison to alternatives relying only on synapse-local consolidation mechanisms. We find that recall-gated consolidation provides significant advantages, substantially amplifying the signal-to-noise ratio with which memories can be stored in noisy environments. We show that recall-gated consolidation gives rise to a number of phenomena that are present in behavioral learning paradigms, including spaced learning effects, task-dependent rates of consolidation, and differing neural representations in short- and long-term pathways.

Lindsey, Jack W. (ORCID:0000000309307327)↗
NASA NTRS2010

Compact, Reliable EEPROM Controller

A compact, reliable controller for an electrically erasable, programmable read-only memory (EEPROM) has been developed specifically for a space-flight application. The design may be adaptable to other applications in which there are requirements for reliability in general and, in particular, for prevention of inadvertent writing of data in EEPROM cells. Inadvertent writes pose risks of loss of reliability in the original space-flight application and could pose such risks in other applications. Prior EEPROM controllers are large and complex and do not provide all reasonable protections (in many cases, few or no protections) against inadvertent writes. In contrast, the present controller provides several layers of protection against inadvertent writes. The controller also incorporates a write-time monitor, enabling determination of trends in the performance of an EEPROM through all phases of testing. The controller has been designed as an integral subsystem of a system that includes not only the controller and the controlled EEPROM aboard a spacecraft but also computers in a ground control station, relatively simple onboard support circuitry, and an onboard communication subsystem that utilizes the MIL-STD-1553B protocol. (MIL-STD-1553B is a military standard that encompasses a method of communication and electrical-interface requirements for digital electronic subsystems connected to a data bus. MIL-STD- 1553B is commonly used in defense and space applications.) The intent was to both maximize reliability while minimizing the size and complexity of onboard circuitry. In operation, control of the EEPROM is effected via the ground computers, the MIL-STD-1553B communication subsystem, and the onboard support circuitry, all of which, in combination, provide the multiple layers of protection against inadvertent writes. There is no controller software, unlike in many prior EEPROM controllers; software can be a major contributor to unreliability, particularly in fault situations such as the loss of power or brownouts. Protection is also provided by a powermonitoring circuit.

Katz, Richard↗
NASA NTRS1999

Sensitivity Analysis of ProSEDS (Propulsive Small Expendable Deployer System) Data Communication System

This paper discusses analytical approaches to evaluating performance of Spacecraft On-Board Computing systems, thereby ultimately achieving a reliable spacecraft data communications systems. The sensitivity analysis approach of memory system on the ProSEDS (Propulsive Small Expendable Deployer System) as a part of its data communication system will be investigated. Also, general issues and possible approaches to reliable Spacecraft On-Board Interconnection Network and Processor Array will be shown. The performance issues of a spacecraft on-board computing systems such as sensitivity, throughput, delay and reliability will be introduced and discussed.

Park, Nohpill↗
NASA NTRS1990

Redundant disk arrays: Reliable, parallel secondary storage

During the past decade, advances in processor and memory technology have given rise to increases in computational performance that far outstrip increases in the performance of secondary storage technology. Coupled with emerging small-disk technology, disk arrays provide the cost, volume, and capacity of current disk subsystems, by leveraging parallelism, many times their performance. Unfortunately, arrays of small disks may have much higher failure rates than the single large disks they replace. Redundant arrays of inexpensive disks (RAID) use simple redundancy schemes to provide high data reliability. The data encoding, performance, and reliability of redundant disk arrays are investigated. Organizing redundant data into a disk array is treated as a coding problem. Among alternatives examined, codes as simple as parity are shown to effectively correct single, self-identifying disk failures.

Gibson, Garth Alan↗
NASA NTRS2005

Highly Reliable, High-Speed, Unidirectional Serial Data Links

Highly reliable, high-speed, unidirectional serial data-communication subsystems have been proposed to be installed in an upgrade of the computing systems aboard the space shuttles. The basic design concept of these serial data links is also adaptable to terrestrial use in applications in which there are requirements for highly reliable serial data communications. The hardware and software aspects of the architecture of the data links are dictated largely by a requirement, in the original space-shuttle application, for one computer to monitor the memory transactions and memory contents of other computers in real time with high reliability and without reliance on requests for retransmission. To minimize weight while affording a capability to transfer data at a required rate of 2.56 x 10(exp 8) bits per second, it was decided that the links would be serial ones of the fiber-channel type. [Fiber channel denotes a type of serial computer bus that is used to connect a computer (usually a supercomputer) with a high-speed data storage device. Depending on the specific application, the physical connection between the transmitter and receiver could be made via an optical fiber or a twisted pair of wires.] Heretofore, fiber-channel links have ordinarily been bidirectional and have operated under protocols that provide for receiving stations to detect errors and request retransmission when necessary. In the present case, the time taken by processing to request retransmission would conflict with the requirement for real-time transfer of data. To ensure reliability without retransmission, a link according to the proposal would utilize a modified version of the normal fiberchannel character set in conjunction with forward error correction by means of a Reed-Solomon code (see figure). The Reed-Solomon encoding and decoding and the translations between the normal and modified character sets would be effected by logic circuitry external to the fiber-channel transmitter and receiver, which would be commercial off-the-shelf units. The receiving end of the link could detect and correct errors at a rate as high as 4 million times per second, if necessary. The receiver detects uncorrectable double-byte errors. It has been estimated that uncorrectable-error rate would amount to one failure in about 10(exp 19) characters.

Cole, Robert M.↗
NASA NTRS2010

NEPP non-volatile memory : FY09 summary report

This report documents the activities and results of the fiscal year 2009 (FY09) funding for the NASA Electronic Parts and Packaging (NEPP) program for non-volatile memory (NVM) devices. The FY09 task was divided into two main efforts: 1. Development of in-house measurement capability for flash devices 2. Reliability characterization of multi-level vs. single-level flash devices The FY09 NEPP Non Volatile Memory study was organized into these two sections in recognition of the continued and increasing importance of NVM to NASA. All NASA missions use NVM for boot code storage and some limited data archiving. Space-grade NVM has lagged commercial NVM development by many orders of magnitude, however. This gap in density only continues to increase as space-grade memories remain constant in the 1–16 Mbit levels, while commercial flash-based devices shrink in size and double in capacity every 18 months. Commercial flash devices are now at the 32 Gbit level, 10,000 times denser than current NASA NVM. This FY marks the beginning of a significant technological transition in NVM for NASA. The aggressive scaling of commercial NVMs has, as a by-product, made some of the flash devices radiation-tolerant enough to be at least considered for low-level radiation environment missions [Irom 2008]. This NEPP task is focused on understanding the reliability and potential future applications of such highly scaled flash memories.

Heidecker, Jason↗
DOE OSTI2025

Enhancing quantum memory lifetime with measurement-free local error correction and reinforcement learning

Reliable quantum computation requires systematic identification and correction of errors that occur and accumulate in quantum hardware. To diagnose and correct such errors, standard quantum error-correcting protocols utilize global error information across the system obtained by mid-circuit readout of ancillary qubits. We investigate circuit-level error-correcting protocols that are measurement-free and based on local error information. Such a local error correction (LEC) circuit consists of faulty multi-qubit gates to perform both syndrome extraction and ancilla-controlled error removal. We develop and implement a reinforcement learning framework that takes a fixed set of faulty gates as inputs and outputs an optimized LEC circuit. To evaluate this approach, we quantitatively characterize an extension of logical qubit lifetime by a noisy LEC circuit. For the two-dimensional (2D) classical Ising model and four-dimensional toric code, our optimized LEC circuit performs better at extending a memory lifetime compared with a conventional LEC circuit based on Toom's rule in a subthreshold gate error regime. We further show that such circuits can be used to reduce the rate of mid-circuit readouts to preserve a 2D toric code memory. Lastly, we discuss the application of the LEC protocol on dissipative preparation of quantum states with topological phases.

74 ATOMIC AND MOLECULAR PHYSICS↗
NASA NTRS1980

Titan probe technology assessment and technology development plan study

The need for technology advances to accomplish the Titan probe mission was determined by defining mission conditions and requirements and evaluating the technology impact on the baseline probe configuration. Mission characteristics found to be technology drivers include (1) ten years dormant life in space vacuum; (2) unknown surface conditions, various sample materials, and a surface temperature; and (3) mission constraints of the Saturn Orbiter Dual Probe mission regarding weight allocation. The following areas were identified for further development: surface sample acquisition system; battery powered system; nonmetallic materials; magnetic bubble memory devices, and the landing system. Preentry science, reliability, and weight reduction and redundancy must also be considered.

Castro, A. J.↗
NASA NTRS2001

Overview of Non-Volatile Testing and Screening Methods

Testing methods for memories and non-volatile memories have become increasingly sophisticated as they become denser and more complex. High frequency and faster rewrite times as well as smaller feature sizes have led to many testing challenges. This paper outlines several testing issues posed by novel memories and approaches to testing for radiation and reliability effects. We discuss methods for measurements of Total Ionizing Dose (TID).

Irom, Farokh↗