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Results for “proportional integral (PI) controller”

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57 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Joint Carrier-Phase Synchronization and LDPC Decoding

A method has been proposed to increase the degree of synchronization of a radio receiver with the phase of a suppressed carrier signal modulated with a binary- phase-shift-keying (BPSK) or quaternary- phase-shift-keying (QPSK) signal representing a low-density parity-check (LDPC) code. This method is an extended version of the method described in Using LDPC Code Constraints to Aid Recovery of Symbol Timing (NPO-43112), NASA Tech Briefs, Vol. 32, No. 10 (October 2008), page 54. Both methods and the receiver architectures in which they would be implemented belong to a class of timing- recovery methods and corresponding receiver architectures characterized as pilotless in that they do not require transmission and reception of pilot signals. The proposed method calls for the use of what is known in the art as soft decision feedback to remove the modulation from a replica of the incoming signal prior to feeding this replica to a phase-locked loop (PLL) or other carrier-tracking stage in the receiver. Soft decision feedback refers to suitably processed versions of intermediate results of iterative computations involved in the LDPC decoding process. Unlike a related prior method in which hard decision feedback (the final sequence of decoded symbols) is used to remove the modulation, the proposed method does not require estimation of the decoder error probability. In a basic digital implementation of the proposed method, the incoming signal (having carrier phase theta theta (sub c) plus noise would first be converted to inphase (I) and quadrature (Q) baseband signals by mixing it with I and Q signals at the carrier frequency [wc/(2 pi)] generated by a local oscillator. The resulting demodulated signals would be processed through one-symbol-period integrate and- dump filters, the outputs of which would be sampled and held, then multiplied by a soft-decision version of the baseband modulated signal. The resulting I and Q products consist of terms proportional to the cosine and sine of the carrier phase cc as well as correlated noise components. These products would be fed as inputs to a digital PLL that would include a number-controlled oscillator (NCO), which provides an estimate of the carrier phase, theta(sub c).

Simon, Marvin↗
DOE OSTI2024

Robust Disturbance Rejection Rotor Current Control of Doubly-Fed Induction Generators

This article proposes a robust transient disturbance rejection current controller (TDRCC) to improve the transient performance of doubly-fed induction generators (DFIGs) in wind turbines during grid disturbances, such as short circuits. Here, the proposed robust TDRCC replaces the proportional-integral-derivative (PID) current controllers conventionally used in the vector control scheme of the DFIG rotor side converter (RSC). The TDRCC estimates the transient disturbances caused by grid faults or other external disturbances and provides compensation to the DFIG rotor voltage in the current control loops of the RSC to improve the robustness of the controller to disturbance. A sliding-mode current controller (SMCC) is also designed to highlight the transient performance improvement of the DFIG using the TDRCC over the state-of-the-art control methods during grid short circuit faults. Simulation studies are conducted in PSCAD/EMTDC for a 3.6-MW DFIG wind turbine with the proposed TDRCC, the conventional PI controller, and the SMCC, respectively during the most severe balanced three-phase grid short circuit fault specified by the U.S. grid code as well as an unbalance single-phase grid short circuit fault. Hardware experiments are conducted on a 200-W DFIG wind turbine emulator with the three different controllers for the same three-phase short circuit fault. Simulation and hardware experiment results show that the TDRCC reduces the peak rotor current significantly when compared with the PI and SMCC controlled DFIG system and, therefore, would help prolong the lifespan of the DFIG's power electronics and reduce maintenance costs.

42 ENGINEERING↗
NASA NTRS2005

Continuous, Full-Circle Arctangent Circuit

A circuit generates an analog voltage proportional to an angle, in response to two sinusoidal input voltages having magnitudes proportional to the sine and cosine of the angle, respectively. That is to say, given input voltages proportional to sin(Omega(t))sin(Theta) and sin(Omega(t))cos(Theta) [where Theta denotes the angle, mega denotes 2(pi) x a carrier frequency, and t denotes time], the circuit generates a steady voltage proportional to Theta. The output voltage varies continuously from its minimum to its maximum value as Theta varies from -180deg to 180deg. While the circuit could accept input modulated sine and cosine signals from any source, it must be noted that such signals are typical of the outputs of shaft-angle resolvers in electromagnetic actuators used to measure and control shaft angles for diverse purposes like aiming scientific instruments and adjusting valve openings. In effect, the circuit is an analog computer that calculates the arctangent of the ratio between the sine and cosine signals. The full-circle angular range of this arctangent circuit stands in contrast to the range of prior analog arctangent circuits, which is from slightly greater than -90deg to slightly less than +90deg. Moreover, for applications in which continuous variation of output is preferred to discrete increments of output, this circuit offers a clear advantage over resolver- to-digital integrated circuits.

Alhorn, Dean C.↗