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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4

All sources NASA NTRS DOE OSTI

NASA NTRS1973

Highly reliable processor system for space application.

Description of a redundant processor organization which can be implemented with off-the-shelf processors for fault-tolerant operation. Reconfiguration can be performed automatically in a transientless manner. To support this system configuration and redundancy management concept, an operating system referred to as a synchronous executive has been designed. This system is directed at real-time closed-loop space applications where minimum response time, no degradation of software solution, and system simplicity are of importance. The system is based on a multicomputer organization with each machine solving the same problem based on a common set of inputs. Processor status is fed to a higher-level device which selects a controlling processor for controlling outputs and monitoring computers for fault detection.

Tsou, H. S. E.↗

NASA NTRS1974

Power processor design considerations for a solar electric propulsion spacecraft

Propulsion power processor design options are described. The propulsion power processor generated the regulated dc voltages and currents from a solar array source of a solar electric propelled spacecraft. The power processor consisted of 12 power supplies that provide the regulated voltages and currents necessary to power a 30-cm mercury ion thruster. The design options for processing unregulated solar array power and for generating the regulated power required by each supply are studied. The technical approaches utilized in the developed design and the technological limitation of the identified design options are discussed. Alternate approaches for delivering power to a number of mercury ion thrusters and methods of optimizing are described. It was concluded that this power processor design should be considered for application in solar electric propulsion missions of the future.

Costogue, E. N.↗

NASA NTRS1975

A reliability tradeoff study of interconnecting power processors to mercury ion thrusters

A Monte Carlo mission simulation program has been developed to optimize the solar electric propulsion (SEP) thrust subsystem configuration for an Encke comet rendezvous mission. This program examines several possible options for interconnecting power processors to the mercury ion thrusters in order to enhance mission reliability and to reduce SEP subsystem weight. The quantity of power processors and ion thrusters required to perform the mission successfully depends not only on the total required thrust, but also on the individual thruster and power processor performance and reliability. Based on these considerations, it was necessary to determine the quantity of the active power processors and ion thrusters required at any time and the means of providing redundancy. The results provide the basis for selecting an optimum SEP thrust subsystem for this mission and other missions.

Costogue, E. N.↗

NASA NTRS1975

An optical/digital processor - Hardware and applications

A real-time two-dimensional hybrid processor consisting of a coherent optical system, an optical/digital interface, and a PDP-11/15 control minicomputer is described. The input electrical-to-optical transducer is an electron-beam addressed potassium dideuterium phosphate (KD2PO4) light valve. The requirements and hardware for the output optical-to-digital interface, which is constructed from modular computer building blocks, are presented. Initial experimental results demonstrating the operation of this hybrid processor in phased-array radar data processing, synthetic-aperture image correlation, and text correlation are included. The applications chosen emphasize the role of the interface in the analysis of data from an optical processor and possible extensions to the digital feedback control of an optical processor.

Casasent, D.↗

NASA NTRS1978

Electrical Prototype Power Processor for the 30-cm Mercury electric propulsion engine

An Electrical Prototpye Power Processor has been designed to the latest electrical and performance requirements for a flight-type 30-cm ion engine and includes all the necessary power, command, telemetry and control interfaces for a typical electric propulsion subsystem. The power processor was configured into seven separate mechanical modules that would allow subassembly fabrication, test and integration into a complete power processor unit assembly. The conceptual mechanical packaging of the electrical prototype power processor unit demonstrated the relative location of power, high voltage and control electronic components to minimize electrical interactions and to provide adequate thermal control in a vacuum environment. Thermal control was accomplished with a heat pipe simulator attached to the base of the modules.

Biess, J. J.↗

NASA NTRS1978

'Smart', remote holographic processor based on the materials characteristics of LiNbO3

A class of 'Smart' remote holographic processors based on the material characteristics of LiNbO3 is introduced. The processors rely on holographic subtraction to detect differences in optical wavefronts that are spatially modulated to reflect either incoming or reference information. The state of the art of their fabrication and performance is described in the following paper. This paper outlines the principles of holography and photorefractivity that make these processors possible. Particular emphasis is placed on a potential mode of operation termed self-subtraction, in which the holographic processor is able to adapt to changes in reference information without the need for commands from an external operator.

Vahey, D. W.↗

NASA NTRS1978

Electronic SAR processors for space missions

This paper reports some interim results relating to an on-going effort to develop an electronic processor for real-time processing of synthetic aperture radar data. An experimental laboratory processor is being developed as a testbed for design of onboard processors for future space missions. This paper describes the configuration of the experimental processor and discusses technical factors pertaining to the design.

Wu, C.↗

NASA NTRS1980

Coding, testing and documentation of processors for the flight design system

The general functional design and implementation of processors for a space flight design system are briefly described. Discussions of a basetime initialization processor; conic, analytical, and precision coasting flight processors; and an orbit lifetime processor are included. The functions of several utility routines are also discussed.

Source record↗

NASA NTRS1979

Reduced power processor requirements for the 30-cm diameter HG ion thruster

The characteristics of power processors strongly impact the overall performance and cost of electric propulsion systems. A program was initiated to evaluate simplifications of the thruster-power processor interface requirements. The power processor requirements are mission dependent with major differences arising for those missions which require a nearly constant thruster operating point (typical of geocentric and some inbound planetary missions) and those requiring operation over a large range of input power (such as outbound planetary missions). This paper describes the results of tests which have indicated that as many as seven of the twelve power supplies may be eliminated from the present Functional Model Power Processor used with 30-cm diameter Hg ion thrusters.

Rawlin, V. K.↗

NASA NTRS1980

The software system development for the TAMU real-time fan beam scatterometer data processors

A software package was designed and written to process in real-time any one quadrature channel pair of radar scatterometer signals form the NASA L- or C-Band radar scatterometer systems. The software was successfully tested in the C-Band processor breadboard hardware using recorded radar and NERDAS (NASA Earth Resources Data Annotation System) signals as the input data sources. The processor development program and the overall processor theory of operation and design are described. The real-time processor software system is documented and the results of the laboratory software tests, and recommendations for the efficient application of the data processing capabilities are presented.

Clark, B. V.↗

NASA NTRS1981

Electro-optical processor for optimal control

An iterative optical processor has been developed for applications in the optimal control of advanced sensor systems. The processor is designed for the realization of the Richardson algorithm on bipolar data, using as input a linear array of LEDs. The usefulness of the processor has been demonstrated by the solution of the linear quadratic regulator problem for the optimal control signals of the F100 turbofan engine. In this case study, the algebraic Riccati equation matrix was solved by the use of a modified Kleinman algorithm along with the Richardson algorithm applied to a system of linear algebraic equations. Preliminary experimental results demonstrate the gradual convergence of the processor.

Casasent, D.↗

NASA NTRS1983

LU and Cholesky decomposition on an optical systolic array processor

Direct solutions of matrix-vector equations on an optical systolic array processor are considered. The solutions are discussed and a parallel algorithm for LU matrix decomposition that is very attractive for an optical realization is formulated. It is noted that when direct techniques are used, it is preferable to realize the matrix decomposition on an optical system and to utilize a digital processor for the solution of the simplified resultant matrix-vector problem. One method of realizing LU matrix decomposition on a new frequency-multiplexed optical systolic array matrix-matrix processor is described. A simple method for extending the process of LU decomposition to Cholesky decomposition on the optical processor is discussed.

Casasent, D.↗

NASA NTRS1983

Performance evaluation of the JPL interim digital SAR processor

The performance of the Interim Digital SAR Processor (IDP) was evaluated. The IDP processor was originally developed for experimental processing of digital SEASAT SAR data. One phase of the system upgrade which features parallel processing in three peripheral array processors, automated estimation for Doppler parameters, and unsupervised image pixel location determination and registration was executed. The method to compensate for the target range curvature effect was improved. A four point interpolation scheme is implemented to replace the nearest neighbor scheme used in the original IDP. The processor still maintains its fast throughput speed. The current performance and capability of the processing modes now available on the IDP system are updated.

Wu, C.↗

NASA NTRS1982

Baseband processor development for the Advanced Communications Satellite Program

An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

Moat, D.↗

NASA NTRS1984

Finding maximum on an array processor with a global bus

The problem of finding the maximum of a set of values stored one/processor on an n x n array of processors is analyzed. The array has a time-shared global bus in addition to conventional processor-processor links. A two-phase algorithm for finding the maximum is presented that uses conventional links during the first phase and the global bus during the second. This algorithm is faster than algorithms that use either only the global bus or only the conventional links. Two types of interconnection patterns (the eighth nearest neighbor and the fourth nearest neighbor) are analyzed. In both cases it is shown that the time required to find the maximum using the two-phase algorithm is 0(n to the 2/3-power) assuming the propagation speed of the global bus to be a constant independent of the size of the array. In the case where the propagation speed is logarithmic in the number of processors, the time to find the maximum is 0(/n-squared log n/1/3), for both types of arrays. Extensions to q-dimensional arrays show that the two-phase algorithm is superior for any fixed value of q.

Bokhari, S. H.↗

NASA NTRS1984

Finite elements and the method of conjugate gradients on a concurrent processor

An algorithm for the iterative solution of finite element problems on a concurrent processor is presented. The method of conjugate gradients is used to solve the system of matrix equations, which is distributed among the processors of a MIMD computer according to an element-based spatial decomposition. This algorithm is implemented in a two-dimensional elastostatics program on the Caltech Hypercube concurrent processor. The results of tests on up to 32 processors show nearly linear concurrent speedup, with efficiencies over 90% for sufficiently large problems.

Lyzenga, G. A.↗

NASA NTRS1986

Dual-Sampler Processor Digitizes CCD Output

Circuit for processing output of charge-coupled device (CCD) imager provides increased time for analog-to-digital conversion, thereby reducing bandwidth required for video processing. Instead of one sampleand-hold circuit of conventional processor, improved processor includes two sample-and-hold circuits alternated with each other. Dual-sampler processor operates with lower bandwidth and with timing requirements less stringent than those of single-sample processor.

Salomon, P. M.↗

NASA NTRS1984

Programmable Real-Time Acousto-Optic/CCD SAR processor

The theory of operation of the Real-Time Acousto-Optic SAR Processor is reviewed and recent experimental results are presented. The results include a demonstration of the real-time imaging capability of the processor with simulated radar signals. An advanced version of this processor is then described in which a programmable reference function is entered via a second acousto-optic device to eliminate the need for a 2-D SLM. In this implementation the reference function is updated by electronic means to give the processor the flexibility to adapt rapidly to changes in the parameters of the radar/target geometry.

Haney, M.↗