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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2019

Simulations of subatomic many-body physics on a quantum frequency processor

Simulating complex many-body quantum phenomena is a major scientific impetus behind the development of quantum computing, and a range of technologies are being explored to address such systems. We present the results of the largest photonics-based simulation to date, applied in the context of subatomic physics. Using an all-optical quantum frequency processor, the ground-state energies of light nuclei including the triton ( 3 H), 3 He, and the alpha particle ( 4 He) are computed. Complementing these calculations and utilizing a 68-dimensional Hilbert space, our photonic simulator is used to perform subnucleon calculations of the two- and three-body forces between heavy mesons in the Schwinger model. Furthermore, this work is a first step in simulating subatomic many-body physics on quantum frequency processors—augmenting classical computations that bridge scales from quarks to nuclei.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2021

Non-Gaussian photonic state engineering with the quantum frequency processor

Non-Gaussian quantum states of light are critical resources for optical quantum information processing, but methods to generate them efficiently remain challenging to implement. Here we introduce a generic approach for non-Gaussian state production from input states populating discrete frequency bins. Based on controllable unitary operations with a quantum frequency processor, followed by photon-number-resolved detection of ancilla modes, our method combines recent developments in both frequency-based quantum information and non-Gaussian state preparation. Leveraging and refining the K-function representation of quantum states in the coherent basis, we develop a theoretical model amenable to numerical optimization and, as specific examples, design quantum frequency processor circuits for the production of Schrödinger cat states, exploring the performance tradeoffs for several combinations of ancilla modes and circuit depth. Our scheme provides a valuable framework for producing complex quantum states in frequency bins, paving the way for single-spatial-mode, fiber-optic-compatible non-Gaussian resources.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

Modular Quantum Processor with an All-to-All Reconfigurable Router

Superconducting qubits provide a promising approach to large-scale fault-tolerant quantum computing. However, qubit connectivity on a planar surface is typically restricted to only a few neighboring qubits. Achieving longer-range and more flexible connectivity, which is particularly appealing in light of recent developments in error-correcting codes, however, usually involves complex multilayer packaging and external cabling, which is resource intensive and can impose fidelity limitations. Here, we propose and realize a high-speed on-chip quantum processor that supports reconfigurable all-to-all coupling with a large on-off ratio. We implement the design in a four-node quantum processor, built with a modular design comprising a wiring substrate coupled to two separate qubit-bearing substrates, each including two single-qubit nodes. We use this device to demonstrate reconfigurable controlled-𝑍 gates across all qubit pairs, with a benchmarked average fidelity of 96.00% ± 0.08% and best fidelity of 97.14% ± 0.07%, limited mainly by dephasing in the qubits. We also generate multiqubit entanglement, distributed across the separate modules, demonstrating GHZ-3 and GHZ-4 states with fidelities of 88.15% ± 0.24% and 75.18% ± 0.11%, respectively. This approach promises efficient scaling to larger-scale quantum circuits and offers a pathway for implementing quantum algorithms and error-correction schemes that benefit from enhanced qubit connectivity.

Quantum circuits↗
DOE OSTI2024

Circuit-Based Leakage-to-Erasure Conversion in a Neutral-Atom Quantum Processor

Atom-loss errors are a major limitation of current state-of-the-art neutral-atom quantum computers and pose a significant challenge for scalable systems. In a quantum processor with cesium atoms, we demonstrate proof-of-principle circuit-based conversion of this form of leakage error to erasure errors via leakage-detection units (LDUs), which nondestructively map information about the presence or absence of the qubit onto the state of an ancilla. We benchmark the performance of the LDU using a three-outcome low-loss state-detection method and find that the LDU detects atom-loss errors with approximately 93.4% accuracy, limited by technical imperfections of our apparatus. We further compile and execute a SWAP LDU, wherein the roles of the original data atom and ancilla atom are exchanged under the action of the LDU, providing “free refilling” of atoms in the case of atom loss. This circuit-based leakage-to-erasure error conversion is a critical component of a neutral-atom quantum processor where the quantum information may significantly outlive the lifetime of any individual atom in the quantum register. Finally, we demonstrate that LDUs may also be used to handle other forms of leakage errors where population moves to states outside of the computational subspace.

Chow, Matthew N. H. [Sandia National Laboratories ↗
DOE OSTI2025

Probing Curved Spacetime with a Distributed Atomic Processor Clock

Quantum dynamics on curved spacetime has never been directly probed beyond the Newtonian limit. Although we can describe such dynamics theoretically, experiments would provide empirical evidence that quantum theory holds even in this extreme limit. The practical challenge is the minute spacetime curvature difference over the length scale of the typical extent of quantum effects. Here, we propose a quantum network of alkaline earth (like) atomic processors for constructing a distributed quantum state that is sensitive to the differential proper time between its constituent atomic processor nodes, implementing a quantum observable that is affected by post-Newtonian curved spacetime. Conceptually, we propose to delocalize one clock between three locations by encoding the presence or absence of a clock into the state of the local atoms. By separating three atomic nodes over approximately kilometer-scale elevation differences and distributing one clock between them via a 𝑊 state, we demonstrate that the curvature of spacetime is manifest in the interference of the three different proper times that give rise to three distinct beat notes in our nonlocal observable. We further demonstrate that 𝑁-atom entanglement within each node enhances the interrogation bandwidth by a factor of 𝑁. We discuss how our proposed system can probe new facets of fundamental physics, such as the linearity, unitarity, and probabilistic nature of quantum theory on curved spacetime. Our protocol combines several recent advances with neutral atom and trapped ions to realize a novel quantum probe of gravity uniquely enabled by quantum networks.

Covey, Jacob P. [Univ. of Illinois at Urbana-Champ↗
DOE OSTI2023

An FPGA-Based Neuromorphic Processor with All-to-All Connectivity

Neuromorphic computing is a promising paradigm for future energy-efficient computing. At present, however, it is in its nascent stages—most hardware implementations are research-grade, commercial products are not available, and the software tools are not production-ready. The lack of hardware and software tools makes neuromorphic computing inaccessible to researchers around the globe. To this extent, we intend to build a low-cost, open-source, FPGA-based digital neuromorphic processor that can be used by researchers worldwide. In this paper, we present a preliminary implementation of the processor on a Xilinx Artix-7 FPGA using SystemVerilog. Our implementation supports the integrate-and-fire neuron with two parameters each for neurons and synapses. It also features all-to-all connectivity among neurons on the hardware. We test our implementation on four cases: bars and stripes datasets, shortest path algorithm, logic gates, and 8-3 encoder. We also perform a scalability study to understand the resource utilization of the FPGA as the number of all-to-all connected neurons increases. With our implementation, the Artix- 7 supports 65 neurons with all-to-all connectivity. Moreover, all the test cases mentioned above achieve 100% accuracy.

Maheshwari, Disha↗
DOE OSTI2022

Benchmarking Quantum Processor Performance through Quantum Distance Metrics Over An Algorithm Suite

Quantum computing is poised to solve computational paradigms that classical computing could never feasibly reach. Tasks such as prime factorization to Quantum Chemistry are examples of classically difficult problems that have analogous algorithms that are sped up on quantum computers. To attain this computational advantage, we must first traverse the noisy intermediate scale quantum (NISQ) era, in which quantum processors suffer from compounding noise factors that can lead to unreliable algorithm induction producing noisy results. We describe QASMBench, a suite of QASM-level (Quantum assembly language) benchmarks that challenge all realisable angles of quantum processor noise. We evaluate a large portion of these algorithms by performing density matrix tomography on 14 IBMQ Quantum devices.

Stein, Samuel A.↗
DOE OSTI2021

Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors

Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor’s scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Furthermore, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop’s sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.

42 ENGINEERING↗
DOE OSTI2024

Probing Quantum Telecloning on Superconducting Quantum Processors

Quantum information cannot be perfectly cloned, but approximate copies of quantum information can be generated. Quantum telecloning combines approximate quantum cloning, more typically referred to as quantum cloning, and quantum teleportation. Quantum telecloning allows approximate copies of quantum information to be constructed by separate parties, using the classical results of a Bell measurement made on a prepared quantum telecloning state. Quantum telecloning can be implemented as a circuit on quantum computers using a classical coprocessor to compute classical feedforward instructions using if statements based on the results of a midcircuit Bell measurement in real time. We present universal symmetric optimal 1 → M telecloning circuits and experimentally demonstrate these quantum telecloning circuits for M = 2 up to M = 10, natively executed with real-time classical control systems on IBM Quantum superconducting processors, known as dynamic circuits. We perform the cloning procedure on many different message states across the Bloch sphere, on seven IBM Quantum processors, optionally using the error suppression technique X–X sequence digital dynamical decoupling. Two circuit optimizations are utilized: one that removes ancilla qubits for M = 2,3 , and one that reduces the total number of gates in the circuit but still uses ancilla qubits. Parallel single-qubit tomography with maximum likelihood estimation density matrix reconstruction is used in order to compute the mixed-state density matrices of the clone qubits, and clone quality is measured using quantum fidelity. These results present one of the largest and most comprehensive noisy intermediate-scale quantum computer experimental analyses on (single qubit) quantum telecloning to date. The clone fidelity sharply decreases to 0.5 for M > 5 , but for M = 2 , we are able to achieve a mean clone fidelity of up to 0.79 using dynamical decoupling.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2025

Realization and Calibration of Continuously Parameterized Two-Qubit Gates on a Trapped-Ion Quantum Processor

Continuously parameterized two-qubit gates are a key feature of state-of-the-art trapped-ion quantum processors, as they have favorable error scalings and show distinct improvements in circuit performance over more restricted maximally entangling gatesets. In this work, we provide a comprehensive and pedagogical discussion on how to practically implement these continuously parameterized Mølmer–Sørensen gates on the Quantum Scientific Computing Open User Testbed, a low-level trapped-ion processor. To generate the arbitrary entangling angles, θ, we simply scale the amplitude of light used to generate the entanglement. However, doing so requires careful consideration of amplifier saturation as well as the variable light shifts that result. As such, we describe a method to calibrate and cancel the dominant fourth-order effects, followed by a dynamic virtual phase advance during the gate to cancel any residual light shifts, and find a linear scaling between θ and the residual light shift. Once we have considered and calibrated these effects, we demonstrate performance improvement with decreasing θ. Finally, we describe nuances of hardware control to transform the XX-type interaction of the arbitrary-angle Mølmer–Sørensen gate into a phase-agnostic and crosstalk-mitigating ZZ interaction.

Yale, Christopher Gordon [Sandia National Laborato↗
DOE OSTI2023

Modelling integrated quantum frequency processors towards robust quantum networks

Frequency-encoded quantum information offers intriguing opportunities for quantum communications networks, with the quantum frequency processor (QFP) paradigm promising scalable construction of quantum gates. Yet all experimental demonstrations to date have relied on discrete fiber-optic components that occupy significant physical space and impart appreciable loss. We introduce a model for designing QFPs comprising microring resonator-based pulse shapers and integrated phase modulators. We estimate the performance of frequency-bin Hadamard gates, finding high fidelity values sustained for relatively wide-bandwidth frequency bins. Our simple model and can be extended to other material platforms, providing a design tool for future frequency processors in integrated photonics.

Nussbaum, Benjamin↗
DOE OSTI2018

Graphic Processor Realization of the Formal Solution of the Problem of Radiation Transfer in the Neutron Star Atmosphere

The realization (on the CUDA platform) of the search for the formal solution to the problem of radiation transfer in the strongly magnetized plasma in the atmosphere of a neutron star on graphic processors with the CUDA architecture. The solution is obtained using the Galerkin method with finite elements. The realization of graphic processors makes it possible to substantially accelerate computations in constructing models for the atmospheres of neutron stars.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2019

SMuRF Processor

This repository contains the SMuRF data processor. This processor receive each data frame from coming from the SMuRF FPGA, and average the data by a configurable number of samples.

Vasquez, Jesus↗
DOE OSTI2018

Image Matrix Processor for Volumetric Computations Final Report CRADA No. TSB-1148-95

The development of an Image Matrix Processor (IMP) was proposed that would provide an economical means to perform rapid ray-tracing processes on volume "Giga Voxel" data sets. This was a multi-phased project. The objective of the first phase of the IMP project was to evaluate the practicality of implementing a workstation-based Image Matrix Processor for use in volumetric reconstruction and rendering using hardware simulation techniques. Additionally, ARACOR and LLNL worked together to identify and pursue further funding sources to complete a second phase of this project.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Efficient Scalable Tomography of Many-Qubit Quantum Processors

Quantum computing has the potential to realize powerful and revolutionary applications. A quantum computer can, in theory, solve certain problems exponentially faster than its classical counterparts. The current state of the art devices, however, are too small and noisy to practically realize this goal. An important tool for the advancement of quantum hardware, called model-based characterization, seeks to learn what types of noise are exhibited in a quantum processor. This technique, however, is notoriously difficult to scale up to even modest numbers of qubit, and has been limited to just 2 qubits until now. In this report, we present a novel method for performing model-based characterization, or tomography, on a many-qubit quantum processor. We consider up to 10 qubits, but the technique is expected to scale to even larger systems.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Efficient, Predictive Tomography of Multi-Qubit Quantum Processors

After decades of R&D, quantum computers comprising more than 2 qubits are appearing. If this progress is to continue, the research community requires a capability for precise characterization (“tomography”) of these enlarged devices, which will enable benchmarking, improvement, and finally certification as mission-ready. As world leaders in characterization -- our gate set tomography (GST) method is the current state of the art – the project team is keenly aware that every existing protocol is either (1) catastrophically inefficient for more than 2 qubits, or (2) not rich enough to predict device behavior. GST scales poorly, while the popular randomized benchmarking technique only measures a single aggregated error probability. This project explored a new insight: that the combinatorial explosion plaguing standard GST could be avoided by using an ansatz of few-qubit interactions to build a complete, efficient model for multi-qubit errors. We developed this approach, prototyped it, and tested it on a cutting-edge quantum processor developed by Rigetti Quantum Computing (RQC), a US-based startup. We implemented our new models within Sandia’s PyGSTi open-source code, and tested them experimentally on the RQC device by probing crosstalk. We found two major results: first, our schema worked and is viable for further development; second, while the Rigetti device is indeed a “real” 8-qubit quantum processor, its behavior fluctuated significantly over time while we were experimenting with it and this drift made it difficult to fit our models of crosstalk to the data.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Mixed core processor unit

A method and apparatus for processing data. The data is sent to a processor unit comprising a group of neural cores, a group of digital processing cores, and a routing network connecting the group of digital processing cores. The data is processed in the processor unit to generate a result.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Promoting prefetched data from a cache memory to registers in a processor

An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.

Kotra, Jagadish↗