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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1997

Piezoelectric Power Requirements for Active Vibration Control

This paper presents a method for predicting the power consumption of piezoelectric actuators utilized for active vibration control. Analytical developments and experimental tests show that the maximum power required to control a structure using surface-bonded piezoelectric actuators is independent of the dynamics between the piezoelectric actuator and the host structure. The results demonstrate that for a perfectly-controlled system, the power consumption is a function of the quantity and type of piezoelectric actuators and the voltage and frequency of the control law output signal. Furthermore, as control effectiveness decreases, the power consumption of the piezoelectric actuators decreases. In addition, experimental results revealed a non-linear behavior in the material properties of piezoelectric actuators. The material non- linearity displayed a significant increase in capacitance with an increase in excitation voltage. Tests show that if the non-linearity of the capacitance was accounted for, a conservative estimate of the power can easily be determined.

Brennan, Matthew C.↗
DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 µm\textsuperscript{2} in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e\textsuperscript{-} and a total dispersion of $\sim$100e\textsuperscript{-} The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4\% – 75.4\% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm\textsuperscript{2} staying within the experimental constraints.

Parpillon, Benjamin↗
DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 $\mu$m$^2$ in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e$^-$ and a total dispersion of $\sim$100e$^-$ The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4% - 75.4% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm$^2$ staying within the experimental constraints.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Photon-to-Digital Converters for Neutron Imaging Instruments (Final Report)

Oak Ridge National Laboratory (ORNL) collaborated with the Université de Sherbrooke (UdeS) to design a modular and scalable tile of innovative digital photodetectors called Photon-to-Digital Converters (PDC) and the required subsystems to demonstrate the feasibility of large area single-photon detectors to support high-resolution, depth-of-interaction, fast neutron radiography based on scintillation detectors. The goal is to demonstrate the advantages of using PDC over conventional Silicon Photomultiplier (SiPM) for neutron imaging systems. The basic building blocks of analog SiPM and PDC are Single-Photon Avalanche Photodiodes (SPAD). The main difference between conventional SiPMs and PDCs, is in the fact that analog SiPMs sum the charge produced by individual SPAD passively, while in PDCs each SPAD is read out individually by an active electronic circuit. Hence, PDCs provide a direct photon-to-bit conversion where a logic “1” means that there was a detection in a given SPAD. Conversely, an analog SiPM requires a sophisticated preamplifier (current amplifiers or transimpedance amplifier) followed by a shaping amplifier and an analog-to-digital converter. Moreover, since the charge from each SPAD varies slightly, the passive sum of the analog SiPM will have signal fluctuations for the same amount of photon detected. This is one of many issues that is completely eliminated by individual one-to-one SPAD read out in PDCs. The large area required for scintillator readouts for neutron imaging is such that the output capacitance of a large area of SiPM arrays is very high. This creates a burden on the signal-to-noise optimization with respect to the power budget. For PDC, the power consumption is dictated by rate of the incident photon flux, or in photon-starved environments, the dark noise rate of the SPAD array. In other words, the power consumption in the absence of events is extremely low. Hence, the power consumption of a PDC read out system is much lower than its analog counterpart. Further, the large SiPM capacitance may introduce signal distortions on the scintillator fast rise or decay time with undesired effects on timing and pulse shape discrimination. The problem is absent in PDCs, as their readout is independent on device capacitance. UdeS is the world leader in 3D vertical integration of frontside illuminated SPAD arrays over CMOS readouts. These capabilities allow future production of “3D PDC” with maximum photosensitive fill factor and electronic functionalities tailored to the application. UdeS' vast knowledge of SPADs and CMOS design made the team an ideal collaborator in the development of large area high-resolution fast neutron radiography.

42 ENGINEERING↗
DOE OSTI2021

Rootkit detection system

A system and method (referred to as the system) detect infectious code. The system injects a repetitive software code that causes malware in a monitored device to render a detectable direct current power consumption profile. A guide wave generator generates a guide wave signal that establishes an observational window that is applied to data that represent a direct current source power consumption of the monitored device. An extraction device extracts a portion of the data that represent the direct current source power consumption of the monitored device. A deviation engine identifies the malware on the monitored device without processing data associated with a prior identification of the malware or identifying a source of the malware or identifying a location of the malware on the monitored device.

Dawson, Joel↗
DOE OSTI2022

Smart dim fuse: electrical load flexibility controller using sub-circuit voltage modulation and load sensing

Improved control of electrical power consumption is provided with “Smart Dim Fuses” (SDF) which can alter their output voltage as provided to the load circuits they are connected to. SDF units can replace conventional circuit breakers in electrical panels. The voltage control capability provided by SDF units can lead to improved control of electrical power consumption, since many loads can smoothly operate at lower power consumption when the voltage they are driven with decreases. SDF units can comply with relevant safety requirements, such as uninterrupted neutral connections between electrical mains and load circuits. SDF units can also provide a current limiting function that can substitute for the protective action of conventional circuit breakers.

Goldin, Aaron↗
DOE OSTI2022

An Ensemble Approach to Computationally Efficient Radiological Anomaly Detection and Isotope Identification

Radiological source search is a challenging task involving detection and identification of weak sources in a constantly changing radiological background. As of now, many radiological source detection algorithms have been proposed; however, their computational complexity, and hence reliance on power intensive processing units inhibit low-power applications of radiological source search systems. In this work, we introduce the anomaly filter (AF) algorithm; a computationally light, yet effective time-series source detection algorithm based on exponential weighted moving average (EWMA) and Poisson deviance statistics. Then, we demonstrate that the proposed algorithm can be used in ensemble with other more computationally intensive source detection and identification algorithms to achieve both increased detection performance and reduced power consumption. The proposed AF algorithm and the ensemble algorithms were thoroughly benchmarked against several existing source detection and identification algorithms. The results show that the AF algorithm outperforms existing conventional source detection algorithms, and the ensemble approach improves the overall performance of existing source detection and isotope identification algorithms. Furthermore, the AF algorithm and the Non-negative Matrix Factorization approach based source identification (NMF-ID) algorithm were combined and implemented on a singleboard microcontroller and the power consumption was measured. This ensemble algorithm reduced the power consumption of the NMF-ID algorithm almost by a factor of 100, while improving the detection performance of the overall system.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2026

Holistic energy analysis method for thermal management architectures of data centers

Modern high-performance computing (HPC) data centers (DCs), particularly those supporting energy-intensive artificial intelligence (AI) workloads, face escalating thermal management challenges that degrade performance through thermal throttling and drive up cooling power consumption and operational costs. To address this challenge, many have developed a wide variety of thermal management solutions (single-phase, two-phase, direct, indirect, hybrid, and more) which attempt to cool HPC DCs effectively while attempting to minimize overall system power consumption. However, the analysis of these solutions and methods to effectively compare one with another is lacking. Overall power usage effectiveness (PUE) and total-power usage effectiveness (TUE) provide a metric to quantify power consumption but fail to identify components in the system which require further optimization. To address this, we propose a holistic analytical framework – the waterfall diagram (WFD) – which leverages a waterfall chart methodology, offering a comprehensive visualization of both the thermal management system loop and heat flow pathways from individual server components to the outdoor ambient. Use of the WFD enables graphical estimations of power efficiency and cooling performance across each component of a DC cooling system and complements Sankey-style energy flow visualizations by additionally resolving stage-wise temperature changes and incremental TUE contributions. The framework is used in conjunction with simulation-based approaches, to conduct a detailed pressure drop and flow distribution analysis aimed at identifying the optimal coolant distribution architecture for a single-phase direct-to-chip water-cooled DC, which serves as the baseline for subsequent WFD analysis. Among the evaluated architectures, the 3 U modular coolant distribution architecture is found to demonstrate the best performance, considering minimal pressure drop and uniform flow distribution. In addition, TUE is calculated for each cooling loop component based on its associated pressure drop and corresponding pumping power, which are integrated into the WFD. This correlation between TUE and local temperature offers immediate insight into the power efficiency and thermal performance contributions of individual components, facilitating further development and optimization. Examples of WFD applications are presented under varying thermal loads and ambient conditions, demonstrating reasonable cooling strategies. Notably, the 3 U modular architecture maintains a consistent chip case temperature of 85°C, achieving a TUE of 1.016 at ambient temperature of 47°C, and a TUE of 1.026 at ambient temperature of 52°C. The WFD methodology provides an efficient, holistic, and streamlined framework for DC thermal management architecture assessment and enables design optimization which is important for addressing the thermal-fluidic energy challenges of current and next-generation DCs.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
NASA NTRS2010

Nanoionics-Based Switches for Radio-Frequency Applications

Nanoionics-based devices have shown promise as alternatives to microelectromechanical systems (MEMS) and semiconductor diode devices for switching radio-frequency (RF) signals in diverse systems. Examples of systems that utilize RF switches include phase shifters for electronically steerable phased-array antennas, multiplexers, cellular telephones and other radio transceivers, and other portable electronic devices. Semiconductor diode switches can operate at low potentials (about 1 to 3 V) and high speeds (switching times of the order of nanoseconds) but are characterized by significant insertion loss, high DC power consumption, low isolation, and generation of third-order harmonics and intermodulation distortion (IMD). MEMS-based switches feature low insertion loss (of the order of 0.2 dB), low DC power consumption (picowatts), high isolation (>30 dB), and low IMD, but contain moving parts, are not highly reliable, and must be operated at high actuation potentials (20 to 60 V) generated and applied by use of complex circuitry. In addition, fabrication of MEMS is complex, involving many processing steps. Nanoionics-based switches offer the superior RF performance and low power consumption of MEMS switches, without need for the high potentials and complex circuitry necessary for operation of MEMS switches. At the same time, nanoionics-based switches offer the high switching speed of semiconductor devices. Also, like semiconductor devices, nanoionics-based switches can be fabricated relatively inexpensively by use of conventional integrated-circuit fabrication techniques. More over, nanoionics-based switches have simple planar structures that can easily be integrated into RF power-distribution circuits.

Nessel, James↗
DOE OSTI2023

The Regenerative Current Mirror: A Very Low Power Front-End Amplifier for Silicon Pixel Detectors

In pixelized detectors, reducing power consumption in the front- end ASIC chips becomes a crucial demand. Optimization based on mature pre-amplifier schemes today is unlikely to bring sufficient improvements. A new CMOS front-end gain stage topology with very low power consumption called regenerative current mirror is developed to fulfill the demand. The circuit takes advantage of high-speed performance of current amplification while operating with relatively low bias current. The regenerative current mirror uses a NMOS current mirror and a PMOS current mirror, both with nominal gain of 1, to form a loop-back topology that provides a positive feedback. An NMOS FET with an external adjustable voltage applied to it gate terminal is used to limit open loop gain of the current mirrors to be slightly lower than 1. This yields a net gain of the positive feedback loop to be much larger than 1 while operating the current mirrors under relatively low bias currents. Simulation shows that in 65 nm fabrication process, the power consumption of the gain stages suitable for silicon pixel detectors can be controlled < 10 micro-Watts per channel. Another novel low-power circuit called Pseudo-Thyristor presented in another document will replace traditional discriminator and the Regenerative Current Mirror plus Pseudo- Thyristor will provide a full solution for the silicon pixel low-power frontend ASIC.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2020

A Sub-Threshold Low-Power Integrated Bandpass Filter for Highly-Integrated Spectrum Analyzers

Low-power analog filter banks provide frequency analysis with minimal power and space requirements, making them viable solutions for integrated remote audio- and vibration-sensing applications. Compared with their digital counterparts, analog filter banks are better suited to achieve the lower power consumption necessary for IoT applications, while maintaining high dynamic range and a wide operational frequency range. In this work, the design and implementation of a sub-threshold complementary metal-oxide semiconductor (CMOS) integrated low-power tunable analog filter channel for signal spectrum analysis and signal discrimination is presented. Project specifications required a programmable, high-order, monolithic bandpass filter channel with small chip area, low power consumption, high dynamic range, and wide operational frequency range. The 8th-order filter channel presented in this work provides an effective Q-factor of 4.5 and a minimum dynamic range (DR) of approximately 85 dB, while allowing for tuning across a range of center frequencies from 2 kHz to 100 kHz, with power consumption of a single 8th-order filter channel measured at 256 µW nominally at the highest center frequency. An integrated analog Gm-C filter topology was selected for this application. Functionally, the high-Q bandpass filter transfer function is implemented via four cascaded 2nd-order filter cells, resulting in a single 8th-order filter channel, fabricated in 130-nm 1.2-V CMOS technology, suitable for use in monolithic integrated spectral analysis (MISA1) applications.

Long, Gavin B.↗
DOE OSTI2025

FPGA-accelerated SpeckleNN with SNL for real-time X-ray single-particle imaging

We present the implementation of a specialized version of our previously published unified embedding model, SpeckleNN, for real-time speckle pattern classification in X-ray Single-Particle Imaging (SPI), using the SLAC Neural Network Library (SNL) on an FPGA platform. This hardware realization transitions SpeckleNN from a prototypic model into a practical edge solution, optimized for running inference near the detector in high-throughput X-ray free-electron laser (XFEL) facilities, such as those found at the Linac Coherent Light Source (LCLS). To address the resource constraints inherent in FPGAs, we developed a more specialized version of SpeckleNN. The original model, which was designed for broader classification across multiple biological samples, comprised ~5.6 million parameters. The new implementation, while reducing the parameter count to 64.6K (a 98.8% reduction), focuses on maintaining the model's essential functionality for real-time operation, achieving an accuracy of 90%. Furthermore, we compressed the latent space from 128 to 50 dimensions. This implementation was demonstrated on the KCU1500 FPGA board, utilizing 71% of available DSPs, 75% of LUTs, and 48% of FFs, with an average power consumption of 9.4W according to the Vivado post-implementation report. The FPGA performed inference on a single image with a latency of 45.015 microseconds at a 200 MHz clock rate. In comparison, running the same inference on an NVIDIA A100 GPU resulted in an average power consumption of ~73W and an image processing latency of around 400 microseconds. Our FPGA-accelerated version of SpeckleNN demonstrated significant improvements, achieving an 8.9 × speedup and a 7.8 × reduction in power consumption compared to the GPU implementation. Key advancements include model specialization and dynamic weight loading through SNL, which eliminates the need for time-consuming FPGA design re-synthesis, allowing fast and continuous deployment of models (re)trained online. These innovations enable real-time adaptive classification and efficient vetoing of speckle patterns, making SpeckleNN more suited for deployment in XFEL facilities. This implementation has the potential to significantly accelerate SPI experiments and enhance adaptability to evolving experimental conditions.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

The Regenerative Current Mirror: A Very Low Power Front-End Amplifier for Silicon Pixel Detectors

In pixelized detectors, reducing power consumption in the front end ASIC chips becomes a crucial demand. Optimization based on mature pre-amplifier schemes today is unlikely to bring sufficient improvements. A new CMOS front-end gain stage topology with very low power consumption called regenerative current mirror is developed to fulfill the demand. The circuit takes advantage of high speed performance of current amplification while operating with relatively low bias current. The regenerative current mirror uses a NMOS current mirror and a PMOS current mirror, both with nominal gain of 1, to form a loop-back topology that provides a positive feedback. An NMOS FET with an external adjustable voltage applied to it gate terminal is used to limit open loop gain of the current mirrors to be slightly lower than 1. This yields a net gain of the positive feedback loop to be much larger than 1 while operating the current mirrors under relatively low bias currents. Simulation shows that in 65 nm fabrication process, the power consumption of the gain stages suitable for silicon pixel detectors can be controlled < 10 micro-Watts per channel.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Resilience Design Patterns: A Structured Approach to Resilience at Extreme Scale (V.2.0)

Reliability is a serious concern for future extreme-scale high-performance computing (HPC) systems. Projections based on the current generation of HPC systems and technology roadmaps suggest the prevalence of very high fault rates in future systems. The errors resulting from these faults will propagate and generate various kinds of failures, which may result in outcomes ranging from result corruptions to catastrophic application crashes. Therefore, the resilience challenge for extreme-scale HPC systems requires coordination between various hardware and software technologies that are capable of handling a broad set of fault models at accelerated fault rates. Also, due to practical limits on power consumption in future HPC systems, they are likely to embrace innovative architectures, increasing the levels of hardware and software complexities. Therefore, the techniques that seek to improve resilience must navigate the complex trade-off space between resilience and the overheads to power consumption and performance. While the HPC community has developed various resilience solutions, application-level techniques as well as system-based solutions, the solution space of HPC resilience techniques remains fragmented. There are no formal methods to integrate the various HPC resilience techniques into composite solutions, nor are there methods to holistically evaluate the adequacy and efficacy of such solutions in terms of their protection coverage, and their performance & power efficiency characteristics. Additionally, few implementations of current resilience solutions are portable to newer architectures and software environments that will be deployed on future systems. We developed a new structured approach to the management of HPC resilience using the concept of resilience-based design patterns. In general, a design pattern is a repeatable solution to a commonly occurring problem. We identified the well-known solutions that are commonly used to deal with faults, errors and failures in HPC systems. In the initial design patterns specification (version 1.0), we described the various solutions, which address specific problems in the design of resilient HPC environments, in the form of patterns. Each pattern describes a problem caused by a fault, error or failure event in an HPC environment, and then describes the core of the solution of the problem in such a way that this solution may be adapted to different systems and implemented at different layers of the system stack. The catalog of these resilience design patterns provides designers with a collection of design elements. To construct complete resilience solutions using combinations of various patterns, we defined a framework that enhances HPC designers' understanding of the important constraints and the opportunities for the design patterns to be implemented and deployed at various layers of the system stack. The design framework is also useful for establishing interfaces and mechanisms to coordinate flexible fault management across hardware and software components, as well as to consider the trade-off between performance, resilience, and power consumption when constructing a solution. The resilience design patterns specification version 1.1 included more detailed explanations of the pattern solutions, the context in which the patterns are applicable, and the implications for hardware or software design. It also provided several additional examples and detailed case studies to demonstrate the use of patterns to build realistic solutions. In version 1.2 of the specification document, we have improved the pattern descriptions, including graphical representations of the pattern components. These improvements are largely based on critical comments, feedback and suggestions received from pattern experts and readers of the previous versions of the specification. The pattern classification has been modified to further clarify the relationships between pattern categories. This version of the specification also introduces a pattern language for resilience design patterns. The pattern language presents the patterns in the catalog as a network, revealing the relations among the resilience patterns. The language provides designers with the means to explore alternative techniques for handling a specific fault model that may have different efficiency and complexity characteristics. Using the pattern language also enables the design and implementation of comprehensive resilience solutions as a set of interconnected resilience patterns that can be instantiated across layers of the system stack. The overall goal of this work is to provide hardware and software designers, as well as the users and operators of HPC systems, a systematic methodology for the design and evaluation of resilience technologies in HPC systems that keep scientific applications running to a correct solution in a timely and cost-efficient manner despite frequent faults, errors, and failures of various types. Version 2.0 expands the resilience design pattern classification and catalog to include self-stabilization patterns and reliability, availability and performance models for each structural pattern.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1999

Demonstration of an Ultra-Short Channel Metal Monolith Catalytic Reactor for Trace Contaminant Control Applications

The International Space Station (ISS) Trace Contaminant Control Subassembly (TCCS) design is based upon proven, highly reliable technology. However, because its core unit operations rely upon expendable activated charcoal and an indirectly heated high temperature catalyst, annual logistics mass, crew time, and power consumption requirements are significant. To address this situation, a unique catalytic reactor design has been developed which is suitable for retrofit into the TCCS's high temperature catalytic oxidizer (HTCO) assembly. The unique design, which employs a metallic, ultra-short channel length monolith (USCM) catalyst substrate, was tested in a flight-like TCCS HTCO assembly to investigate its performance characteristics. Test results indicate that retrofitting the TCCS with a USCM-based catalytic reactor is feasible and that it may provide significant reductions in logistics mass, crew time, and power consumption. Savings indicated by test results are up to 81% for annual logistics, 56% for crew time, and 77% for startup transient duration. In addition, its demonstrated ability to operate in a power saving mode provides up to a 43% savings in average power consumption. A summary of the USCM demonstration test objectives, approach, results, and specific benefits to the TCCS's process economics are presented,

Perry, J. L↗
NASA NTRS2000

Highly Parallel Computing Architectures by using Arrays of Quantum-dot Cellular Automata (QCA): Opportunities, Challenges, and Recent Results

There has been significant improvement in the performance of VLSI devices, in terms of size, power consumption, and speed, in recent years and this trend may also continue for some near future. However, it is a well known fact that there are major obstacles, i.e., physical limitation of feature size reduction and ever increasing cost of foundry, that would prevent the long term continuation of this trend. This has motivated the exploration of some fundamentally new technologies that are not dependent on the conventional feature size approach. Such technologies are expected to enable scaling to continue to the ultimate level, i.e., molecular and atomistic size. Quantum computing, quantum dot-based computing, DNA based computing, biologically inspired computing, etc., are examples of such new technologies. In particular, quantum-dots based computing by using Quantum-dot Cellular Automata (QCA) has recently been intensely investigated as a promising new technology capable of offering significant improvement over conventional VLSI in terms of reduction of feature size (and hence increase in integration level), reduction of power consumption, and increase of switching speed. Quantum dot-based computing and memory in general and QCA specifically, are intriguing to NASA due to their high packing density (10(exp 11) - 10(exp 12) per square cm ) and low power consumption (no transfer of current) and potentially higher radiation tolerant. Under Revolutionary Computing Technology (RTC) Program at the NASA/JPL Center for Integrated Space Microelectronics (CISM), we have been investigating the potential applications of QCA for the space program. To this end, exploiting the intrinsic features of QCA, we have designed novel QCA-based circuits for co-planner (i.e., single layer) and compact implementation of a class of data permutation matrices, a class of interconnection networks, and a bit-serial processor. Building upon these circuits, we have developed novel algorithms and QCA-based architectures for highly parallel and systolic computation of signal/image processing applications, such as FFT and Wavelet and Wlash-Hadamard Transforms.

Fijany, Amir↗