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At least 73 records · Page 4

NASA Tech Briefs, October 2008

Topics covered include: Control Architecture for Robotic Agent Command and Sensing; Algorithm for Wavefront Sensing Using an Extended Scene; CO2 Sensors Based on Nanocrystalline SnO2 Doped with CuO; Improved Airborne System for Sensing Wildfires; VHF Wide-Band, Dual-Polarization Microstrip-Patch Antenna; Onboard Data Processor for Change-Detection Radar Imaging; Using LDPC Code Constraints to Aid Recovery of Symbol Timing; System for Measuring Flexing of a Large Spaceborne Structure; Integrated Formation Optical Communication and Estimation System; Making Superconducting Welds between Superconducting Wires; Method for Thermal Spraying of Coatings Using Resonant-Pulsed Combustion; Coating Reduces Ice Adhesion; Hybrid Multifoil Aerogel Thermal Insulation; SHINE Virtual Machine Model for In-flight Updates of Critical Mission Software; Mars Image Collection Mosaic Builder; Providing Internet Access to High-Resolution Mars Images; Providing Internet Access to High-Resolution Lunar Images; Expressions Module for the Satellite Orbit Analysis Program Virtual Satellite; Small-Body Extensions for the Satellite Orbit Analysis Program (SOAP); Scripting Module for the Satellite Orbit Analysis Program (SOAP); XML-Based SHINE Knowledge Base Interchange Language; Core Technical Capability Laboratory Management System; MRO SOW Daily Script; Tool for Inspecting Alignment of Twinaxial Connectors; An ATP System for Deep-Space Optical Communication; Polar Traverse Rover Instrument; Expert System Control of Plant Growth in an Enclosed Space; Detecting Phycocyanin-Pigmented Microbes in Reflected Light; DMAC and NMP as Electrolyte Additives for Li-Ion Cells; Mass Spectrometer Containing Multiple Fixed Collectors; Waveguide Harmonic Generator for the SIM; Whispering Gallery Mode Resonator with Orthogonally Reconfigurable Filter Function; Stable Calibration of Raman Lidar Water-Vapor Measurements; Bimaterial Thermal Compensators for WGM Resonators; Root Source Analysis/ValuStream[Trade Mark] - A Methodology for Identifying and Managing Risks; Ensemble: an Architecture for Mission-Operations Software; Object Recognition Using Feature-and Color-Based Methods; On-Orbit Multi-Field Wavefront Control with a Kalman Filter; and The Interplanetary Overlay Networking Protocol Accelerator.

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NASA Tech Briefs, February 2011

Topics covered include: Multi-Segment Radius Measurement Using an Absolute Distance Meter Through a Null Assembly; Fiber-Optic Magnetic-Field-Strength Measurement System for Lightning Detection; Photocatalytic Active Radiation Measurements and Use; Computer Generated Hologram System for Wavefront Measurement System Calibration; Non-Contact Thermal Properties Measurement with Low-Power Laser and IR Camera System; SpaceCube 2.0: An Advanced Hybrid Onboard Data Processor; CMOS Imager Has Better Cross-Talk and Full-Well Performance; High-Performance Wireless Telemetry; Telemetry-Based Ranging; JWST Wavefront Control Toolbox; Java Image I/O for VICAR, PDS, and ISIS; X-Band Acquisition Aid Software; Antimicrobial-Coated Granules for Disinfecting Water; Range 7 Scanner Integration with PaR Robot Scanning System; Methods of Antimicrobial Coating of Diverse Materials; High-Operating-Temperature Barrier Infrared Detector with Tailorable Cutoff Wavelength; A Model of Reduced Kinetics for Alkane Oxidation Using Constituents and Species for N-Heptane; Thermally Conductive Tape Based on Carbon Nanotube Arrays; Two Catalysts for Selective Oxidation of Contaminant Gases; Nanoscale Metal Oxide Semiconductors for Gas Sensing; Lightweight, Ultra-High-Temperature, CMC-Lined Carbon/Carbon Structures; Sample Acquisition and Handling System from a Remote Platform; Improved Rare-Earth Emitter Hollow Cathode; High-Temperature Smart Structures for Engine Noise Reduction and Performance Enhancement; Cryogenic Scan Mechanism for Fourier Transform Spectrometer; Piezoelectric Rotary Tube Motor; Thermoelectric Energy Conversion Technology for High-Altitude Airships; Combustor Computations for CO2-Neutral Aviation; Use of Dynamic Distortion to Predict and Alleviate Loss of Control; Cycle Time Reduction in Trapped Mercury Ion Atomic Frequency Standards; and A (201)Hg+ Comagnetometer for (199)Hg+ Trapped Ion Space Atomic Clocks.

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Non Radiation Hardened Microprocessors in Spaced Based Remote Sensing Systems

The CALIPSO (Cloud-Aerosol Lidar and Infrared Pathfinder Satellite Observations) mission is a comprehensive suite of active and passive sensors including a 20Hz 230mj Nd:YAG lidar, a visible wavelength Earth-looking camera and an imaging infrared radiometer. CALIPSO flies in formation with the Earth Observing System Post-Meridian (EOS PM) train, provides continuous, near-simultaneous measurements and is a planned 3 year mission. CALIPSO was launched into a 98 degree sun synchronous Earth orbit in April of 2006 to study clouds and aerosols and acquires over 5 gigabytes of data every 24 hours. The ground track of one CALIPSO orbit as well as high and low intensity South Atlantic Anomaly outlines is shown. CALIPSO passes through the SAA several times each day. Spaced based remote sensing systems that include multiple instruments and/or instruments such as lidar generate large volumes of data and require robust real-time hardware and software mechanisms and high throughput processors. Due to onboard storage restrictions and telemetry downlink limitations these systems must pre-process and reduce the data before sending it to the ground. This onboard processing and realtime requirement load may mean that newer more powerful processors are needed even though acceptable radiation-hardened versions have not yet been released. CALIPSO's single board computer payload controller processor is actually a set of four (4) voting non-radiation hardened COTS Power PC 603r's built on a single width VME card by General Dynamics Advanced Information Systems (GDAIS). Significant radiation concerns for CALIPSO and other Low Earth Orbit (LEO) satellites include the South Atlantic Anomaly (SAA), the north and south poles and strong solar events. Over much of South America and extending into the South Atlantic Ocean the Van Allen radiation belts dip to just 200-800km and spacecraft entering this area are subjected to high energy protons and experience higher than normal Single Event Upset (SEU) and Single Event Latch-up (SEL) rates. Although less significant, spacecraft flying in the area around the poles experience similar upsets. Finally, powerful solar proton events in the range of 10MeV/10pfu to 100MeV/1pfu as are forecasted and tracked by NOAA's Space Environment Center in Colorado can result in Single Event Upset (SEU), Single Event Latch-up (SEL) and permanent failures such as Single Event Gate Rupture (SEGR) in some technologies. (Galactic Cosmic Rays (GCRs) are another source, especially for gate rupture) CALIPSO mitigates common radiation concerns in its data handling through the use of redundant processors, radiation-hardened Application Specific Integrated Circuits (ASIC), hardware-based Error Detection and Correction (EDAC), processor and memory scrubbing, redundant boot code and mirrored files. After presenting a system overview this paper will expand on each of these strategies. Where applicable, related on-orbit data collected since the CALIPSO initial boot on May 4, 2006 will be noted.

Decoursey, Robert J.

Simulating and Detecting Radiation-Induced Errors for Onboard Machine Learning

Spacecraft processors and memory are subjected to high radiation doses and therefore employ radiation-hardened components. However, these components are orders of magnitude more expensive than typical desktop components, and they lag years behind in terms of speed and size. We have integrated algorithm-based fault tolerance (ABFT) methods into onboard data analysis algorithms to detect radiation-induced errors, which ultimately may permit the use of spacecraft memory that need not be fully hardened, reducing cost and increasing capability at the same time. We have also developed a lightweight software radiation simulator, BITFLIPS, that permits evaluation of error detection strategies in a controlled fashion, including the specification of the radiation rate and selective exposure of individual data structures. Using BITFLIPS, we evaluated our error detection methods when using a support vector machine to analyze data collected by the Mars Odyssey spacecraft. We found ABFT error detection for matrix multiplication is very successful, while error detection for Gaussian kernel computation still has room for improvement.

data analysis

NASA Tech Briefs, December 2011

Topics covered include: 1) SNE Industrial Fieldbus Interface; 2) Composite Thermal Switch; 3) XMOS XC-2 Development Board for Mechanical Control and Data Collection; 4) Receiver Gain Modulation Circuit; 5) NEXUS Scalable and Distributed Next-Generation Avionics Bus for Space Missions; 6) Digital Interface Board to Control Phase and Amplitude of Four Channels; 7) CoNNeCT Baseband Processor Module; 8) Cryogenic 160-GHz MMIC Heterodyne Receiver Module; 9) Ka-Band, Multi-Gigabit-Per-Second Transceiver; 10) All-Solid-State 2.45-to-2.78-THz Source; 11) Onboard Interferometric SAR Processor for the Ka-Band Radar Interferometer (KaRIn); 12) Space Environments Testbed; 13) High-Performance 3D Articulated Robot Display; 14) Athena; 15) In Situ Surface Characterization; 16) Ndarts; 17) Cryo-Etched Black Silicon for Use as Optical Black; 18) Advanced CO2 Removal and Reduction System; 19) Correcting Thermal Deformations in an Active Composite Reflector; 20) Umbilical Deployment Device; 21) Space Mirror Alignment System; 22) Thermionic Power Cell To Harness Heat Energies for Geothermal Applications; 23) Graph Theory Roots of Spatial Operators for Kinematics and Dynamics; 24) Spacesuit Soft Upper Torso Sizing Systems; 25) Radiation Protection Using Single-Wall Carbon Nanotube Derivatives; 26) PMA-PhyloChip DNA Microarray to Elucidate Viable Microbial Community Structure; 27) Lidar Luminance Quantizer; 28) Distributed Capacitive Sensor for Sample Mass Measurement; 29) Base Flow Model Validation; 30) Minimum Landing Error Powered-Descent Guidance for Planetary Missions; 31) Framework for Integrating Science Data Processing Algorithms Into Process Control Systems; 32) Time Synchronization and Distribution Mechanisms for Space Networks; 33) Local Estimators for Spacecraft Formation Flying; 34) Software-Defined Radio for Space-to-Space Communications; 35) Reflective Occultation Mask for Evaluation of Occulter Designs for Planet Finding; and 36) Molecular Adsorber Coating

Source record

Aircraft on-board SAR processing using a frequency-domain fast correlation technique

The design of a frequency-domain fast correlation processor for aircraft onboard synthetic-aperture radar (SAR) applications is described. The design uses the fast Fourier transform (FFT) fast correlation technique to perform both range and azimuth pulse compression functions for the NASA/JPL L-band, quad-polarization airborne SAR. The subject processor is computationally efficient and requires a simple control unit. It is capable of producing single-look, 8-m (slant range) by 10-m (azimuth) resolution, SAR images of a selected polarization over a swath width of up to 15 km in real time onboard the aircraft.

Liu, Kuang Y.

Autonomous Flight Safety System

Autonomous Flight Safety System (AFSS) is an independent flight safety system designed for small to medium sized expendable launch vehicles launching from or needing range safety protection while overlying relatively remote locations. AFSS replaces the need for a man-in-the-loop to make decisions for flight termination. AFSS could also serve as the prototype for an autonomous manned flight crew escape advisory system. AFSS utilizes onboard sensors and processors to emulate the human decision-making process using rule-based software logic and can dramatically reduce safety response time during critical launch phases. The Range Safety flight path nominal trajectory, its deviation allowances, limit zones and other flight safety rules are stored in the onboard computers. Position, velocity and attitude data obtained from onboard global positioning system (GPS) and inertial navigation system (INS) sensors are compared with these rules to determine the appropriate action to ensure that people and property are not jeopardized. The final system will be fully redundant and independent with multiple processors, sensors, and dead man switches to prevent inadvertent flight termination. AFSS is currently in Phase III which includes updated algorithms, integrated GPS/INS sensors, large scale simulation testing and initial aircraft flight testing.

Ferrell, Bob

Thinking Like a Human

Accurate Automation Corporation (AAC) of Chattanooga, TN, developed a neural network processor (NNP) for use onboard the NASA- and Air Force-sponsored LoFLYTE aircraft. The processor is modeled after connections in the brain.

Source record

Spacecraft technology

Developments in spacecraft technology are discussed with emphasis on the Explorer satellite program. The subjects considered include the following: (1) nutational behavior of the Explorer-45 satellite, (2) panoramic sensor development, (3) onboard camera signal processor for Explorer satellites, and (4) microcircuit development. Information on the zero gravity testing of heat pipes is included. Procedures for cleaning heat treated aluminum heat pipes are explained. The development of a five-year magnetic tape, an accurate incremental angular encoder, and a blood freezing apparatus for leukemia research are also discussed.

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Spaceborne radar measurement of wind velocity over the ocean - An overview of the NSCAT scatterometer system

Scatterometry and scatterometer design issues are reviewed. The design of the NASA Scatterometer (NSCAT) to be flown on the Japanese ADEOS mission is presented. Building on Seasat experience, the NSCAT system includes several enhancements, such as three antenna azimuths in each of two swaths, and an onboard digital Doppler processor to allow backscatter measurements to be colocated everywhere within the orbit. These enhancements will greatly increase the quality of the NSCAT wind data. The ground processing of data is discussed, and scatterometers of the next decade are briefly described.

Naderi, F. M.

Fault tolerant onboard packet switch architecture for communication satellites: Shared memory per beam approach

The NASA Lewis Research Center is developing a multichannel communication signal processing satellite (MCSPS) system which will provide low data rate, direct to user, commercial communications services. The focus of current space segment developments is a flexible, high-throughput, fault tolerant onboard information switching processor. This information switching processor (ISP) is a destination-directed packet switch which performs both space and time switching to route user information among numerous user ground terminals. Through both industry study contracts and in-house investigations, several packet switching architectures were examined. A contention-free approach, the shared memory per beam architecture, was selected for implementation. The shared memory per beam architecture, fault tolerance insertion, implementation, and demonstration plans are described.

Shalkhauser, Mary JO

Modeling of the ground-to-SSFMB link networking features using SPW

This report describes the modeling and simulation of the networking features of the ground-to-Space Station Freedom manned base (SSFMB) link using COMDISCO signal processing work-system (SPW). The networking features modeled include the implementation of Consultative Committee for Space Data Systems (CCSDS) protocols in the multiplexing of digitized audio and core data into virtual channel data units (VCDU's) in the control center complex and the demultiplexing of VCDU's in the onboard baseband signal processor. The emphasis of this work has been placed on techniques for modeling the CCSDS networking features using SPW. The objectives for developing the SPW models are to test the suitability of SPW for modeling networking features and to develop SPW simulation models of the control center complex and space station baseband signal processor for use in end-to-end testing of the ground-to-SSFMB S-band single access forward (SSAF) link.

Watson, John C.

Commercial Off-The-Shelf GPU Qualification for Space Applications

With increased sensor data rates, and limited downlink capability, NASA missions have increased demands for onboard processing for applications ranging from synthetic aperture radar (SAR) data reduction to hyperspectral image processing and recognition, and even artificial intelligence (AI). Graphics Processor Units (GPUs) offer an attractive processing architecture for many of the applications due to their massive parallelism. As no radiation hardened GPU devices currently exist, any near term GPU-based onboard processors must use commercially available devices. To address this need NASA GSFC is collaborating with Cubic Aerospace Incorporated to, (a) characterize the capability of GPUs to meet the demands of a candidate onboard processing application, thereby demonstrating their ability to improve mission performance, reduce spacecraft SWaP, and potentially enable new missions, and (b) evaluate the radiation tolerance of capable COTS GPU devices to determine their suitability for spaceflight applications and understand any mitigations that are needed. A candidate onboard processing image has been prototyped and evaluated on a commercial GPU board and has demonstrated significantly increased processing throughput. Radiation tests for commercial GPU devices are planned for early fiscal year 2019.

Onboard processing

Weather information network including graphical display

An apparatus for providing weather information onboard an aircraft includes a processor unit and a graphical user interface. The processor unit processes weather information after it is received onboard the aircraft from a ground-based source, and the graphical user interface provides a graphical presentation of the weather information to a user onboard the aircraft. Preferably, the graphical user interface includes one or more user-selectable options for graphically displaying at least one of convection information, turbulence information, icing information, weather satellite information, SIGMET information, significant weather prognosis information, and winds aloft information.

Leger, Daniel R.

FPGA Coprocessor for Accelerated Classification of Images

An effort related to that described in the preceding article focuses on developing a spaceborne processing platform for fast and accurate onboard classification of image data, a critical part of modern satellite image processing. The approach again has been to exploit the versatility of recently developed hybrid Virtex-4FX field-programmable gate array (FPGA) to run diverse science applications on embedded processors while taking advantage of the reconfigurable hardware resources of the FPGAs. In this case, the FPGA serves as a coprocessor that implements legacy C-language support-vector-machine (SVM) image-classification algorithms to detect and identify natural phenomena such as flooding, volcanic eruptions, and sea-ice break-up. The FPGA provides hardware acceleration for increased onboard processing capability than previously demonstrated in software. The original C-language program demonstrated on an imaging instrument aboard the Earth Observing-1 (EO-1) satellite implements a linear-kernel SVM algorithm for classifying parts of the images as snow, water, ice, land, or cloud or unclassified. Current onboard processors, such as on EO-1, have limited computing power, extremely limited active storage capability and are no longer considered state-of-the-art. Using commercially available software that translates C-language programs into hardware description language (HDL) files, the legacy C-language program, and two newly formulated programs for a more capable expanded-linear-kernel and a more accurate polynomial-kernel SVM algorithm, have been implemented in the Virtex-4FX FPGA. In tests, the FPGA implementations have exhibited significant speedups over conventional software implementations running on general-purpose hardware.

Pingree, Paula J.

Data compression for Eos on-board SAR processor

A lightweight, low-power, real-time data compressor design for the Earth Observing System (Eos) onboard synthetic aperture radar (SAR) processor is presented. The implementation is based on VLSI design of a pipelined binary tree-searched vector quantizer (VQ), utilizing space-qualifiable 1.25-micron CMOS technology. The implementation exploits VLSI system design principles such as the modularity, regular data flow, simple interconnection, localized communication, simple global control, and parallel/pipelined processing. The overall system requires 30 chips with only one VLSI processing element design. The total weight is about 1.2 lbs, with an estimated power dissipation of approximately 4 watts operating at the maximum input data rate. The projected throughput rate exceeds 5 MHz.

Chang, C. Y.

Destination-directed, packet-switched architecture for a geostationary communications satellite network

A major goal of the Digital Systems Technology Branch at the NASA Lewis Research Center is to identify and develop critical digital components and technologies that either enable new commercial missions or significantly enhance the performance, cost efficiency, and/or reliability of existing and planned space communications systems. NASA envisions a need for low-data-rate, interactive, direct-to-the-user communications services for data, voice, facsimile, and video conferencing. The network would provide enhanced very-small-aperture terminal (VSAT) communications services and be capable of handling data rates of 64 kbps through 2.048 Mbps in 64-kbps increments. Efforts have concentrated heavily on the space segment; however, the ground segment has been considered concurrently to ensure cost efficiency and realistic operational constraints. The focus of current space segment developments is a flexible, high-throughput, fault-tolerant onboard information-switching processor (ISP) for a geostationary satellite communications network. The Digital Systems Technology Branch is investigating both circuit and packet architectures for the ISP. Destination-directed, packet-switched architectures for geostationary communications satellites are addressed.

Ivancic, William D.