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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2018

Parallelized Kalman-Filter-Based Reconstruction of Particle Tracks on Many-Core Architectures

Faced with physical and energy density limitations on clock speed, contemporary microprocessor designers have increasingly turned to on-chip parallelism for performance gains. Algorithms should accordingly be designed with ample amounts of fine-grained parallelism if they are to realize the full performance of the hardware. This requirement can be challenging for algorithms that are naturally expressed as a sequence of small-matrix operations, such as the Kalman filter methods widely in use in high-energy physics experiments. In the High-Luminosity Large Hadron Collider (HL-LHC), for example, one of the dominant computational problems is expected to be finding and fitting charged-particle tracks during event reconstruction; today, the most common track-finding methods are those based on the Kalman filter. Experience at the LHC, both in the trigger and offline, has shown that these methods are robust and provide high physics performance. Previously we reported the significant parallel speedups that resulted from our efforts to adapt Kalman-filter-based tracking to many-core architectures such as Intel Xeon Phi. Here we report on how effectively those techniques can be applied to more realistic detector configurations and event complexity.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Contact-Less Integrity Verification of Microelectronics Using Near-Field EM Analysis

Modern microelectronics life-cycle and supply chain ecosystem bring multiple untrusted entities, which can compromise their integrity. A major integrity issue of microelectronics stems from piracy of intellectual properties (IP) and counterfeiting, which causes significant revenue loss to the semiconductor manufacturers. Further, these components often lead to compromised functionality, reliability, security, and safety of an electronic system. This paper presents secure information transmission and probing methods for verifying the integrity of digital integrated circuit (ICs) based on their electromagnetic (EM) near-field emissions and thereby protecting systems against counterfeit components. The proposed method has been tested on both high-level instructions executed by microprocessors or Systems-on-Chip (serving as examples of software), and also logic circuits within FPGA fabrics and ASICs (serving as examples of hardware). The authentication information required by each digital system is generated using a pseudo-random number generator circuit and securely transmitted via near-field magnetic emissions. The authorized party can probe these emissions using a near-field probe, process the acquired signals to improve the signal-to-noise ratio (SNR), and then recover the secure information through matched filtering. Experimental results from commercial SoCs are used to demonstrate the proposed technique. Methods for reducing EM interference during integrity verification of both FPGAs and ASICs are also described.

47 OTHER INSTRUMENTATION↗
DOE OSTI2018

High-Level Simulation for Spiking Neuromorphic Computing Systems

Neuromorphic computing systems are alternatives to conventional microprocessors, often built from unconventional hardware. Designing and evaluating these systems requires multiple levels of simulation, from the device level to the circuit level to the system level. In this paper, we describe the system level simulator of a neuromorphic computing system based on memristors. We compare it to a circuit level simulator of the same system, both verifying its accuracy and demonstrating its performance improvement. We argue that system level simulation is an essential part of the design process of neuromorphic systems.

Skuda, Nicholas↗
DOE OSTI2020

An 85 nW IoT Node-Controlling SoC for MELs Power-Mode Management and Phantom Energy Reduction

This paper presents an ultra-low power (ULP) node-controlling system-on-chip (SoC) used for power-mode management and phantom energy reduction of miscellaneous electric loads (MELs). The SoC is powered from a single 2.5 V voltage supply enabled by the integrated power management unit (PMU) and can control up to 16 MELs due to the on-chip 16-channel correlator and the 32b RISC-V microprocessor. To further reduce the system power consumption, two clock domains have been adopted for the correlator and the processor separately. Fabricated in 65-nm CMOS, the measured minimum power consumption of the proposed SoC is only 85 nW at 0.45 V voltage supply and 1 kHz clock frequency. The measured maximum operating frequency can go up to 148 kHz with a 0.55 V supply. An application experiment successfully demonstrates that the SoC controls the power modes of MELs from wake-up to cut-off to save the average power and phantom energy.

power-mode management, phantom energy, phantom pow↗
DOE OSTI2024

Development of a Hybrid Single/Two-Phase Capillary-Based Micro-Cooler using Copper Inverse Opals Wick with Silicon 3D Manifold for High-Heat-Flux Cooling Application

Previously, we reported two-phase capillary-based cooling using narrow (200 to 1000 ..mu..m) heater bridge copper inverse opal (CIO) wicks with heat flux level of 1400 Wcm -2 and superheat ~ 10 degrees C. Here, we demonstrate the area scaling of the proposed technology to a large-area micro-cooler for high-heat-flux cooling of microprocessors and power electronics. We developed a hybrid single/two-phase micro-cooler that relies on capillary-wicking in a 25-..mu..m-thick CIO with an open silicon microchannel 3D-manifold for liquid delivery and vapor extraction, achieving a high heat flux ~ 400 Wcm -2 over a heated area of 10 x 10 mm 2 . For a range of inlet water flowrates from 5 to 60 g(min) -1 , we achieved total thermal resistances and vapor qualities of 0.68 cm 2 degrees CW -1 to 0.2 cm 2 degrees CW -1 and 0.55 to 0.12, respectively. The flowrates are 10x smaller than those of conventional single- or two-phase microchannel cooling technology. The corresponding two-phase thermal resistances ranges from 0.05 to 0.02 cm 2 degrees CW -1 with temperature superheat of 8 to 6 degrees C, respectively. While the overall performance of the large-area (10 x 10 mm 2 ) capillary-based micro-cooler degraded compared to the previous demonstration of the technology for a heated area of 5 x 5 mm 2 , however, preliminary CFD modeling indicates that an improved manifold design will be able to achieve comparable performance.

capillary flow↗
DOE OSTI2018

Accelerated Architectures Create Programming Opportunities

In the early 2000s, industry switched to multicore microprocessors to address semiconductors' speed and power limits. However, the change was unsuccessful, leading to dire claims that “Moore's law is ending.” In conclusion, this column suggests that while the approach was sound, it needed a deeper architectural transformation. Industry has since discovered a suitable architecture, but work remains on software to support it.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

ByzSec — A Multi-layered Byzantine Resilient Architecture for Bulk Power System Protective Relays

Reliability, selectivity, and sensitivity are the fundamental attributes of any protection system, acting as the main drivers in the selection of schemes, and equipment. In high-voltage systems, microprocessor-based relays represent the industry’s preferred solution, providing engineers with a vast array of benefits. However, they remain vulnerable to cybersecurity events that may compromise their functionality. To help mitigate against potential cybersecurity risks, this paper presents a fault-tolerant, Byzantine Resilient (BR) architecture that significantly increases the cybersecurity attributes of a protection system while minimizing the amount of performance impacts and integration overheads introduced. The solution relies on an array of independent relays that utilize robust consensus methods (based on Spire [1], [2]) to ensure correct system behavior is achieved even when a relay has been compromised. Furthermore, the solution has been complemented with a custom-built Situational Awareness engine that can be used to detect and identify potential threats. The implemented solution has been developed in consultation with three hardware vendors and has been tested to comply with the performance requirements of a 345kV differential protection scheme (87T). The results indicate that the proposed architecture is a comprehensive solution that: supports the strict correctness and performance requirements of the bulk power grid while providing a cost-effective alternative that offers a seamless, long-term solution.

byzantine security, Fault Tolerant Application Sof↗
DOE OSTI2026

Development and Evaluation of a Cost-Effective Behind-the-Meter Synchronized Measurement Unit for Enhanced Grid Integration

This paper presents the development of the Inverter Based Resource Monitor (IBRM), an innovative behind-the-meter synchronized measurement unit (SMU) tailored for integration with inverter-based resources (IBRs). The IBRM distinguishes itself as a highly accurate and cost-effective SMU, offering facile deployment and connectivity to IBRs. It is equipped to conduct real-time voltage and current waveform analyses, serving as a phasor measurement unit (PMU) with exceptionally rapid synchrophasor transmission capabilities. The device incorporates a cutting-edge dual-core architecture designed to minimize sampling delays inherent to its microprocessor, thereby enhancing the precision of synchronized waveform measurements. Moreover, the IBRM is adept at recording high-fidelity waveform data, capturing nuances such as waveform distortions, high-order harmonics, and wide-band oscillations prevalent in power grids with substantial IBR presence. A prototype of the IBRM has been constructed and subjected to rigorous testing to assess its functional capabilities and measurement precision, utilizing both idealized signal generators and a real-world off-grid inverter setup as benchmarks.

Wu, Ori [ORNL] (ORCID:0000000326723410)↗
DOE OSTI2021

Multiscale System Modeling of Single-Event-Induced Faults in Advanced Node Processors

Integration-technology feature shrink increases computing-system susceptibility to single-event effects (SEE). While modeling SEE faults will be critical, an integrated processor’s scope makes physically correct modeling computationally intractable. Without useful models, presilicon evaluation of fault-tolerance approaches becomes impossible. To incorporate accurate transistor-level effects at a system scope, we present a multiscale simulation framework. Charge collection at the 1) device level determines 2) circuit-level transient duration and state-upset likelihood. Circuit effects, in turn, impact 3) register-transfer-level architecture-state corruption visible at 4) the system level. Furthermore, the physically accurate effects of SEEs in large-scale systems, executed on a high-performance computing (HPC) simulator, could be used to drive cross-layer radiation hardening by design. We demonstrate the capabilities of this model with two case studies. First, we determine a D flip-flop’s sensitivity at the transistor level on 14-nm FinFet technology, validating the model against published cross sections. Second, we track and estimate faults in a microprocessor without interlocked pipelined stages (MIPS) processor for Adams 90% worst case environment in an isotropic space environment.

42 ENGINEERING↗
DOE OSTI2014

Adaptive prefetching on POWER7: Improving performance and power consumption

Hardware data prefetch engines are integral parts of many general purpose server-class microprocessors in the field today. Some prefetch engines allow users to change some of their parameters. But, the prefetcher is usually enabled in a default configuration during system bring-up, and dynamic reconfiguration of the prefetch engine is not an autonomic feature of current machines. Conceptually, however, it is easy to infer that commonly used prefetch algorithms—when applied in a fixed mode—will not help performance in many cases. In fact, they may actually degrade performance due to useless bus bandwidth consumption and cache pollution, which in turn, will also waste power. We present an adaptive prefetch scheme that dynamically modifies the prefetch settings in order to adapt to workloads

adaptive system↗
DOE OSTI2016

Identifying the Root Causes of Wait States in Large-Scale Parallel Applications

Driven by growing application requirements and accelerated by current trends in microprocessor design, the number of processor cores on modern supercomputers is increasing from generation to generation. However, load or communication imbalance prevents many codes from taking advantage of the available parallelism, as delays of single processes may spread wait states across the entire machine. Moreover, when employing complex point-to-point communication patterns, wait states may propagate along far-reaching cause-effect chains that are hard to track manually and that complicate an assessment of the actual costs of an imbalance. Building on earlier work by Meira Jr. et al., we present a scalable approach that identifies program wait states and attributes their costs in terms of resource waste to their original cause. Ultimately, by replaying event traces in parallel both forward and backward, we can identify the processes and call paths responsible for the most severe imbalances even for runs with hundreds of thousands of processes.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

C3PU:Real-Time Predictive Charge Control Software for Battery Management Systems (Code for Charge Control and Predictive Unit) [SWR-21-48]

C3PU sets up a model predictive control formulation for the optimal charging control of battery packs and can be deployed for real-time operation on an embedded microprocessor. C3PU uses electrochemical and thermal models of battery packs to predict the charging trajectories of the battery pack over a time horizon under different operating conditions. It then selects the optimal charging trajectory such that a pre-defined objective is minimized, which in the present state of the code is to minimize the charging duration of the battery pack. The optimal charging trajectory is obtained by solving an underlying mathematical problem. However, C3PU is flexible to incorporate other charging objectives. The underlying battery models can be swapped as well, as long as they follow certain mathematical properties. Mathematically, optimal control problems (in this case, optimally controlling the charging current of the battery pack) are computationally expensive. C3PU implements advanced numerical techniques, namely pseudo-spectral optimization, to reduce the computational burden of the underlying problem to solve. This allows for the problem to be solved in real-time in an embedded system. Once the optimal charging trajectory is computed over a time horizon, C3PU can package such data and send it out via appropriate communication protocols.

Mishra, Partha↗
DOE OSTI2016

Image Processing Occupancy Sensor

The Image Processing Occupancy Sensor, or IPOS, is a novel sensor technology developed at the National Renewable Energy Laboratory (NREL). The sensor is based on low-cost embedded microprocessors widely used by the smartphone industry and leverages mature open-source computer vision software libraries. Compared to traditional passive infrared and ultrasonic-based motion sensors currently used for occupancy detection, IPOS has shown the potential for improved accuracy and a richer set of feedback signals for occupant-optimized lighting, daylighting, temperature setback, ventilation control, and other occupancy and location-based uses. Unlike traditional passive infrared (PIR) or ultrasonic occupancy sensors, which infer occupancy based only on motion, IPOS uses digital image-based analysis to detect and classify various aspects of occupancy, including the presence of occupants regardless of motion, their number, location, and activity levels of occupants, as well as the illuminance properties of the monitored space. The IPOS software leverages the recent availability of low-cost embedded computing platforms, computer vision software libraries, and camera elements.

Source record↗
DOE OSTI2014

Charging and Heating Dynamics of Nanoparticles in Nonthermal Plasmas

The focus of this award was to understand the interactions of nanometer-sized particles with ionized gases, also called plasmas. Plasmas are widely used in the fabrication of electronic circuits such as microprocessors and memory devices, in plasma display panels, as well as in medical applications. Recently, these ionized gases are finding applications in the synthesis of advanced nanomaterials with novel properties, which are based on nanometer-sized particulate (nanoparticles) building blocks. As these nanoparticles grow in the plasma environment, they interact with the plasmas species such as electrons and ions which critically determines the nanoparticle properties. The University of Minnesota researchers conducting this project performed numerical simulations and developed analytical models that described the interaction of plasma-bound nanoparticles with the plasma ions. The plasma ions bombard the nanoparticle surface with substantial energy, which can result in the rearrangement of the nanoparticles’ atoms, giving them often desirable structures at the atomic scale. Being able to tune the ion energies allows to control the properties of nanoparticles produced in order to tailor their attributes for certain applications. For instance, when used in high efficiency light emitting devices, nanoparticles produced under high fluxes of highly energetic ions may show superior light emission to particles produced under low fluxes of less energetic ions. The analytical models developed by the University of Minnesota researchers enable the research community to easily determine the energy of ions bombarding the nanoparticles. The researchers extensively tested the validity of the analytical models by comparing them to sophisticated computer simulations based on stochastic particle modeling, also called Monte Carlo modeling, which simulated the motion of hundreds of thousands of ions and their interaction with the nanoparticle surfaces. Beyond the scientific intellectual merits, this award had significant broader impacts. Two graduate students received their doctoral degrees and both have joined a U.S. manufacturer of plasma-based semiconductor processing equipment. Four undergraduate students participated in research conducted under this grant and gained valuable hands-on laboratory experience. A middle school science teacher observed research conducted under this grant and developed three new course modules that introduce middle school students to the concepts of nanometer scale, the atomic structure of matter, and the composition of matter of different chemical elements.

42 ENGINEERING↗
DOE OSTI2014

Field Test of Boiler Primary Loop Temperature Controller

Beyond these initial system efficiency upgrades are an emerging class of Advanced Load Monitoring (ALM) aftermarket controllers that dynamically respond to the boiler load, with claims of 10% to 30% of fuel savings over a heating season. For hydronic boilers specifically, these devices perform load monitoring, with continuous measurement of supply and in some cases return water temperatures. Energy savings from these ALM controllers are derived from dynamic management of the boiler differential, where a microprocessor with memory of past boiler cycles prevents the boiler from firing for a period of time, to limit cycling losses and inefficient operation during perceived low load conditions. These differ from OTR controllers, which vary boiler setpoint temperatures with ambient conditions while maintaining a fixed differential. PARR installed and monitored the performance of one type of ALM controller, the M2G from Greffen Systems, at multifamily sites in the city of Chicago and its suburb Cary, IL, both with existing OTR control. Results show that energy savings depend on the degree to which boilers are over-sized for their load, represented by cycling rates. Also savings vary over the heating season with cycling rates, with greater savings observed in shoulder months. Over the monitoring period, over-sized boilers at one site showed reductions in cycling and energy consumption in line with prior laboratory studies, while less over-sized boilers at another site showed muted savings.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2013

Collective Memory Transfers for Multi-Core Chips

Future performance improvements for microprocessors have shifted from clock frequency scaling towards increases in on-chip parallelism. Performance improvements for a wide variety of parallel applications require domain-decomposition of data arrays from a contiguous arrangement in memory to a tiled layout for on-chip L1 data caches and scratchpads. How- ever, DRAM performance suffers under the non-streaming access patterns generated by many independent cores. We propose collective memory scheduling (CMS) that actively takes control of collective memory transfers such that requests arrive in a sequential and predictable fashion to the memory controller. CMS uses the hierarchically tiled arrays formal- ism to compactly express collective operations, which greatly improves programmability over conventional prefetch or list- DMA approaches. CMS reduces application execution time by up to 32% and DRAM read power by 2.2×, compared to a baseline DMA architecture such as STI Cell.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2014

Energy-aware Thread and Data Management in Heterogeneous Multi-core, Multi-memory Systems

By 2004, microprocessor design focused on multicore scaling—increasing the number of cores per die in each generation—as the primary strategy for improving performance. These multicore processors typically equip multiple memory subsystems to improve data throughput. In addition, these systems employ heterogeneous processors such as GPUs and heterogeneous memories like non-volatile memory to improve performance, capacity, and energy efficiency. With the increasing volume of hardware resources and system complexity caused by heterogeneity, future systems will require intelligent ways to manage hardware resources. Early research to improve performance and energy efficiency on heterogeneous, multi-core, multi-memory systems focused on tuning a single primitive or at best a few primitives in the systems. The key limitation of past efforts is their lack of a holistic approach to resource management that balances the tradeoff between performance and energy consumption. In addition, the shift from simple, homogeneous systems to these heterogeneous, multicore, multi-memory systems requires in-depth understanding of efficient resource management for scalable execution, including new models that capture the interchange between performance and energy, smarter resource management strategies, and novel low-level performance/energy tuning primitives and runtime systems. Tuning an application to control available resources efficiently has become a daunting challenge; managing resources in automation is still a dark art since the tradeoffs among programming, energy, and performance remain insufficiently understood. In this dissertation, I have developed theories, models, and resource management techniques to enable energy-efficient execution of parallel applications through thread and data management in these heterogeneous multi-core, multi-memory systems. I study the effect of dynamic concurrent throttling on the performance and energy of multi-core, non-uniform memory access (NUMA) systems. I use critical path analysis to quantify memory contention in the NUMA memory system and determine thread mappings. In addition, I implement a runtime system that combines concurrent throttling and a novel thread mapping algorithm to manage thread resources and improve energy efficient execution in multi-core, NUMA systems.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2014

Field Test of Boiler Primary Loop Temperature Controller

Beyond these initial system efficiency upgrades are an emerging class of Advanced Load Monitoring (ALM) aftermarket controllers that dynamically respond to the boiler load, with claims of 10% to 30% of fuel savings over a heating season. For hydronic boilers specifically, these devices perform load monitoring, with continuous measurement of supply and, in some cases, return water temperatures. Energy savings from these ALM controllers are derived from dynamic management of the boiler differential, where a microprocessor with memory of past boiler cycles prevents the boiler from firing for a period of time, to limit cycling losses and inefficient operation during perceived low load conditions. These differ from OTR controllers, which vary boiler setpoint temperatures with ambient conditions while maintaining a fixed differential.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗