Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “microelectronics reliability”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2018

Microstructure Evolution and Implications for Cu Nanointerconnects and Beyond

The continued scaling of Cu low k technology is facing serious challenges imposed by basic limits from materials, processing and reliability. This has generated great interests recently to further develop Cu nanointerconnects and alternates, particularly Co and Ru nanointerconnects beyond the 10nm node. The performance and reliability are important considerations for the development of nanointerconnects in addition to challenges from processing complexity and manufacturing cost. In this paper, we investigate the microstructure evolution in Cu, Co and Ru nanointerconnects and the effects on resistivity and electromigration (EM), two key factors contributing to the RC delay and reliability of the nanointerconnects.

36 MATERIALS SCIENCE↗
DOE OSTI2015

Effects of vacuum ultraviolet irradiation on trapped charges and leakage currents of low-k organosilicate dielectrics

Vacuum ultraviolet (VUV) photoemission spectroscopy is utilized to investigate the distribution of trapped charges within the bandgap of low dielectric constant (low-k) organosilicate (SiCOH) materials. It was found that trapped charges are continuously distributed within the bandgap of porous SiCOH and the center of the trapped states is 1.3 eV above the valence band of the tested sample. By comparing photoemission spectroscopic results before and after VUV exposure, VUV irradiation with photon energies between 7.6 and 8.9 eV was found to deplete trapped charge while UV exposure with photon energies less than 6.0 eV induces more trapped charges in tested samples. Current-Voltage (IV) characteristics results show that the reliability of dielectrics is improved after VUV irradiation with photon energies between 7.6 and 8.9 eV, while UV exposure results in an increased level of leakage current and a decreased breakdown voltage, both of which are harmful to the reliability of the dielectric. This work shows that VUV irradiation holds the potential to substitute for UV curing in microelectronic processing to improve the reliability of low-k dielectrics by mitigating the leakage currents and trapped charges induced by UV irradiation.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS2006

Design Parameters Influencing Reliability of CCGA Assembly: A Sensitivity Analysis

Area Array microelectronic packages with small pitch and large I/O counts are now widely used in microelectronics packaging. The impact of various package design and materials/process parameters on reliability has been studied through extensive literature review. Reliability of Ceramic Column Grid Array (CCGA) package assemblies has been evaluated using JPL thermal cycle test results (-50(deg)/75(deg)C, -55(deg)/100(deg)C, and -55(deg)/125(deg)C), as well as those reported by other investigators. A sensitivity analysis has been performed using the literature da to study the impact of design parameters and global/local stress conditions on assembly reliability. The applicability of various life-prediction models for CCGA design has been investigated by comparing model's predictions with the experimental thermal cycling data. Finite Element Method (FEM) analysis has been conducted to assess the state of the stress/strain in CCGA assembly under different thermal cycling, and to explain the different failure modes and locations observed in JPL test assemblies.

reliability↗
DOE OSTI2015

Modeling of single event transients with dual double-exponential current sources: Implications for logic cell characterization

Single event effects (SEE) are a reliability concern for modern microelectronics. Bit corruptions can be caused by single event upsets (SEUs) in the storage cells or by sampling single event transients (SETs) from a logic path. Likewise, an accurate prediction of soft error susceptibility from SETs requires good models to convert collected charge into compact descriptions of the current injection process. This paper describes a simple, yet effective, method to model the current waveform resulting from a charge collection event for SET circuit simulations. The model uses two double-exponential current sources in parallel, and the results illustrate why a conventional model based on one double-exponential source can be incomplete. Furthermore, a small set of logic cells with varying input conditions, drive strength, and output loading are simulated to extract the parameters for the dual double-exponential current sources. As a result, the parameters are based upon both the node capacitance and the restoring current (i.e., drive strength) of the logic cell.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS2012

3D X-ray CT for BGA/CGA Workmanship Defect Detection

Commercial-off-the-shelf (COTS) advanced microelectronic technologies in high-reliability versions are now being considered for use in a number of National Aeronautics and Space Administration (NASA) electronic systems. One of the key drawbacks of advanced electronic packages with hidden solder joint interconnections, such as the column grid array (CGA), is that inspection can be challenging—whether visually or using X-rays. In general, inspection for solder joint integrity is poor, except for identifying shorts. The new, advanced X-ray systems, especially the 3D computer tomography version, may be able to provide the three-dimensional features that are extremely difficult to resolve under the 2D systems.This report presents both 2D and 3D X-ray images along with their representative optical photomicrographs for a number of advanced electronics package assemblies including 3D stack and CGA assemblies before and after thermal cycling.

Ghaffarian, Reza↗
DOE OSTI2024

Covalently-Bonded Laminar Assembly of Van der Waals Semiconductors with Polymers: Toward High-Performance Flexible Devices

Van der Waals semiconductors (vdWS) offer superior mechanical and electrical properties and are promising for flexible microelectronics when combined with polymer substrates. However, the self-passivated vdWS surfaces and their weak adhesion to polymers tend to cause interfacial sliding and wrinkling, and thus, are still challenging the reliability of vdWS-based flexible devices. Here, in this study, an effective covalent vdWS–polymer lamination method with high stretch tolerance and excellent electronic performance is reported. Using molybdenum disulfide (MoS 2 ) and polydimethylsiloxane (PDMS) as a case study, gold–chalcogen bonding and mercapto silane bridges are leveraged. The resulting composite structures exhibit more uniform and stronger interfacial adhesion. This enhanced coupling also enables the observation of a theoretically predicted tension-induced band structure transition in MoS 2 . Moreover, no obvious degradation in the devices’ structural and electrical properties is identified after numerous mechanical cycle tests. This high-quality lamination enhances the reliability of vdWS-based flexible microelectronics, accelerating their practical applications in biomedical research and consumer electronics.

36 MATERIALS SCIENCE↗
NASA NTRS1979

Contamination control in hybrid microcircuit modules

The influence of chemical and particulate contamination upon the reliability and service life of hybrid microelectronic systems is documented. Several coating systems used include the parylene and Dow Corning silicone (DC90-711). These passivating coatings have potential for decreasing the degradation caused by particulate contaminants in hybrid systems as well as the possible deleterious effect of trapping chemical contaminants which have long term degrading influences upon the performance of the system. The reliability of a representative hybrid microcircuit is enhanced by the coating process.

Kinser, D. L.↗
DOE OSTI2015

On the interplay between relaxation, defect formation, and atomic Sn distribution in Ge{sub (1−x)}Sn{sub (x)} unraveled with atom probe tomography

Ge{sub (1−x)}Sn{sub (x)} has received a lot of interest for opto-electronic applications and for strain engineering in advanced complementary-metal-oxide-semiconductor technology, because it enables engineering of the band gap and inducing strain in the alloy. To target a reliable technology for mass application in microelectronic devices, the physical problem to be addressed is to unravel the complex relationship between strain relaxation (as induced by the growth of large layer thicknesses or a thermal anneal) and defect formation, and/or stable Sn-cluster formation. In this paper, we study the onset of Sn-cluster formation and its link to strain relaxation using Atom Probe Tomography (APT). To this end, we also propose a modification of the core-linkage [Stephenson et al., Microsc. Microanal. 13, 448 (2007)] cluster analysis method, to overcome the challenges of limited detection efficiency and lateral resolution of APT, and the quantitative assessment for very small clusters (<40 atoms) embedded in a random distribution of Sn-atoms. We concluded that the main relaxation mechanism for these layers is defect generation (misfit dislocations, threading dislocations, etc.), irrespective of the cause (thickness of layer or thermal anneal) of relaxation and is independent of the cluster formation. The low thermodynamic solubility limit of Sn in Ge seems to be the driving force for Sn-cluster formation. Finally, we also discuss the spatial distribution of Sn in clusters and relate them to the theoretically predicted stable Sn clusters [Ventura et al., Phys. Rev. B 79, 155202 (2009)].

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
NASA NTRS2006

Product Reliability Trends, Derating Considerations and Failure Mechanisms with Scaled CMOS

As microelectronics is scaled into the deep sub-micron regime, space and aerospace users of advanced technology CMOS are reassessing how scaling effects impact long-term product reliability. The effects of electromigration (EM), time-dependent-dielectric-breakdown (TDDB) and hot carrier degradation (HCI and NBTI) wearout mechanisms on scaled technologies and product reliability are investigated, accelerated stress testing across several technology nodes is performed, and FA is conducted to confirm the failure mechanism(s).

CMOS integrated circuits↗
NASA NTRS1975

Investigation of discrete component chip mounting technology for hybrid microelectronic circuits

The use of polymer adhesives for high reliability microcircuit applications is a radical deviation from past practices in electronic packaging. Bonding studies were performed using two gold-filled conductive adhesives, 10/90 tin/lead solder and Indalloy no. 7 solder. Various types of discrete components were mounted on ceramic substrates using both thick-film and thin-film metallization. Electrical and mechanical testing were performed on the samples before and after environmental exposure to MIL-STD-883 screening tests.

Caruso, S. V.↗
NASA NTRS2012

Reliability Considerations of ULP Scaled CMOS in Spacecraft Systems

NASA, the aerospace community, and other high reliability (hi-rel) users of advanced microelectronic products face many challenges as technology continues to scale into the deep sub-micron region. Decreasing the feature size of CMOS devices not only allows more components to be placed on a single chip, but it increases performance by allowing faster switching (or clock) speeds with reduced power compared to larger scaled devices. Higher performance, and lower operating and stand-by power characteristics of Ultra-Low Power (ULP) microelectronics are not only desirable, but also necessary to meet low power consumption design goals of critical spacecraft systems. The integration of these components in such systems, however, must be balanced with the overall risk tolerance of the project.

reliability↗
NASA NTRS1989

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Buehler, M. G.↗
DOE OSTI2015

Density functional theory study of the influence of segregation of S or Fe impurities on electromigration in nano-grained copper interconnects

The reliability of the circuits in the modern microelectronic devices remains, during last decades, one of the key topics in research and gains an attention for improving the promising candidates for conductors. Improvement of materials for such applications can be obtained by both electronic and compositional optimization. Ab initio calculations using full potential linearized augmented plane wave method in density functional theory are applied to explain the reduction in electromigration effect in the vicinity of grain boundaries (GB) in nano-structured Cu due to the segregation of some additives to the GB. Several possible mechanisms are considered. It is demonstrated that S atoms segregated to GB of nano-structured Cu lead to the growth of effective mass of the electrons. This decreases the mobility of electrons in external electric field, and, correspondingly, the momentum that they may transfer to atoms in collisions. Fe atoms segregated to GB of Cu create new empty states at the top of the valance band. These non-occupied states may stimulate the current of holes when external electric field is applied to the system, creating the “hole wind” in the direction opposite to the current of electrons. Such “hole wind” will compensate the forces generated by the electron current and therefore will reduce the total momentum transfer between charge carriers and atoms. The calculated electron density maps show that S and Fe segregating to Cu GB increases the strength of covalent bonds reducing the diffusion of Cu atoms in the vicinity of GB.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRSDate not supplied

Comparison of a Probabilistic TID Hardness Assurance Method to Military Standards

The rapid evolution of electronics has heralded countless benefits to humanity, enabling increases in computing power while decreasing costs. However, the constantly changing semiconductor device landscape proves to be an immense challenge for the reliability community, especially for those concerned with radiation effects on microelectronics. Changes in device manufacturing, from device structure to processing steps, may and often do change the way the device responds to radiation. While radiation hardened parts are not as much of a reliability concern, they also lag behind commercial off-the-shelf, or COTS, parts in terms of computing capabilities, some by over a decade. Many missions may have no choice but to utilize COTS. As such, these missions need to ensure their parts are reliable in the face of total ionizing dose (TID). However, part and testing facility costs limit the amount of testing possible.

Chloe Champagne↗
DOE OSTI2025

In-situ synchrotron X-ray study on microstructure and stress evolutions of electroplated copper upon self-annealing

Background: The self-annealing behavior of electroplated copper (Cu) at room temperature is gaining attention in the microelectronics industry due to its significant impact on reliability issues such as substrate warpage and electrical resistivity. Methods: In this study, in-situ analysis of the microstructure transition and stress relaxation of the electroplated copper upon self-annealing was conducted via synchrotron white X-ray nanodiffraction (beamline 21A, Taiwan Photon Source) and grazing-incidence X-ray diffraction (beamline 17B1, Taiwan Light Source). Significant Findings: Remarkable relaxations of deviatoric stress and absolute strain component along the [002] direction were closely related to the Cu grain growth and crystallographic reorientation at the early stage of selfannealing, and a complete stress/strain relaxation can be achieved with the cessation of microstructure transition. In conclusion, the in-situ synchrotron X-ray studies provided an insight into Cu self-annealing mechanism, offering valuable information for improving Cu interconnect reliability.

Cu Self-annealing↗
NASA NTRS2002

Recent photonics activites under the NASA electronic parts and packaging (NEPP) program

With the rapidly increasing insertion of photonic devices, circuits and subsystems into NASA spacecraft, a variety of issues associated with reliability and radiation tolerance have arisen. In this paper, we discuss these issues from the perspective of the work currently ongoing in the NASA Electronic Parts and Packaging (NEPP) Program. This Program is focused on evaluating the reliability and radiation response of advanced and emerging microelectronics and photonics technologies of interest to NASA spacecraft system designers.

NEEP↗