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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

UNITY: Unified Memory and Storage Space

UNITY is a 36-month project focused on providing design and evaluate a new distributed storage paradigm that unifies the traditionally distinct application views of memory- and file-based data storage into a single scalable and resilient environment. The project is a collaboration among Oak Ridge National Laboratory (ORNL, Lead institution), Los Alamos National Labs (LANL), and Georgia Tech (GT). The main contributions of the GT team have been around development of low level systems software for best leveraging the capabilities of new types of persistent memory technologies, and for development of methods for intelligent data management across memory/storage substrates with heterogeneous components. GT contributed the Phoenix library for optimized checkpoint/restart for HPC I/O for systems with non-volatile memory (NVM), the NVStream library for NVM-specialized streaming I/O for HPC workflows, the CoMerge, Mnemo and Kleio solutions for intelligent data management on NVM-based systems. These contributions result in significant improvements in both application performance and system efficiency.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2018

A Novel 3D DRAM Memory Cube Architecture for Space Applications

The first mainstream products in 3D IC design are memory devices where multiple memory tiers are horizontally integrated to offer manifold improvements compared with their 2D counterparts. Unfortunately, none of these existing 3D memory cubes are ready for harsh space environments. This paper presents a new memory cube architecture for space, based on vertical integration of Commercial Off-The-Shelf (COTS), 3D stacked, DRAM memory devices with a custom Radiation-Hardened-By-Design (RHBD) controller offering high memory capacity, robust reliability and low latency.Validation and evaluation of the ASIC controller will be conducted prior to tape-out on a custom FPGA-based emulator platform integrating the 3D-stack.

Yang-Scharlotta, Jean↗
NASA NTRS1975

Camera memory study for large space telescope

Specifications were developed for a memory system to be used as the storage media for camera detectors on the large space telescope (LST) satellite. Detectors with limited internal storage time such as intensities charge coupled devices and silicon intensified targets are implied. The general characteristics are reported of different approaches to the memory system with comparisons made within the guidelines set forth for the LST application. Priority ordering of comparisons is on the basis of cost, reliability, power, and physical characteristics. Specific rationales are provided for the rejection of unsuitable memory technologies. A recommended technology was selected and used to establish specifications for a breadboard memory. Procurement scheduling is provided for delivery of system breadboards in 1976, prototypes in 1978, and space qualified units in 1980.

Hoffman, C. P.↗
NASA NTRS1992

The 30th AAS Goddard Memorial Symposium. World space programs and fiscal reality: Synopsis

A full proceedings of the symposium will be issued later in the year. This synopsis consists of summations of three sessions by appointed rapporteurs. International figures in space and in politics spoke at the sessions. Themes of international cooperation and fiscal reality pervaded the conference. International speakers from Canada, the European Space Agency, Russia, Japan and China and other countries addressed the topic of the symposium. American representation included Senator Barbara Mikulski, former NASA administrator James Beggs and other speakers.

Source record↗
NASA NTRS1989

A class of designs for a sparse distributed memory

A general class of designs for a space distributed memory (SDM) is described. The author shows that Kanerva's original design and the selected-coordinate design are related, and that there is a series of possible intermediate designs between those two designs. In each such design, the set of addresses that activate a memory location is a sphere in the address space. We can also have hybrid designs, in which the memory locations may be a mixture of those found in the other designs. In some applications, the bits of the read and write addresses that will actually be used might be mostly zeros; that is, the addresses might lie on or near z hyperplane in the address space. The author describes a hyperplane design which is adapted to this situation and compares it to an adaptation of Kanerva's design. To study the performance of these designs, he computes the expected number of memory locations activated by both of two addresses.

Jaeckel, Louis A.↗
NASA NTRS2001

Space Radiation Effects in Advanced Flash Memories

Memory storage requirements in space systems have steadily increased, much like storage requirements in terrestrial systems. Large arrays of dynamic memories (DRAMs) have been used in solid-state recorders, relying on a combination of shielding and error-detection-and correction (EDAC) to overcome the extreme sensitivity of DRAMs to space radiation. For example, a 2-Gbit memory (with 4-Mb DRAMs) used on the Clementine mission functioned perfectly during its moon mapping mission, in spite of an average of 71 memory bit flips per day from heavy ions. Although EDAC worked well with older types of memory circuits, newer DRAMs use extremely complex internal architectures which has made it increasingly difficult to implement EDAC. Some newer DRAMs have also exhibited catastrophic latchup. Flash memories are an intriguing alternative to DRAMs because of their nonvolatile storage and extremely high storage density, particularly for applications where writing is done relatively infrequently. This paper discusses radiation effects in advanced flash memories, including general observations on scaling and architecture as well as the specific experience obtained at the Jet Propulsion Laboratory in evaluating high-density flash memories for use on the NASA mission to Europa, one of Jupiter's moons. This particular mission must pass through the Jovian radiation belts, which imposes a very demanding radiation requirement.

Johnston, A. H.↗
NASA NTRS1991

Data systems and computer science space data systems: Onboard memory and storage

The topics are presented in viewgraph form and include the following: technical objectives; technology challenges; state-of-the-art assessment; mass storage comparison; SODR drive and system concepts; program description; vertical Bloch line (VBL) device concept; relationship to external programs; and backup charts for memory and storage.

Shull, Tom↗
NASA NTRS2012

Non Volatile Flash Memory Radiation Tests

Commercial flash memory industry has experienced a fast growth in the recent years, because of their wide spread usage in cell phones, mp3 players and digital cameras. On the other hand, there has been increased interest in the use of high density commercial nonvolatile flash memories in space because of ever increasing data requirements and strict power requirements. Because of flash memories complex structure; they cannot be treated as just simple memories in regards to testing and analysis. It becomes quite challenging to determine how they will respond in radiation environments.

single event upset results↗
NASA NTRS1989

An alternative design for a sparse distributed memory

A new design for a Sparse Distributed Memory, called the selected-coordinate design, is described. As in the original design, there are a large number of memory locations, each of which may be activated by many different addresses (binary vectors) in a very large address space. Each memory location is defined by specifying ten selected coordinates (bit positions in the address vectors) and a set of corresponding assigned values, consisting of one bit for each selected coordinate. A memory location is activated by an address if, for all ten of the locations's selected coordinates, the corresponding bits in the address vector match the respective assigned value bits, regardless of the other bits in the address vector. Some comparative memory capacity and signal-to-noise ratio estimates for the both the new and original designs are given. A few possible hardware embodiments of the new design are described.

Jaeckel, Louis A.↗
NASA NTRS1996

Analysis of space radiation data of semiconductor memories

This article presents an analysis of radiation effects for several select device types and technologies aboard the Combined Release and Radiation Effects Satellite (CRRES) satellite. These space-flight measurements covered a period of about 14 months of mission lifetime. Single Event Upset (SEU) data of the investigated devices from the Microelectronics Package (MEP) were processed and analyzed. Valid upset measurements were determined by correcting for invalid readings, hard failures, missing data tapes (thus voids in data), and periods over which devices were disabled from interrogation. The basic resolution time of the measurement system was confirmed to be 2 s. Lessons learned, important findings, and recommendations are presented.

Flight Experiment↗
NASA NTRS1972

Conceptual design of a 10 to the 8th power bit magnetic bubble domain mass storage unit and fabrication, test and delivery of a feasibility model

The conceptual design of a highly reliable 10 to the 8th power-bit bubble domain memory for the space program is described. The memory has random access to blocks of closed-loop shift registers, and utilizes self-contained bubble domain chips with on-chip decoding. Trade-off studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit-per-chip basis. The final design has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a 16-adjacent code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (equal to or less than, 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 msec to an 800-word block and an additional 4 msec (average) to a word. The fabrication and operation are also described for a 64-bit bubble domain memory chip designed to test the concept of on-chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble.

Source record↗
NASA NTRS1975

System applications of the fault tolerant memory

Conventional memory technologies currently employed in aerospace applications contribute at least fifty percent to system unreliability (where the system includes CPU, I/O and memory). A fault tolerant memory performs both error correction and memory replacement at the bit plane level. To determine the effects of system design of using a fault tolerant memory in space applications, analysis was performed to determine tradeable hardware configurations that meet the reliability goals of each program. The candidate configurations, which included redundant elements of the computer system with both conventional and fault tolerant memories, were then traded in terms of selection criteria of cost, weight, volume, and power. These trade studies demonstrated that a fault tolerant memory provided significant advantages in terms of cost, weight, and volume. The memory selected for this analysis was a recently developed five fault tolerant memory.

Murphy, L. J.↗
NASA NTRS2010

NEPP non-volatile memory : FY09 summary report

This report documents the activities and results of the fiscal year 2009 (FY09) funding for the NASA Electronic Parts and Packaging (NEPP) program for non-volatile memory (NVM) devices. The FY09 task was divided into two main efforts: 1. Development of in-house measurement capability for flash devices 2. Reliability characterization of multi-level vs. single-level flash devices The FY09 NEPP Non Volatile Memory study was organized into these two sections in recognition of the continued and increasing importance of NVM to NASA. All NASA missions use NVM for boot code storage and some limited data archiving. Space-grade NVM has lagged commercial NVM development by many orders of magnitude, however. This gap in density only continues to increase as space-grade memories remain constant in the 1–16 Mbit levels, while commercial flash-based devices shrink in size and double in capacity every 18 months. Commercial flash devices are now at the 32 Gbit level, 10,000 times denser than current NASA NVM. This FY marks the beginning of a significant technological transition in NVM for NASA. The aggressive scaling of commercial NVMs has, as a by-product, made some of the flash devices radiation-tolerant enough to be at least considered for low-level radiation environment missions [Irom 2008]. This NEPP task is focused on understanding the reliability and potential future applications of such highly scaled flash memories.

Heidecker, Jason↗
NASA NTRS2002

Space Transportation and the Computer Industry: Learning from the Past

Since the space shuttle began flying in 1981, NASA has made a number of attempts to advance the state of the art in space transportation. In spite of billions of dollars invested, and several concerted attempts, no replacement for the shuttle is expected before 2010. Furthermore, the cost of access to space has dropped very slowly over the last two decades. On the other hand, the same two decades have seen dramatic progress in the computer industry. Computational speeds have increased by about a factor of 1000 and available memory, disk space, and network bandwidth has seen similar increases. At the same time, the cost of computing has dropped by about a factor of 10000. Is the space transportation problem simply harder? Or is there something to be learned from the computer industry? In looking for the answers, this paper reviews the early history of NASA's experience with supercomputers and NASA's visionary course change in supercomputer procurement strategy.

Merriam, M. L.↗