MOS field-effect transistor drivers for laminated-ferrite memories.
MOSFET drivers for low current memory fabricated in 64 unit monolithic strips, discussing driver performance data
Boesenberg, W. A.↗
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Results for “low memory”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Tuning resistance states by thickness control in an electroforming-free nanometallic complementary resistance random access memory
Tuning low resistance state is crucial for resistance random access memory (RRAM) that aims to achieve optimal read margin and design flexibility. By back-to-back stacking two nanometallic bipolar RRAMs with different thickness into a complementary structure, we have found that its low resistance can be reliably tuned over several orders of magnitude. Such high tunability originates from the exponential thickness dependence of the high resistance state of nanometallic RRAM, in which electron wave localization in a random network gives rise to the unique scaling behavior. The complementary nanometallic RRAM provides electroforming-free, multi-resistance-state, sub-100 ns switching capability with advantageous characteristics for memory arrays.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
Field-current phase diagrams of in-plane spin transfer torque memory cells with low effective magnetization storage layers
Field-current phase diagrams were measured on in-plane anisotropy Co{sub 60}Fe{sub 20}B{sub 20} magnetic tunnel junctions to obtain the spin transfer torque (STT) field-current switching window. These measurements were used to characterise junctions with varying free layer thicknesses from 2.5 down to 1.1 nm having a reduced effective demagnetizing field due to the perpendicular magnetic anisotropy at CoFeB/MgO interface. Diagrams were obtained with 100 ns current pulses, of either same or alternating polarity. When consecutive pulses have the same polarity, it is possible to realize the STT switching even for conditions having a low switching probability. This was evidenced in diagrams with consecutive pulses of alternating polarity, with 100% switching obtained at 4.7 MA/cm{sup 2}, compared to the lower 3.4 MA/cm{sup 2} value for same polarity pulses. Although the low level of the current density window is higher in alternating polarity diagrams, the field window in both diagrams is the same and therefore independent of the pulse polarity sequence.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
High-performance low-power CMOS memories using silicon-on-sapphire technology.
MOS/silicon-on-sapphire (SOS) technology is shown to permit the realization of large-scale integrated arrays that combine the best features of monolithic bipolar and MOS technologies. The perfect isolation and reduced capacitance of SOS technology make possible static MOS circuits with nearly an order-of-magnitude improvement in speed and dynamic power dissipation over their monolithic counterparts. CMOS/SOS memory arrays have been fabricated with speeds comparable to TTL bipolar memory arrays even when operated at TTL compatible levels. Quiescent power dissipation of two described arrays is typically less than 1 microwatt/bit. The SOS/MOS technology is compatible with both aluminum and self-aligned silicon-gate processing.
Boleky, E. J.↗
Design and testing of a low cost Shape Memory Alloy (SMA) heat switch for CubeSats
UNKNOWN
Redmond, Matthew↗
Analog computing using SONOS charge trap memory for low-power space-borne artificial intelligence
Full paper submission for accepted GOMAC'25 oral presentation.
Xiao, Tianyao Patrick [Sandia National Laboratorie↗
Low-Voltage, CMOS-Free Synaptic Memory Based on Li X TiO 2 Redox Transistors
Neuromorphic computers based on analogue neural networks aim to substantially lower computing power by reducing the need to shuttle data between memory and logic units. Artificial synapses containing nonvolatile analogue conductance states enable direct computation using memory elements; however, most nonvolatile analogue memories require high write voltages and large current densities and are accompanied by nonlinear and unpredictable weight updates. Here, we develop an inorganic redox transistor based on electrochemical lithium-ion insertion into Li X TiO 2 that displays linear weight updates at both low current densities and low write voltages. The write voltage, as low as 200 mV at room temperature, is achieved by minimizing the open-circuit voltage and using a low-voltage diffusive memristor selector. We further show that the Li X TiO 2 redox transistor can achieve an extremely sharp transistor subthreshold slope of just 40 mV/decade when operating in an electrochemically driven phase transformation regime.
42 ENGINEERING↗
Microscopic origin of read current noise in TaO{sub x}-based resistive switching memory by ultra-low temperature measurement
TaO{sub x}-based resistive random access memory (RRAM) attracts considerable attention for the development of next generation nonvolatile memories. However, read current noise in RRAM is one of the critical concerns for storage application, and its microscopic origin is still under debate. In this work, the read current noise in TaO{sub x}-based RRAM was studied thoroughly. Based on a noise power spectral density analysis at room temperature and at ultra-low temperature of 25 K, discrete random telegraph noise (RTN) and continuous average current fluctuation (ACF) are identified and decoupled from the total read current noise in TaO{sub x} RRAM devices. A statistical comparison of noise amplitude further reveals that ACF depends strongly on the temperature, whereas RTN is independent of the temperature. Measurement results combined with conduction mechanism analysis show that RTN in TaO{sub x} RRAM devices arises from electron trapping/detrapping process in the hopping conduction, and ACF is originated from the thermal activation of conduction centers that form the percolation network. At last, a unified model in the framework of hopping conduction is proposed to explain the underlying mechanism of both RTN and ACF noise, which can provide meaningful guidelines for designing noise-immune RRAM devices.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
Ultra low density biodegradable shape memory polymer foams with tunable physical properties
Compositions and/or structures of degradable shape memory polymers (SMPs) ranging in form from neat/unfoamed to ultra low density materials of down to 0.005 g/cc density. These materials show controllable degradation rate, actuation temperature and breadth of transitions along with high modulus and excellent shape memory behavior. A method of m ly low density foams (up to 0.005 g/cc) via use of combined chemical and physical aking extreme blowing agents, where the physical blowing agents may be a single compound or mixtures of two or more compounds, and other related methods, including of using multiple co-blowing agents of successively higher boiling points in order to achieve a large range of densities for a fixed net chemical composition. Methods of optimization of the physical properties of the foams such as porosity, cell size and distribution, cell openness etc. of these materials, to further expand their uses and improve their performance.
36 MATERIALS SCIENCE↗
OAST Space Theme Workshop. Volume 3: Working group summary. 2: Data handling, communications (E-2). A. Statement. B. Technology needs (form 1). C. Priority assessment (form 2)
Technologies required to support the stated OAST thrust to increase information return by X1000, while reducing costs by a factor of 10 are identified. The most significant driver is the need for an overall end-to-end data system management technology. Maximum use of LSI component technology and trade-offs between hardware and software are manifest in most all considerations of technology needs. By far, the greatest need for data handling technology was identified for the space Exploration and Global Services themes. Major advances are needed in NASA's ability to provide cost effective mass reduction of space data, and automated assessment of earth looking imagery, with a concomitant reduction in cost per useful bit. A combined approach embodying end-to-end system analysis, with onboard data set selection, onboard data processing, highly parallel image processing (both ground and space), low cost, high capacity memories, and low cost user data distribution systems would be necessary.
Source record↗
Low-power resistive random access memory by confining the formation of conducting filaments
Owing to their small physical size and low power consumption, resistive random access memory (RRAM) devices are potential for future memory and logic applications in microelectronics. In this study, a new resistive switching material structure, TiO{sub x}/silver nanoparticles/TiO{sub x}/AlTiO{sub x}, fabricated between the fluorine-doped tin oxide bottom electrode and the indium tin oxide top electrode is demonstrated. The device exhibits excellent memory performances, such as low operation voltage (<±1 V), low operation power, small variation in resistance, reliable data retention, and a large memory window. The current-voltage measurement shows that the conducting mechanism in the device at the high resistance state is via electron hopping between oxygen vacancies in the resistive switching material. When the device is switched to the low resistance state, conducting filaments are formed in the resistive switching material as a result of accumulation of oxygen vacancies. The bottom AlTiO{sub x} layer in the device structure limits the formation of conducting filaments; therefore, the current and power consumption of device operation are significantly reduced.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
Apparatus and Method for Low-Temperature Training of Shape Memory Alloys
An apparatus and method for the low-temperature thermo-mechanical training of shape memory alloys (SMA) has been developed. The experimental SMA materials are being evaluated as prototypes for applicability in novel thermal management systems for future cryogenic applications. Alloys providing two-way actuation at cryogenic temperatures are the chief target. The mechanical training regimen was focused on the controlled movement of rectangular strips, with S-bend configurations, at temperatures as low as 30 K. The custom holding fixture included temperature sensors and a low heat-leak linear actuator with a magnetic coupling. The fixture was mounted to a Gifford-McMahon cryocooler providing up to 25 W of cooling power at 20 K and housed within a custom vacuum chamber. Operations included both training cycles and verification of shape memory movement. The system design and operation are discussed. Results of the training for select prototype alloys are presented.
Training↗
Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)
Most parts of present computer systems are made of volatile devices, and the power to supply them to avoid information loss causes huge energy losses. We can eliminate this meaningless energy loss by utilizing the non-volatile function of advanced spin-transfer torque magnetoresistive random-access memory (STT-MRAM) technology and create a new type of computer, i.e., normally off computers. Critical tasks to achieve normally off computers are implementations of STT-MRAM technologies in the main memory and low-level cache memories. STT-MRAM technology for applications to the main memory has been successfully developed by using perpendicular STT-MRAMs, and faster STT-MRAM technologies for applications to the cache memory are now being developed. The present status of STT-MRAMs and challenges that remain for normally off computers are discussed.
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
Non-Volatile, Low Power, and High Density SiC Memory For Future Venus Missions
Long lived memory would transform Venus landers & missions. Venus durable memory demonstrated in earlier HOTTech with impractically high power and low bit capacity. This project seeks to develop and demonstrate the world’s first Venus-durable low power memory device (Non-Volatile Random Access Memory (NVRAM) to enhance extended Venus surface missions.
silicon carbide↗
Resistance drift in Ge 2 Sb 2 Te 5 phase change memory line cells at low temperatures and its response to photoexcitation
Resistance drift in amorphous Ge 2 Sb 2 Te 5 is experimentally characterized in melt-quenched line cells in the range of 300 K to 125 K and is observed to follow the previously reported power-law behavior with drift coefficients in the range of 0.07 to 0.11 in the dark, linearly decreasing with 1/kT. While these drift coefficients measured in the dark are similar to commonly observed drift coefficients (~0.1) at and above room temperature, measurements under light show a significantly lower drift coefficient (0.05 under illumination vs 0.09 in the dark at 150 K). Periodic on/off switching of light shows a sudden decrease/increase in resistance, attributed to photo-excited carriers, followed by a very slow response (~30 min at 150 K) attributed to contribution of electron traps and slow trap-to-trap charge exchanges. A device-level electronic model is used to relate these experimental findings to gradual charging of electron traps in amorphous Ge 2 Sb 2 Te 5 , which gives rise to growth of a potential barrier for holes in time and, hence, resistance drift.
42 ENGINEERING↗
Energy and Area Efficiency in Neuromorphic Computing for Resource Constrained Devices
Resource constrained devices are the building blocks of the internet of things (IoT) era. Since the idea behind IoT is to develop an interconnected environment where the devices are tiny enough to operate with limited resources, several control systems have been built to maintain low energy and area consumption while operating as IoT edge devices. Several researchers have begun work on implementing control systems built from resource constrained devices using machine learning. However, there are many ways such devices can achieve lower power consumption and area utilization while maximizing application efficiency. Spiky neuromorphic computing (SNC) is an emerging paradigm that can be leveraged in resource constrained devices for several emerging applications. While delivering the benefits of machine learning, SNC also helps minimize power consumption. For example, low energy memory devices (memristors) are often used to achieve low power operation and also help in reducing system area. In total, we anticipate SNC will provide computational efficiency approaching that of deep learning while using low power, resource constrained devices.
Chakma, Gangotree↗
A radiation - tolerant, low - power non - volatile memory based on silicon nanocrystal quantum dots.
Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in Si02 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled.
Green, M. L.↗