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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS2014

Statistical Symbolic Execution with Informed Sampling

Symbolic execution techniques have been proposed recently for the probabilistic analysis of programs. These techniques seek to quantify the likelihood of reaching program events of interest, e.g., assert violations. They have many promising applications but have scalability issues due to high computational demand. To address this challenge, we propose a statistical symbolic execution technique that performs Monte Carlo sampling of the symbolic program paths and uses the obtained information for Bayesian estimation and hypothesis testing with respect to the probability of reaching the target events. To speed up the convergence of the statistical analysis, we propose Informed Sampling, an iterative symbolic execution that first explores the paths that have high statistical significance, prunes them from the state space and guides the execution towards less likely paths. The technique combines Bayesian estimation with a partial exact analysis for the pruned paths leading to provably improved convergence of the statistical analysis. We have implemented statistical symbolic execution with in- formed sampling in the Symbolic PathFinder tool. We show experimentally that the informed sampling obtains more precise results and converges faster than a purely statistical analysis and may also be more efficient than an exact symbolic analysis. When the latter does not terminate symbolic execution with informed sampling can give meaningful results under the same time and memory limits.

Reliability↗
NASA NTRS2018

An Investigation of Parallel Programming Techniques Applied to Monte Carlo Simulations for Post-Flight Reconstruction of Spacecraft Trajectory

Parallelizing software to execute on multi-core central processing units (CPUs) and graphics processing units (GPUs) can be challenging. For some fields outside of Computer Science, this transition comes with new issues. For example, memory limitations can require modifications to code not initially developed to run on GPUs. This work applies the Open Multi-Processing (OpenMP) and Open Accelerators (OpenACC) directive-based parallelization strategies on a Monte Carlo simulation approach for trajectory reconstruction enabling it to run on multi-core CPUs and GPUs. Large matrix operations are the most common use of GPUs, which are not present in this algorithm; however, the natural parallelism of independent trajectories in Monte Carlo simulations is exploited. Benchmarking data are presented comparing execution times of the software for single-thread CPUs, multi-thread CPUs with OpenMP, and multi-thread GPUs using OpenACC. These data were collected using nodes with Intel® Xeon® E5-2670 (Sandy Bridge) CPUs enhanced with NVIDIA® Tesla® K40 GPUs on the Pleiades Supercomputer cluster at the National Aeronautics and Space Administration (NASA) Ames Research Center (ARC) and a local Intel® Xeon Phi™ node at NASA Langley Research Center (LaRC).

Williams, R. Anthony↗
NASA NTRSDate not supplied

A Partitioned - Task Parallel Implementation of the NASA Multiscale Analysis Tool for High Performance Computing

The NASA Multiscale Analysis Tool (NASMAT) is a platform for multiscale modeling of composites which can perform analysis of materials with any arbitrary number of length scales. The platform supports modularity, scalability, and interoperability using recursive procedures and data structures. A Macro solver driven parallelization scheme often limits the capability of NASMAT to scale as it has access to limited memory and number of cores (often one core/thread) and often forces to implement macro solver specific changes to the platform. In this work, a partitioned task-parallel approach is adopted, where the parallelization strategy adopted for NASMAT is independent of the macro solver and the computational resources are managed independently. The programming architecture takes into account the hierarchy of multiple scales (task-dependence) and the heterogeneous nature (dynamic load balancing) of computation through implementation of a hierarchy-informed task parallel model. The partitioned nature of the framework further extends the “plug and play” capability of NASMAT. preCICE, an open-source library for coupling multiphysics solver in a partitioned manner, is adopted to integrate NASMAT with an external macro solver by implementing a NASMAT adapter for preCICE. Speedup and scalability of the framework is studied for micromechanical models of varying size.

task-parallel↗
NASA NTRS1969

Circuitry selectively limits data storage in general purpose computer

Circuitry limits storage in the memory of a stored program general purpose digital computer by permitting storage or writing to certain, specified areas of memory. The limit register used in the computer is easily set under program control, and the memory block size and position is readily changed to suit each specific program.

Slopper, D. K.↗
NASA NTRS2020

The NANOGrav 11 yr data set: Limits on Gravitational Wave Memory

The mergers of supermassive black hole binaries (SMBHBs) promise to be incredible sources of gravitational waves (GWs).While the oscillatory part of the merger gravitational waveform will be outside the frequency sensitivity range of pulsar timing arrays, the nonoscillatory GW memory effect is detectable. Further, any burst of GWs will produce GW memory, making memory a useful probe of unmodeled exotic sources and new physics. We searched the North American Nanohertz Observatory for Gravitational Waves (NANOGrav) 11 yr data set for GW memory. This data set is sensitive to very low-frequency GWs of ∼3 to 400 nHz (periods of ∼11 yr–1 month). Finding no evidence for GWs, we placed limits on the strain amplitude of GW memory events during the observation period. We then used the strain upper limits to place limits on the rate of GW memory causing events. At a strain of 2.5 × 10−14, corresponding to the median upper limit as a function of source sky position, we set a limit on the rate of GW memory events at <0.4 yr−1. That strain corresponds to an SMBHB merger with reduced mass of ηM ~2 × 1010Mmoonand inclination of ι = π/3 at a distance of 1 Gpc. As a test of our analysis, we analyzed the NANOGrav 9 yr data set as well. This analysis found an anomolous signal, which does not appear in the 11 yr data set. This signal is not a GW, and its origin remains unknown.

K Aggarwal↗
DOE OSTI2021

Phase‐Change‐Memory Process at the Limit: A Proposal for Utilizing Monolayer Sb 2 Te 3

Abstract One central task of developing nonvolatile phase change memory (PCM) is to improve its scalability for high‐density data integration. In this work, by first‐principles molecular dynamics, to date the thinnest PCM material possible (0.8 nm), namely, a monolayer Sb 2 Te 3 , is proposed. Importantly, its SET (crystallization) process is a fast one‐step transition from amorphous to hexagonal phase without the usual intermediate cubic phase. An increased spatial localization of electrons due to geometrical confinement is found to be beneficial for keeping the data nonvolatile in the amorphous phase at the 2D limit. The substrate and superstrate can be utilized to control the phase change behavior: e.g., with passivated SiO 2 (001) surfaces or hexagonal Boron Nitride, the monolayer Sb 2 Te 3 can reach SET recrystallization in 0.54 ns or even as fast as 0.12 ns, but with unpassivated SiO 2 (001), this would not be possible. Besides, working with small volume PCM materials is also a natural way to lower power consumption. Therefore, the proposed PCM working process at the 2D limit will be an important potential strategy of scaling the current PCM materials for ultrahigh‐density data storage.

2D limit↗
DOE OSTI2022

MemHC: An Optimized GPU Memory Management Framework for Accelerating Many-body Correlation

The many-body correlation function is a fundamental computation kernel in modern physics computing applications, e.g., Hadron Contractions in Lattice quantum chromodynamics (QCD). This kernel is both computation and memory intensive, involving a series of tensor contractions, and thus usually runs on accelerators like GPUs. Existing optimizations on many-body correlation mainly focus on individual tensor contractions (e.g., cuBLAS libraries and others). In contrast, this work discovers a new optimization dimension for many-body correlation by exploring the optimization opportunities among tensor contractions. More specifically, it targets general GPU architectures (both NVIDIA and AMD) and optimizes many-body correlation’s memory management by exploiting a set of memory allocation and communication redundancy elimination opportunities: first, GPU memory allocation redundancy: the intermediate output frequently occurs as input in the subsequent calculations; second, CPU-GPU communication redundancy: although all tensors are allocated on both CPU and GPU, many of them are used (and reused) on the GPU side only, and thus, many CPU/GPU communications (like that in existing Unified Memory designs) are unnecessary; third, GPU oversubscription: limited GPU memory size causes oversubscription issues, and existing memory management usually results in near-reuse data eviction, thus incurring extra CPU/GPU memory communications.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2007

Distributed Saturation

The Saturation algorithm for symbolic state-space generation, has been a recent break-through in the exhaustive veri cation of complex systems, in particular globally-asyn- chronous/locally-synchronous systems. The algorithm uses a very compact Multiway Decision Diagram (MDD) encoding for states and the fastest symbolic exploration algo- rithm to date. The distributed version of Saturation uses the overall memory available on a network of workstations (NOW) to efficiently spread the memory load during the highly irregular exploration. A crucial factor in limiting the memory consumption during the symbolic state-space generation is the ability to perform garbage collection to free up the memory occupied by dead nodes. However, garbage collection over a NOW requires a nontrivial communication overhead. In addition, operation cache policies become critical while analyzing large-scale systems using the symbolic approach. In this technical report, we develop a garbage collection scheme and several operation cache policies to help on solving extremely complex systems. Experiments show that our schemes improve the performance of the original distributed implementation, SmArTNow, in terms of time and memory efficiency.

Chung, Ming-Ying↗
DOE OSTI2023

COLLABORATIVE DEVELOPMENT PROJECTS - PHOTONIC MEMORY CONTROLLER MODULE (P-MCM)

As computational density for high-performance computing and big-data services continues to scale, performance scalability of next generation computing systems is becoming increasingly constrained by limitations in memory access, power dissipation and chip packaging. The processor-memory communication bottleneck, a major challenge in current multicore processors due to limited pin-out and power budget, presents a detrimental scaling barrier to data-intensive computing. A consortium team of small businesses and leading researchers that includes experts from photonics processor-memory architecture, III/V photonic laser design/fabrication, silicon photonics design/fabrication, photonics packaging and assembly, and FPGA-based high-performance memory controller IP development – to collaboratively develop a commercialization path for a Photonic Memory Controller Module (P-MCM).

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2001

Future Development of Dense Ferroelectric Memories for Space Applications

The availability of high density, radiation tolerant, nonvolatile memories is critical for space applications. Ferroelectric memories, when fabricated with radiation hardened complementary metal oxide semiconductors (CMOS), can be manufactured and packaged to provide high density replacements for Flash memory, which is not radiation tolerant. Previous work showed ferroelectric memory cells to be resistant to single event upsets and proton irradiation, and ferroelectric storage capacitors to be resistant to neutron exposure. In addition to radiation hardness, the fast programming times, virtually unlimited endurance, and low voltage, low power operation make ferroelectric memories ideal for space missions. Previously, a commercial double level metal 64-kilobit ferroelectric memory was presented. Although the capabilities of radiation hardened wafer fabrication facilities lag behind those of the most modern commercial wafer fabrication facilities, several paths to achieving radiation tolerant, dense ferroelectric memories are emerging. Both short and long term solutions are presented in this paper. Although worldwide major semiconductor companies are introducing commercial ferroelectric memories, funding limitations must be overcome to proceed with the development of high density, radiation tolerant ferroelectric memories.

Philpy, Stephen C.↗
DOE OSTI2024

R-Adaptivity to Enable Compression of Elementary Computations in Extreme-Scale Finite Element Simulators

Modern computing systems are capable of exascale calculations, which are revolutionizing the development and application of high-fidelity numerical models in computational science and engineering. While these systems continue to grow in processing power, the available system memory has not increased commensurately, and electrical power consumption continues to grow. A predominant approach to limit the memory usage in large-scale applications is to exploit the abundant processing power and continually recompute many low-level simulation quantities, rather than storing them. However, this approach can adversely impact the throughput of the simulation and diminish the benefits of modern computing architectures. We present three novel contributions to reduce the memory burden while maintaining, and sometimes improving, performance in simulations based on finite element discretizations. The first contribution develops dictionary-based data compression schemes that detect and exploit the structure of the discretization, due to redundancies across the finite element mesh. While these schemes are shown to reduce memory requirements by more than 99% on meshes with large numbers of identical mesh cells, there are applications where this structure does not exist. The second contribution leverages a recently developed augmented Lagrangian optimization algorithm to enable r-adaptivity for meshes with the goal of enhancing the redundancies in the mesh. The third contribution extends these methods to patch-based linear solvers and preconditioners by compressing local matrices. Numerical results demonstrate the effectiveness of the proposed methods to detect, enhance and exploit mesh structure on a suite of examples inspired by large-scale applications.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1971

Nonvolatile read/write memory element - A concept

Memory, with limited number of programming cycles, is achieved by using verticle, fusible links in series with oxide breakthrough elements. Memory elements are fabricated with integrated circuit technology and are ideal for low power digital computer application.

Cricchi, J. R.↗
DOE OSTI2022

Shape memory embolectomy devices and systems

An embolectomy device comprised of an expansion unit and a support unit is disclosed. The expansion unit can be actuated in response to one or more external stimuli, and the support unit, located proximately to the expansion unit, provides a force to hold the expansion unit in place and to further induce the expansion unit's radial expansion. The radial expansion of the expansion unit causes the expansion unit to physically contact a blood clot, enabling the blood clot to be removed. In some embodiments, the expansion unit can be fabricated from a shape memory polymer foam. In some embodiments the support unit can be fabricated from any elastic material including, without limitation, shape memory alloys.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2022

Analysis of Vector Particle-In-Cell (VPIC) memory usage optimizations on cutting-edge computer architectures

Vector Particle-In-Cell (VPIC) is one of the fastest plasma simulation codes in the world, with particle numbers ranging from one trillion on the first petascale system, Roadrunner, to ten trillion particles on the more recent Blue Waters supercomputer. As supercomputers continue to grow rapidly in size, so too does the gap between computing capability and memory capability. Current memory systems limit VPIC simulations greatly as the maximum number of particles that can be simulated directly depends on the available memory. In this study, we present a suite of VPIC memory optimizations (i.e., particle weight, half-precision, and fixed-point optimizations) that enable a significant increase in the number of particles in VPIC simulations. Here, we assess the optimizations’ impact on memory and runtime performance for a suite of cutting-edge computer architectures such has the NVIDIA V100 GPU, the IBM Power9, and the Fujitsu A64FX architectures. Our optimizations enable a 31.25% reduction in memory usage and up to 40% increase in the number of particles. This paper extends our work on developing particle storage format optimizations Tan et al.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1994

Confessions of a robot lobotomist

Since its inception, numerically controlled (NC) machining methods have been used throughout the aerospace industry to mill, drill, and turn complex shapes by sequentially stepping through motion programs. However, the recent demand for more precision, faster feeds, exotic sensors, and branching execution have existing computer numerical control (CNC) and distributed numerical control (DNC) systems running at maximum controller capacity. Typical disadvantages of current CNC's include fixed memory capacities, limited communication ports, and the use of multiple control languages. The need to tailor CNC's to meet specific applications, whether it be expanded memory, additional communications, or integrated vision, often requires replacing the original controller supplied with the commercial machine tool with a more powerful and capable system. This paper briefly describes the process and equipment requirements for new controllers and their evolutionary implementation in an aerospace environment. The process of controller retrofit with currently available machines is examined, along with several case studies and their computational and architectural implications.

Gottshall, R. Marc↗
NASA NTRS1997

On the Floating Point Performance of the i860 Microprocessor

The i860 microprocessor is a pipelined processor that can deliver two double precision floating point results every clock. It is being used in the Touchstone project to develop a teraflop computer by the year 2000. With such high computational capabilities it was expected that memory bandwidth would limit performance on many kernels. Measured performance of three kernels showed performance is less than what memory bandwidth limitations would predict. This paper develops a model that explains the discrepancy in terms of memory latencies and points to some problems involved in moving data from memory to the arithmetic pipelines.

Lee, King↗
NASA NTRS1991

Efficient packing of patterns in sparse distributed memory by selective weighting of input bits

When a set of patterns is stored in a distributed memory, any given storage location participates in the storage of many patterns. From the perspective of any one stored pattern, the other patterns act as noise, and such noise limits the memory's storage capacity. The more similar the retrieval cues for two patterns are, the more the patterns interfere with each other in memory, and the harder it is to separate them on retrieval. A method is described of weighting the retrieval cues to reduce such interference and thus to improve the separability of patterns that have similar cues.

Kanerva, Pentti↗
DOE OSTI2025

UltraLiM: In-Memory Boolean Logic Architecture Using UltraRAM

Conventional computing architectures encounter ‘von Neumann’ and ‘memory wall’ bottlenecks which arise due to the back-and-forth data movement between the physically separate memory and processing units and the speed mismatch between them, respectively. These bottlenecks hurt both energy efficiency and the throughput of computing systems. To address these challenges, in-memory computing architectures have emerged as a promising alternative. They reduce the need for frequent data movement by executing different computing tasks inside the memory system. Here, we present UltraLiM, a logic-in-memory architecture using the UltraRAM-based memory system. UltraRAM holds the promise of developing a ‘universal memory’, overcoming the limitations of charge-based memories thanks to their non-volatile behavior with lower operating voltage. This work presents an in-memory computing architecture that integrates an UltraRAM-based memory array with a custom-designed peripheral circuitry. With this architecture, we can perform various in-memory Boolean logic operations (such as NOT, NAND, NOR, and XOR) in a single cycle. Leveraging the separate read-write paths in the UltraRAM-based memory array, we optimize read operations without encountering design conflicts. This optimization enhances the sense margin, enabling the use of simpler peripheral circuitry for in-memory logic operations.

Alam, Shamiul [University of Tennessee, Knoxville ↗