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DOE OSTI2022

Design-Technology Co-Optimization for NVM-based Neuromorphic Processing Elements

An emerging use-case of machine learning (ML) is to train a model on a high-performance system and deploy the trained model on energy-constrained embedded systems. Neuromorphic hardware platforms, which operate on principles of the biological brain, can significantly lower the energy overhead of a machine learning inference task, making these platforms an attractive solution for embedded ML systems. In this paper, we present a design-technology tradeoff analysis to implement such inference tasks on the processing elements (PEs) of a Non-Volatile Memory (NVM)-based neuromorphic hardware. Through detailed circuit-level simulations at scaled process technology nodes, we show the negative impact of technology scaling on the information-processing latency, which impacts the quality-of-service (QoS) of an embedded ML system. At a finer granularity, the latency inside a PE depends on 1) the delay introduced by parasitic components on its current paths, and 2) the varying delay to sense different resistance states of its NVM cells. Based on these two observations, we make the following three contributions. First, on the technology front, we propose an optimization scheme where the NVM resistance state that takes the longest time to sense is set on current paths having the least delay, and vice versa, reducing the average PE latency, which improves the QoS. Second, on the architecture front, we introduce isolation transistors within each PE to partition it into regions that can be individually power-gated, reducing both latency and energy. Finally, on the system-software front, we propose a mechanism to leverage the proposed technological and architectural enhancements when implementing a machine-learning inference task on neuromorphic PEs of the hardware. Evaluations with a recent neuromorphic hardware architecture show that our proposed design-technology co-optimization approach improves both performance and energy efficiency of machine-learning inference tasks without incurring high cost-per-bit.

42 ENGINEERING↗

DOE OSTI2021

Enabling Realistic Communications Evaluations for ADMS

Increasing penetration levels of inverter-based distributed energy resources (DERs) in distribution systems are creating challenges in system operation. Currently, wired or proprietary wireless communications are used by advanced distribution management systems (ADMS) to detect the state of the system and control the DERs for optimal operation. Wireless communications are an alternative solution that can enable connectivity between the dispersed assets used in distribution system applications. As demand for the seamless integration of distributed energy resources (DERs) continues to increase, proper networking and communications systems are becoming important to support the DER infrastructure. This report summarizes validation of a private wireless LTE network in a laboratory environment. The purpose of this work is to 1) demonstrate the effectiveness of private wireless LTE communication for grid applications and 2) provide a means of evaluating latency and overall performance of wireless communication in grid applications. First, private wireless LTE communication was validated in a direct transfer trip relaying scenario as an example of one-way communications using grid equipment. This study provided a baseline understanding of the variation in latency for seven different kinds of wireless scenarios shown in Figure A below. As expected, weak (attenuated) wireless signal-based communication yielded the widest ranges in latency. When higher priority was set for the trip signal communication, this resulted in lower latency in communication timing. In the final phase of this project, the private wireless LTE network was validated using two-way communications in an advanced distribution management system (ADMS) testbed which was developed in the ESIF at NREL. The purpose of this was to study the impact of wireless communication on grid performance.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2023

IceNet for FireBox - A Berkeley Warehouse-Scale Computer

Berkeley’s FireBox is a next-generation warehouse-scale computer (WSC) that utilizes the energy-efficiency and bandwidth density of integrated silicon-photonic interconnects to enable a new high-bandwidth and low-latency network fabric connecting thousands of compute nodes to petabytes of DRAM and Flash storage. The high bandwidth, low latency and high connectivity of FireBox’s WSC network fabric (IceNet) will enable dramatic improvements in the overall system energy efficiency enabling fine-grain power control on system resources (processors, links and memory/storage components). IceNet is a special 3-stage photonic Clos network architected to achieve ultra-low-latency connectivity between processor nodes and memory, drastically cutting down on the energy wasted in resource idling (processors and memory stalled due to pending network requests). This is achieved by integration of the first and last switch stages into processor/memory hub clients and by heavy over-provisioning of the high-radix middle switches (FlareSwitches). A key hardware component developed in this program is an active laser power management photonic integrated circuits called LightSpark. It interacts with the FlareSwitch and provides laser power to a subset of occupied switch ports, increasing the utilization of laser light in the photonic network by an order of magnitude. In addition to guiding the laser power where it is needed, the laser-power management module enables both wavelength and laser redundancy, significantly increasing the robustness of the system. The goal of the IceNet fabric is to enable communication between 1000s of processor nodes and PBs of memory/storage with <100ns latency, <10pJ/b wall-plug energy cost at multiple Pb/s of available connectivity bandwidth. These metrics represent two-orders of magnitude improvement with respect to the status of current data-center technology.

42 ENGINEERING↗

DOE OSTI2025

EVSE Characterization: V2G EVSE Comparison

As part of the U.S. Department of Energy EVs@Scale consortium Next-Generation Profiles project, results and analysis from the characterization of high-power conductive and wireless charging infrastructure are presented. This characterization is conducted over a wide range of direct current (DC) current and DC voltage operation for nominal test conditions and off-nominal test conditions. Test plans and procedures were developed to define the test configurations and requirements, measurement parameters, and test procedures used throughout testing. Results from a 2024 study conducted on electric vehicle supply equipment (EVSE) characterization by the Idaho National Laboratory (INL) include two bi-directional vehicle-to-grid (V2G) capable EVSEs. These EVSE are referred to as V2G-EVSE9 and V2G-EVSE10. Laboratory testing is conducted at nominal test conditions to characterize the power transfer capabilities, efficiency, power factor, and other power quality metrics of the two DC EVSEs capable of V2G bi-directional power transfer. Results from testing show the performance is consistent for V2G-EVSE9 and V2G-EVSE10 when comparing charging to discharging performance, except for V2G-EVSE10 for power transfer when operating above 70% of the rated DC current. V2G-EVSE10 efficiency is >98% while charging and <91% while discharging at the same operating conditions, near maximum-rated current, at 300VDC. In contrast, V2G-EVSE9 results are consistent for charging and discharging. This EVSE is nearly 96% efficient while charging or discharging when operating over 50% of rated AC power. V2G EVSE performance is also characterized during off-nominal AC grid conditions involving AC voltage deviation (426 VAC to 518 VAC), AC frequency deviation of +2% (58.8 Hz to 61.2 Hz), and AC voltage harmonics injection. Many test conditions have little-to-no impact on performance characteristics of the two EVSEs; however, there are a few notable findings with significant power transfer capability impacts. AC voltage harmonics injection resulted in negative impacts on power quality attributes for both EVSEs, but with no impact on power transfer capability. Off-nominal AC voltage and frequency conditions resulted in unstable or lack of power transfer capability for both EVSEs. V2G-EVSE9 is unable to transfer power when AC voltage is >300V L-N. V2G-EVSE10 is unable to transfer power when AC frequency deviation exceeds +0.8%. V2G energy management system transient response and latency are quantified during laboratory testing. V2G-EVSE9 and V2G-EVSE10 utilize cloud-based V2G energy management systems that command the power transfer level between the EVSE and EV. The latency and response characteristics of the entire systems (web-based user interface, V2G energy management system, cellular communications, and EVSE response) are quantified through laboratory testing for V2G-EVSE9 and V2G-EVSE10. V2G-EVSE9 latency ranges from 0.8 to 1.8 seconds, whereas V2G-EVSE10 latency ranges from 3.4 to 8.8 seconds. The ramp rate to a change in power transfer request also differs between the two EVSEs. V2G-EVSE10 ramp rate ranges from 50% to -250% of rated AC power per second, whereas V2G-EVSE9 rate ranges from 95% to -95% of rated AC power per second. At the highest rate of change in power transfer, V2G-EVSE10 can change from full charge power to full discharge power in less than one second. The V2G EVSE characterization presented in this report provides valuable insights and results for use by numerous entities. This includes modeling and simulation organizations, decision makers, fleet planning, industry stakeholders, and many others involved with the development and deployment of electrified transportation technologies. Additional high-power DC chargers, bidirectional chargers, and inductive power transfer EVSE characterization results are anticipated from additional EVSE brands and models, which will be detailed in future publications in support of the U.S. Department of Energy EVs@Scale consortium Next-Gen Profiles project.

25 ENERGY STORAGE↗

DOE OSTI2023

ML-based Real-Time Control at the Edge: An Approach Using hls4ml

This study focuses on implementing a real-time control system for a particle accelerator facility that performs high energy physics experiments. A critical operating parameter in this facility is beam loss, which is the fraction of particles deviating from the accelerated proton beam into a cascade of secondary particles. Accelerators employ a large number of sensors to monitor beam loss. The data from these sensors is monitored by human operators who predict the relative contribution of different sub-systems to the beam loss. Using this information, they engage control interventions. In this paper, we present a controller to track this phenomenon in real-time using edge-Machine Learning (ML) and support control with low latency and high accuracy. We implemented this system on an Intel Arria 10 SoC. Optimizations at the algorithm, high-level synthesis, and interface levels to improve latency and resource usage are presented. Our design implements a neural network, which can predict the main source of beam loss (between two possible causes) at speeds up to 575 frames per second (fps) (average latency of 1.74 ms). The practical deployed system is required to operate at 320 fps, with a 3ms latency requirement, which has been met by our design successfully.

Shi, R.↗

DOE OSTI2024

HGQ: High Granularity Quantization for Real-time Neural Networks on FPGAs

Neural networks with sub-microsecond inference latency are required by many critical applications. Targeting such applications deployed on FPGAs, we present High Granularity Quantization (HGQ), a quantization-aware training framework that optimizes parameter bit-widths through gradient descent. Unlike conventional methods, HGQ determines the optimal bit-width for each parameter independently, making it suitable for hardware platforms supporting heterogeneous arbitrary precision arithmetic. In our experiments, HGQ shows superior performance compared to existing network compression methods, achieving orders of magnitude reduction in resource consumption and latency while maintaining the accuracy on several benchmark tasks. These improvements enable the deployment of complex models previously infeasible due to resource or latency constraints. HGQ is open-source and is used for developing next-generation trigger systems at the CERN ATLAS and CMS experiments for particle physics, enabling the use of advanced machine learning models for real-time data selection with sub-microsecond latency.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2021

Design Space Exploration of Emerging Memory Technologies for Machine Learning Applications

Memory design space exploration methods study memory systems’ performances and limitations before implementation. The computer memory design space has grown exponentially because of the enormous growth of memory types, memory controllers, and application software. Computer simulators are commonly used for memory design space exploration. However, complex memory simulations take an enormous amount of time. Hence, in this paper, we proposed a machine learning-based design space exploration method for dynamic random-access memory and non-volatile memory systems. We applied our method to the CosmoGAN and LeNet applications to predict the following six memory response parameters: (i) bandwidth, (ii) power, (iii) average latency, (iv) average total latency, (v) memory reads, and (vi) memory writes. Our experimental results show that machine learning models can predict memory response parameter values faster than simulations. We used support vector machine, random forest, and gradient boosting machine learning models. We observed that the support vector machine provides better performance for bandwidth, average latency, and average total latency. The random forest model works better for memory reads and writes. The gradient boosting model provides superior prediction performance for power. We provide a detailed discussion on learning curve characteristics, error analysis, and memory type recommendation.

Hasan, S M Shamimul↗

DOE OSTI2020

On the Marriage of Asynchronous Many Task Runtimes and Big Data: A Glance

The rise of the accelerator-based architectures and reconfigurable computing have showcased the weakness of software stack toolchains that still maintain a static view of the hardware instead of relying on a symbiotic relationship between static (e.g., compilers) and dynamic tools (e.g., runtimes). In the past decades, this need has given rise to adaptive runtimes with increasingly finer computational tasks. These finer tasks help to take advantage of the hardware by switching out when a long latency operation is encountered (because of the deeper memory hierarchies and new memory technologies that might target streaming instead of random access), thus trading off idle time for unrelated work. Examples of these finer task runtimes are Asynchronous Many Task (AMT) runtimes, in which highly efficient computational graphs run on a variety of hardware. Due to its inherent latency tolerant characteristics, Latency-sensitive applications, such as Graph Analytics and Big Data can effectively use these runtimes. This paper aims to present an example of how the careful design of an AMT can exploit the hardware substrate when faced with high latency applications such as the ones given in the Big Data domain. Moreover, with its introspection and adaptive capabilities, we aim to show the power of these runtimes when facing the changing requirements of the application workloads. We use the Performance Open Community Runtime (P-OCR) as our vehicle to demonstrate the concepts presented here.

adaptive runtime, big data analysis↗

DOE OSTI2025

LUNA: LUT-Based Neural Architecture for Fast and Low-Cost Qubit Readout

Qubit readout is a critical operation in quantum computing systems, which maps the analog response of qubits into discrete classical states. Deep neural networks (DNNs) have recently emerged as a promising solution to improve readout accuracy . Prior hardware implementations of DNN-based readout are resource-intensive and suffer from high inference latency, limiting their practical use in low-latency decoding and quantum error correction (QEC) loops. This paper proposes LUNA, a fast and efficient superconducting qubit readout accelerator that combines low-cost integrator-based preprocessing with Look-Up Table (LUT) based neural networks for classification. The architecture uses simple integrators for dimensionality reduction with minimal hardware overhead, and employs LogicNets (DNNs synthesized into LUT logic) to drastically reduce resource usage while enabling ultra-low-latency inference. We integrate this with a differential evolution based exploration and optimization framework to identify high-quality design points. Our results show up to a 10.95x reduction in area and 30% lower latency with little to no loss in fidelity compared to the state-of-the-art. LUNA enables scalable, low-footprint, and high-speed qubit readout, supporting the development of larger and more reliable quantum computing systems.

Farooq, M. A. [Arizona State U., Tempe]↗

DOE OSTI2020

Cyber‐physical system testbed for power system monitoring and wide‐area control verification

The electric power system is intrinsically a cyber‐physical system (CPS) with power flowing inthe physical system and information flowing in the cyber‐network. Testbeds arecrucial for understanding the cyber‐physical interactions and provideenvironments for prototyping novel applications. This study proposes afour‐layer architecture for CPS testbeds with emphases on communication networkemulation and networked physical components. A configurable software‐definednetwork is employed to bridge physical components with wide‐area applicationsfor closed‐loop control. In order to distribute physically coupled devices intomultiple software simulations, this study proposes a data broker setup based ona distributed messaging environment to achieve low‐latency data streaming. Thedecoupled design with data streaming allows for building testbed components asmodules and running them in a distributed manner. Case studies verify the databroker setup for low‐latency sensing and actuation, as well as the communicationemulation setup for the desired network latency. Also illustrated is a replayattack scenario using synchrophasors in the Western Electricity CoordinatingCouncil (WECC) 181‐bus system for demonstrating the closed‐loop cyber‐physicalsimulation capability of the testbed.

Cui, Hantao↗

DOE OSTI2021

Fast convolutional neural networks on FPGAs with hls4ml

We introduce an automated tool for deploying ultra low-latency, low-power deep neural networks with convolutional layers on field-programmable gate arrays (FPGAs). By extending the hls4ml library, we demonstrate an inference latency of 5 µs using convolutional architectures, targeting microsecond latency applications like those at the CERN Large Hadron Collider. Considering benchmark models trained on the Street View House Numbers Dataset, we demonstrate various methods for model compression in order to fit the computational constraints of a typical FPGA device used in trigger and data acquisition systems of particle detectors. In particular, we discuss pruning and quantization-aware training, and demonstrate how resource utilization can be significantly reduced with little to no loss in model accuracy. We show that the FPGA critical resource consumption can be reduced by 97% with zero loss in model accuracy, and by 99% when tolerating a 6% accuracy degradation.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2022

Lightweight jet reconstruction and identification as an object detection task

We apply object detection techniques based on deep convolutional blocks to end-to-end jet identification and reconstruction tasks encountered at the CERN large hadron collider (LHC). Collision events produced at the LHC and represented as an image composed of calorimeter and tracker cells are given as an input to a Single Shot Detection network. The algorithm, named PFJet-SSD performs simultaneous localization, classification and regression tasks to cluster jets and reconstruct their features. This all-in-one single feed-forward pass gives advantages in terms of execution time and an improved accuracy w.r.t. traditional rule-based methods. A further gain is obtained from network slimming, homogeneous quantization, and optimized runtime for meeting memory and latency constraints of a typical real-time processing environment. We experiment with 8-bit and ternary quantization, benchmarking their accuracy and inference latency against a single-precision floating-point. We show that the ternary network closely matches the performance of its full-precision equivalent and outperforms the state-of-the-art rule-based algorithm. Finally, we report the inference latency on different hardware platforms and discuss future applications.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2024

Accelerating data acquisition with FPGA-based edge machine learning: a case study with LCLS-II

New scientific experiments and instruments generate vast amounts of data that need to be transferred for storage or further processing, often overwhelming traditional systems. Edge machine learning (EdgeML) addresses this challenge by integrating machine learning (ML) algorithms with edge computing, enabling real-time data processing directly at the point of data generation. EdgeML is particularly beneficial for environments where immediate decisions are required, or where bandwidth and storage are limited. In this paper, we demonstrate a high-speed configurable ML model in a fully customizable EdgeML system using a field programmable gate array (FPGA). Our demonstration focuses on an angular array of electron spectrometers, referred to as the ‘CookieBox,’ developed for the Linac Coherent Light Source II project. The EdgeML system captures 51.2 Gbps from a 6.4 GS s −1 analog to digital converter and is designed to integrate data pre-processing and ML inside an FPGA. Our implementation achieves an inference latency of 0.2 µs for the ML model, and a total latency of 0.4 µs for the complete EdgeML system, which includes pre-processing, data transmission, digitization, and ML inference. The modular design of the system allows it to be adapted for other instrumentation applications requiring low-latency data processing.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2023

A Pulse Generation Framework with Augmented Program-aware Basis Gates and Criticality Analysis

Near-term intermediate scale quantum (NISQ) de- vices are subject to considerable noise and short coherence time. Consequently, it is critical to minimize circuit execution latency. Traditionally, each basis gate of a transpiled circuit is decoded into a fixed episode of the device control pulses. Recently, people started to investigate merged pulse generation for customized gates through quantum optimal control (QOC). However, existing QOC approaches face the challenges of (i) restricted search space due to prohibitive compilation overhead; (ii) suboptimal end-to-end performance due to aggressive local optimization and falsely introduced dependency among the customized gates; (iii) inadequate adaptivity towards system calibration, which is critical for NISQ devices. In this work, we propose PAQOC, a novel QOC framework that can (i) automatically detect frequently encountered gate patterns in the logical circuit by modeling the problem as a subgraph mining process and reuse these patterns to enable much larger search space exploration (i.e., program aware); (ii) systemically construct customized gate-set based on the impact to the overall program latency (i.e., criticality-aware); and (iii) quickly adapt to system re-calibration thanks to the small-scale pattern-based gate generation (i.e., adaptivity-aware). PAQOC achieves a good tradeoff between circuit performance and compilation time, allowing fully automatic, single stop, ad- hoc customized pulse generation for more efficient execution of user programs on NISQ devices. Evaluations using fifteen applications show that PAQOC can achieve on average 1.95× speedup of the circuit latency and achieve on average 36.7% reduction in compilation overhead. With PAQOC, circuits can run faster with reduced noise, allowing deeper circuits to be tested within the coherence time of present NISQ platforms.

Chen, Yanhao↗

DOE OSTI2022

A Data-Driven Algorithm for Enabling Delay Tolerance in Resilient Microgrid Controls Using Dynamic Mode Decomposition

The increased implementation of smart grid technologies in the power distribution grid presents unique opportunities that enable resiliency, but also brings challenges motivating needs for novel solutions and mitigation techniques. The bi-directional power and data flow allow for the grid to operate with increased resiliency, which is the ability to avoid discontinuity of service to end-use loads during extreme events. However, in applications where control of the distribution grid or microgrid relies on communication networks, the degradation of communication systems in the form of loss or high latency can cause maloperation and result in loss of end-use loads. Here this paper presents a novel framework to enable delay tolerance of centralized microgrid control schemes to mitigate communication system latency impacts and guarantee successful control action. We demonstrate the delay tolerance on a control scheme that operates a battery energy storage system (BESS) to offset the sudden loss of generation and maintain system frequency. During periods of severely degraded communication system performance, the proposed delay-tolerant algorithm compensates for the latency by utilizing a data-driven model generated at the device level using dynamic mode decomposition (DMD) to determine the performance of the communications. The DMD technique predicts the system’s frequency using device-level terminal measurements and provides updated control signals. The HELICS cosimulation platform evaluates the cyber-physical interaction of the power system model in GridLAB-D, the centralized control agent in Python, and the discrete network model in NS-3. The framework is tested and validated on the IEEE-123 node system modified to represent a networked remote microgrid model, and the results show an improvement in the dynamic performance

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2026

ML–Enabled FPGA Framework for Fast Quantum State Discrimination in Mid-Circuit Measurement Regimes

Accurate and low-latency quantum state discrimination is essential for protocols involving mid-circuit measurement (MCM) and conditional feed-forward. In superconducting quantum systems, conventional readout pipelines transfer measurement data to host processors for post-processing, introducing millisecond-scale delays that far exceed qubit coherence times. To overcome this bottleneck, we present an in-situ machine learning (ML) inference engine implemented on an FPGA for real-time quantum state discrimination. Our design performs inference directly on digitized readout signals with 40 ns latency, supports both qubit and qutrit readout, and enables conditional operations without host-side intervention. This capability is critical for MCM and for feedback-driven protocols such as quantum error correction. We validate the system on superconducting transmon hardware, demonstrating robust discrimination fidelity across multiple qubit and qutrit channels. We further demonstrate conditional qutrit logic driven by FPGA-resident classification, highlighting the potential of low-latency ML-on-FPGA control for NISQ applications and scalable fault-tolerant quantum computing.

Vora, Neel [Lawrence Berkeley National Laboratory ↗

DOE OSTI2026

FLYING SERVING: On-the-Fly Parallelism Switching for Large Language Model Serving

Production LLM serving must simultaneously deliver high throughput, low latency, and sufficient context capacity under non-stationary traffic and mixed request requirements. Data parallelism (DP) maximizes throughput by running independent replicas, while tensor parallelism (TP) reduces per-request latency and pools memory for long-context inference. However, existing serving stacks typically commit to a static parallelism configuration at deployment; adapting to bursts, priorities, or long-context requests is often disruptive and slow. We present Flying Serving, a vLLM-based system that enables online DP-TP switching without restarting engine workers. Flying Serving makes reconfiguration practical by virtualizing the state that would otherwise force data movement: (i) a zero-copy Model Weights Manager that exposes TP shard views on demand, (ii) a KV Cache Adaptor that preserves request KV state across DP/TP layouts, (iii) an eagerly initialized Communicator Pool to amortize collective setup, and (iv) a deadlock-free scheduler that coordinates safe transitions under execution skew. Across three popular LLMs and realistic serving scenarios, Flying Serving improves performance by up to 4.79 × under high load and 3.47 × under low load while supporting latency- and memory-driven requests.

Gao, Shouwei [ORNL]↗

DOE OSTI2022

Multifidelity DRAM Simulation in SST [Poster]

We will always want to speed up simulation. While architects are able to pick between levels of detail when designing simulation, we will find further speed-up if we can adjust the level of detail during simulation, depending on the behavior of the simulated components. We create a simple fixed-latency model for each phase. On the first execution of a phase, we record the average latency of accesses. On subsequent executions, we skip DRAMSin 3 and send the response back using the average latency.

97 MATHEMATICS AND COMPUTING↗