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NASA NTRS2005

Reliability Assessment of Advanced Flip-clip Interconnect Electronic Package Assemblies under Extreme Cold Temperatures (-190 and -120 C)

Flip-chip interconnect electronic package boards have been assembled, underfilled, non-destructively evaluated and subsequently subjected to extreme temperature thermal cycling to assess the reliability of this advanced packaging interconnect technology for future deep space, long-term, extreme temperature missions. In this very preliminary study, the employed temperature range covers military specifications (-55 C to 100 C), extreme cold Martian (-120 C to 115 C) and asteroid Nereus (-180 C to 25 C) environments. The resistance of daisy-chained, flip-chip interconnects were measured at room temperature and at various intervals as a function of extreme temperature thermal cycling. Electrical resistance measurements are reported and the tests to date have not shown significant change in resistance as a function of extreme temperature thermal cycling. However, the change in interconnect resistance becomes more noticeable with increasing number of thermal cycles. Further research work has been carried out to understand the reliability of flip-chip interconnect packages under extreme temperature applications (-190 C to 85 C) via continuously monitoring the daisy chain resistance. Adaptation of suitable diagnostic techniques to identify the failure mechanisms is in progress. This presentation will describe the experimental test results of flip-chip testing under extreme temperatures.

thermal cycling↗

NASA NTRS2000

IsoWAN: A NASA Science and Engineering Information and Services Framework

We believe that the next evolutionary step in supporting wide-area application and services delivery to customers is a network framework that provides for collocation of applications and services at distinct sites in the network, an interconnection between these sites that is performance optimized for these applications, and value-added services for applications.

IsoWAN↗

NASA NTRS1995

InP tunnel junction for InGaAs/InP tandem solar cells

Chemical beam epitaxy (CBE) has been shown to allow the growth of high quality materials with reproducible complex compositional and doping profiles. The main advantage of CBE compared to metalorganic chemical vapor deposition (MOCVD), the most popular technique for InP-based photovoltaic device fabrication, is the ability to grow high purity epilayers at much lower temperatures (450-530 C). We have previously shown that CBE is perfectly suited toward the fabrication of complex photovoltaic devices such as InP/InGaAs monolithically integrated tandem solar cells, because its low process temperature preserves the electrical characteristics of the InGaAs tunnel junction commonly used as an ohmic interconnect. In this work using CBE for the fabrication of optically transparent (with respect to the bottom cell) InP tunnel diodes is demonstrated. Epitaxial growth were performed in a Riber CBE 32 system using PH3 and TMIn as III and V precursors. Solid Be (p-type) and Si (n-type) have been used as doping sources, allowing doping levels up to 2 x 10(exp -19)/cu cm and 1 x 10(exp -19)/cu cm for n and p type respectively. The InP tunnel junction characteristics and the influence of the growth's conditions (temperature, growth rate) over its performance have been carefully investigated. InP p(++)/n(++) tunnel junction with peak current densities up to 1600 A/sq cm and maximum specific resistivities (V(sub p)/I(sub p) - peak voltage to peak current ratio) in the range of 10(exp -4) Omega-sq cm were obtained. The obtained peak current densities exceed the highest results previously reported for their lattice matched counterparts, In(0.53)Ga( 0.47)As and should allow the realization of improved minimal absorption losses in the interconnect InP/InGaAs tandem devices for Space applications. Owing to the low process temperature required for the top cell, these devices exhibit almost no degradation of its characteristics after the growth of subsequent thick InP layer suggesting minimal doping cross diffusion in the narrow space-charge region (approximately 1-5 nm) of the device. The fabrication of tandem devices using InP tunnel diodes as interconnect is in progress and will be reported at the conference.

Vilela, M. F.↗

NASA NTRS1992

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

Packaging schemes were developed that provide low-loss, hermetic enclosure for advanced monolithic microwave and millimeter-wave integrated circuits (MMICs). The package designs are based on a fused quartz substrate material that offers improved radio frequency (RF) performance through 44 gigahertz (GHz). The small size and weight of the packages make them appropriate for a variety of applications, including phased array antenna systems. Packages were designed in two forms; one for housing a single MMIC chip, the second in the form of a multi-chip phased array module. The single chip array module was developed in three separate sizes, for chips of different geometry and frequency requirements. The phased array module was developed to address packaging directly for antenna applications, and includes transmission line and interconnect structures to support multi-element operation. All packages are fabricated using fused quartz substrate materials. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices. The package and test fixture designs were both developed in a generic sense, optimizing performance for a wide range of possible applications and devices.

Shalkhauser, K. A.↗

NASA NTRS1970

Applications of gap welding

Gap welding of electronic interconnections yields high strength joints, is easy to use, and allows visual inspection of the welding process. It is easily adaptable to automated circuit assembly.

Adams, G. D.↗

NASA NTRS1999

Nanoporous Silica Thermal Insulation for Space Shuttle Cryogenic Tanks: A Case Study

Nanoporous silica (with typical 10-50 nm porous radii) has been benchmarked for thermal insulators capable of maintaining a 150 K/cm temperature gradient. For cryogenic use in aerospace applications, the combined features for low-density, high thermal insulation factors, and low temperature compatibility are demonstrated in a prototype sandwich structure between two propulsion tanks. Theoretical modelling based on a nanoscale fractal structure suggest that the thermal conductivity scales proportionally (exponent, 1.7) with the material density-lower density increases the thermal insulation rating. Computer simulations, however, support the optimization tradeoff between material strength (Young moduli, proportional to density with exponent, 3.7), the characteristic (colloidal silica, less than 5 nm) particle size, and the thermal rating. The results of these simulations indicate that as nanosized particles are incorporated into the silica backbone, the resulting physical properties will be tailored by the smallest characteristic length and their fractal interconnections (dimension and fractal size). The application specifies a prototype panel which takes advantage of the processing flexibility inherent in sol-gel chemistry.

Noever, David A.↗

NASA NTRS1997

Novel Highly Parallel and Systolic Architectures Using Quantum Dot-Based Hardware

VLSI technology has made possible the integration of massive number of components (processors, memory, etc.) into a single chip. In VLSI design, memory and processing power are relatively cheap and the main emphasis of the design is on reducing the overall interconnection complexity since data routing costs dominate the power, time, and area required to implement a computation. Communication is costly because wires occupy the most space on a circuit and it can also degrade clock time. In fact, much of the complexity (and hence the cost) of VLSI design results from minimization of data routing. The main difficulty in VLSI routing is due to the fact that crossing of the lines carrying data, instruction, control, etc. is not possible in a plane. Thus, in order to meet this constraint, the VLSI design aims at keeping the architecture highly regular with local and short interconnection. As a result, while the high level of integration has opened the way for massively parallel computation, practical and full exploitation of such a capability in many applications of interest has been hindered by the constraints on interconnection pattern. More precisely. the use of only localized communication significantly simplifies the design of interconnection architecture but at the expense of somewhat restricted class of applications. For example, there are currently commercially available products integrating; hundreds of simple processor elements within a single chip. However, the lack of adequate interconnection pattern among these processing elements make them inefficient for exploiting a large degree of parallelism in many applications.

Fijany, Amir↗

NASA NTRS1971

Ceramic wiring board increases packaging density of electronic modules

Ceramic multilayer wiring board interconnects large scale integration /LSI/ modules which dissipate nearly 2W/cc. Extremely high packaging density is possible by application of alumina cover hermetically sealed to board. Signal interconnections are completely dependent on transfer heat between layers.

Hamley, L. D.↗

NASA NTRS2003

Using SPEEDES to simulate the blue gene interconnect network

JPL and the Center for Advanced Computer Architecture (CACR) is conducting application and simulation analyses of BG/L in order to establish a range of effectiveness for the Blue Gene/L MPP architecture in performing important classes of computations and to determine the design sensitivity of the global interconnect network in support of real world ASCI application execution.

SPEEDES BlueGene/L BG/L system-on-a-chip↗

NASA NTRS1979

High temperature - low mass solar blanket

Interconnect materials and designs for use with ultrathin silicon solar cells are discussed, as well as the results of an investigation of the applicability of parallel-gap resistance welding for interconnecting these cells. Data relating contact pull strength and cell electrical degradation to variations in welding parameters such as time, voltage and pressure are presented. Methods for bonding ultrathin cells to flexible substances and for bonding thin (75 micrometers) covers to these cells are described. Also, factors influencing fabrication yield and approaches for increasing yield are discussed. The results of vacuum thermal cycling and thermal soak tests on prototype ultrathin cell test coupons and one solar module blanket are presented.

Mesch, H. G.↗

NASA NTRS1979

Signal-interleaving device

Interleaving devices combine and duplicate optical electronic and other energy-saving signals in signal processing applications necessary for recording heads in interconnecting logic elements in computers and in data transmission systems. Simple cubic interleaver is characterized by high energy transmission and potentiality for low cost fabrication, and is designed to be easily interconnected with other signal processing elements.

Fischer, J. R.↗

NASA NTRS1993

SPOT4 Operational Control Center (CMP)

CNES(F) is responsible for the development of a new generation of Operational Control Center (CMP) which will operate the new heliosynchronous remote sensing satellite (SPOT4). This Operational Control Center takes large benefit from the experience of the first generation of control center and from the recent advances in computer technology and standards. The CMP is designed for operating two satellites all the same time with a reduced pool of controllers. The architecture of this CMP is simple, robust, and flexible, since it is based on powerful distributed workstations interconnected through an Ethernet LAN. The application software uses modern and formal software engineering methods, in order to improve quality and reliability, and facilitate maintenance. This software is table driven so it can be easily adapted to other operational needs. Operation tasks are automated to the maximum extent, so that it could be possible to operate the CMP automatically with very limited human interference for supervision and decision making. This paper provides an overview of the SPOTS mission and associated ground segment. It also details the CMP, its functions, and its software and hardware architecture.

Zaouche, G.↗

NASA NTRS1994

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Sewell, James S.↗

NASA NTRS1995

Optical Interconnection Via Computer-Generated Holograms

Method of free-space optical interconnection developed for data-processing applications like parallel optical computing, neural-network computing, and switching in optical communication networks. In method, multiple optical connections between multiple sources of light in one array and multiple photodetectors in another array made via computer-generated holograms in electrically addressed spatial light modulators (ESLMs). Offers potential advantages of massive parallelism, high space-bandwidth product, high time-bandwidth product, low power consumption, low cross talk, and low time skew. Also offers advantage of programmability with flexibility of reconfiguration, including variation of strengths of optical connections in real time.

Liu, Hua-Kuang↗

NASA NTRS1992

LinkWinds: An Approach to Visual Data Analysis

The Linked Windows Interactive Data System (LinkWinds) is a prototype visual data exploration and analysis system resulting from a NASA/JPL program of research into graphical methods for rapidly accessing, displaying and analyzing large multivariate multidisciplinary datasets. It is an integrated multi-application execution environment allowing the dynamic interconnection of multiple windows containing visual displays and/or controls through a data-linking paradigm. This paradigm, which results in a system much like a graphical spreadsheet, is not only a powerful method for organizing large amounts of data for analysis, but provides a highly intuitive, easy to learn user interface on top of the traditional graphical user interface.

Jacobson, Allan S.↗

NASA NTRS1978

Bank Terminals

In the photo, employees of the UAB Bank, Knoxville, Tennessee, are using Teller Transaction Terminals manufactured by SCI Systems, Inc., Huntsville, Alabama, an electronics firm which has worked on a number of space projects under contract with NASA. The terminals are part of an advanced, computerized financial transaction system that offers high efficiency in bank operations. The key to the system's efficiency is a "multiplexing" technique developed for NASA's Space Shuttle. Multiplexing is simultaneous transmission of large amounts of data over a single transmission link at very high rates of speed. In the banking application, a small multiplex "data bus" interconnects all the terminals and a central computer which stores information on clients' accounts. The data bus replaces the maze-of wiring that would be needed to connect each terminal separately and it affords greater speed in recording transactions. The SCI system offers banks real-time data management through constant updating of the central computer. For example, a check is immediately cancelled at the teller's terminal and the computer is simultaneously advised of the transaction; under other methods, the check would be cancelled and the transaction recorded at the close of business. Teller checkout at the end of the day, conventionally a time-consuming matter of processing paper, can be accomplished in minutes by calling up a summary of the day's transactions. SCI manufactures other types of terminals for use in the system, such as an administrative terminal that provides an immediate printout of a client's account, and another for printing and recording savings account deposits and withdrawals. SCI systems have been installed in several banks in Tennessee, Arizona, and Oregon and additional installations are scheduled this year.

Source record↗

NASA NTRS1997

Preliminary reliability evaluation of flip chip on flex interconnect technology

The study was carried out to evaluate the flip-chip-on-flex (FCOF) interconnection process in order to determine its feasibility for space flight applications. The key objectives were to: develop and apply simple and cost effective process steps needed to manufacture FCOFs and build test samples; perform a preliminary technology validation, and determine any initial environmental or application risks. The FCOF was shown to be simpler and more economical than other chip interconnection schemes.

Shaw, Jack J.↗

NASA NTRS1979

High temperature, low mass solar blanket development

This paper presents methods of incorporating ultrathin silicon solar cells into photovoltaic blankets for space applications. This type of cell has the highest power-to-mass ratio and best performance under space radiation of any silicon solar cell. Interconnect materials and designs, and the results of the investigation of the applicability of parallel-gap resistance welding for interconnecting ultrathin cells are discussed. Data relating contact pull strength and cell electrical degradation to welding parameters such as time, voltage, and pressure are presented. Methods for bonding ultrathin cells to flexible substrates and for bonding thin covers to these cells are described, and the results of vacuum thermal cycling and thermal soak tests on prototype ultrathin cell test coupons are included.

Mesch, H. G.↗