Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “integrated circuit modeling”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS2008

SiC JFET Transistor Circuit Model for Extreme Temperature Range

A technique for simulating extreme-temperature operation of integrated circuits that incorporate silicon carbide (SiC) junction field-effect transistors (JFETs) has been developed. The technique involves modification of NGSPICE, which is an open-source version of the popular Simulation Program with Integrated Circuit Emphasis (SPICE) general-purpose analog-integrated-circuit-simulating software. NGSPICE in its unmodified form is used for simulating and designing circuits made from silicon-based transistors that operate at or near room temperature. Two rapid modifications of NGSPICE source code enable SiC JFETs to be simulated to 500 C using the well-known Level 1 model for silicon metal oxide semiconductor field-effect transistors (MOSFETs). First, the default value of the MOSFET surface potential must be changed. In the unmodified source code, this parameter has a value of 0.6, which corresponds to slightly more than half the bandgap of silicon. In NGSPICE modified to simulate SiC JFETs, this parameter is changed to a value of 1.6, corresponding to slightly more than half the bandgap of SiC. The second modification consists of changing the temperature dependence of MOSFET transconductance and saturation parameters. The unmodified NGSPICE source code implements a T(sup -1.5) temperature dependence for these parameters. In order to mimic the temperature behavior of experimental SiC JFETs, a T(sup -1.3) temperature dependence must be implemented in the NGSPICE source code. Following these two simple modifications, the Level 1 MOSFET model of the NGSPICE circuit simulation program reasonably approximates the measured high-temperature behavior of experimental SiC JFETs properly operated with zero or reverse bias applied to the gate terminal. Modification of additional silicon parameters in the NGSPICE source code was not necessary to model experimental SiC JFET current-voltage performance across the entire temperature range from 25 to 500 C.

Neudeck, Philip G.↗
DOE OSTI2024

Strong Zero Modes in Integrable Quantum Circuits

It is a classic result that certain interacting integrable spin chains host robust edge modes known as strong zero modes (SZMs). In this Letter, we extend this result to the Floquet setting of local quantum circuits, focusing on a prototypical model providing an integrable Trotterization for the evolution of the XXZ Heisenberg spin chain. By exploiting the algebraic structures of integrability, we show that an exact SZM operator can be constructed for these integrable quantum circuits in certain regions of parameter space. Our construction, which recovers a well-known result by Paul Fendley in the continuous-time limit, relies on a set of commuting transfer matrices known from integrability, and allows us to easily prove important properties of the SZM, including normalizabilty. Our approach is different from previous methods and could be of independent interest even in the Hamiltonian setting. Furthermore, our predictions, which are corroborated by numerical simulations of infinite-temperature autocorrelation functions, are potentially interesting for implementations of the XXZ quantum circuit on available quantum platforms.

1-dimensional spin chains↗
NASA NTRS1991

Addressable-Matrix Integrated-Circuit Test Structure

Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

Sayah, Hoshyar R.↗
NASA NTRS2005

Radiation Testing and Evaluation Issues for Modern Integrated Circuits

Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

LaBel, Kenneth A.↗
NASA NTRS1971

Development and performance of pulse-width-modulated static inverter and converter modules

Pulse-width-modulated inverter and converter modules are being developed for modular aerospace electrical power systems. The modules, rate 2.5 kilowatts per module and 10-minute - 150-percent overload, operate from 56 volts dc. The converter module provides two output voltages: a nominal link voltage of 200 volts dc when used with the inverter, and 150 volts dc to a load bus when used separately. The inverter module output is 400-hertz, sinusoidal, three-phase, 120/208 volts. Tests of breadboard models with standard parts and integrated circuits show rated power efficiencies of 71.4 and 85.1 percent and voltage regulation of 5 and 3.1 percent for inverter and converter modules, respectively. Sine-wave output distortion is 0.74 percent.

Pittman, P. F.↗
NASA NTRS1997

Video display engineering and optimization system

A video display engineering and optimization CAD simulation system for designing a LCD display integrates models of a display device circuit, electro-optics, surface geometry, and physiological optics to model the system performance of a display. This CAD system permits system performance and design trade-offs to be evaluated without constructing a physical prototype of the device. The systems includes a series of modules which permit analysis of design trade-offs in terms of their visual impact on a viewer looking at a display.

Larimer, James↗
NASA NTRS1985

Fault models

A major problem in the qualification of integrated circuit cells and in the development of adequate tests for the circuits is to lack of information on the nature and density of fault models. Some of this information is being obtained from the test structures. In particular, the Pinhole Array Capacitor is providing values for the resistance of gate oxide shorts, and the Addressable Inverter Matrix is providing values for parameter distributions such as noise margins. Another CMOS fault mode, that of the open-gated transistor, is examined and the state of the transistors assessed. Preliminary results are described for a number of open-gated structures such as transistors, inverters, and NAND gates. Resistor faults are applied to various CMOS gates and the time responses are noted. The critical value for the resistive short to upset the gate response was determined.

Sayah, H. R.↗
NASA NTRS1986

A lumped parameter mathematical model for simulation of subsonic wind tunnels

Equations for a lumped parameter mathematical model of a subsonic wind tunnel circuit are presented. The equation state variables are internal energy, density, and mass flow rate. The circuit model is structured to allow for integration and analysis of tunnel subsystem models which provide functions such as control of altitude pressure and temperature. Thus the model provides a useful tool for investigating the transient behavior of the tunnel and control requirements. The model was applied to the proposed NASA Lewis Altitude Wind Tunnel (AWT) circuit and included transfer function representations of the tunnel supply/exhaust air and refrigeration subsystems. Both steady state and frequency response data are presented for the circuit model indicating the type of results and accuracy that can be expected from the model. Transient data for closed loop control of the tunnel and its subsystems are also presented, demonstrating the model's use as a control analysis tool.

Krosel, S. M.↗
DOE OSTI2022

A method for automated modeling of plasma shape control response in tokamaks

Here, a simple method commonly used in modeling of tokamak conductor and plasma response for plasma control has been extended to allow more general modeling of tokamak PF conductor circuits. This extension combines a previously existing method for integrating plasma response and tokamak circuits with a more capable circuit modeling technique derived from the theory that underlies present-day automatic circuit simulation codes. This combined method can incorporate any combination of inductors (e.g., coils), resistors, capacitors, voltage sources, and current sources, while retaining the same model structure and ease of interpretation as the simple method. For many tokamaks, use of this extended method would not be the preferred approach, but for certain devices or for specialized models of a device, it is useful and occasionally essential. For example, the method has enabled fast and automated modeling of the complicated and daily-changing circuit topology used in the DIII-D tokamak. This automated modeling is essential to the support of controller design for the frequently changing requirements for DIII-D plasmas. It is likely to also find application in the workflows for new device designs.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
NASA NTRS2012

Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

linear integrated circuits↗
NASA NTRS2008

Embedded ESD Protection Proof of Concept

The purpose of this project is to characterize and correlate Electrostatic Discharge (ESD) sensitivity levels of an Integrated Circuit (IC) package using Transmission Line Pulse (TLP) and Human Body Model (HBM) methods. This characterization will be used as a baseline ESD sensitivity level to demonstrate improvement to the ESD sensitivity of the IC package through the use of EPI-FLO(Trade Mark) Polymer Voltage Suppression (PVS) protection devices developed and manufactured by Electronic Polymers, Inc. (EPI).

Human Body Model (HBM) methods↗
DOE OSTI2026

A Unidirectional Two-Compartment Neuron Circuit with On-chip STDP learning

Most neuromorphic chips implement the single-compartment point neuron model where synapse circuits connect directly to a leaky integrate and fire (LIF) soma circuit. However, when using a biologically plausible soma circuit (e.g., Hodgkin-Huxley neuron model), an interface circuitry, such as a current conveyor circuit, is needed to transmit synaptic current to the soma circuit. This is especially true for ultra-low power neuron circuits, where membrane capacitance is on the order of 20 fF. This need for an interface circuit arises because the parasitic capacitance and leakage current caused by fabrication mismatch and second-order effects of the output transistors in the synapse circuits can disturb the spiking dynamics of the soma circuit if connected without an interface. Using an interface circuit to isolate the soma’s membrane capacitor from synapses resolves this issue. We propose to use a unidirectional resistor (a transconductance circuit) to connect the synapse and soma circuits instead of conventional current conveyor circuits. Using a biologically plausible spike pattern detection model, we show that the on-chip spike-timing-dependent plasticity (STDP) learning performance of the proposed unidirectional two-compartment neuron circuit is similar to a single-compartment circuit (with a current conveyor as an interface) and additionally, it is more power-efficient and biologically plausible. The chip is fabricated in the Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm technology node and comprises a single neuron circuit.

Gautam, Ashish [ORNL]↗
DOE OSTI2025

Characterizing and Modeling the Influence of Geometry on the Performance of Superconducting Nanowire Cryotrons

The scaling of superconducting nanowire detectors to larger arrays is often limited by room-temperature-readout cabling. Cryogenic integrated circuits constructed from nanowire cryotrons, or nanocryotrons, can address this limitation by performing signal processing on chip. In this study, we characterize key performance metrics of the nanocryotron to elucidate its potential as a logical element in cryogenic integrated circuits and develop an electro-thermal model to connect material parameters with device performance. We find that the performance of the nanocryotron depends on the device geometry, and trade-offs are associated with optimizing the gain, jitter, and energy dissipation. Here, we demonstrate that nanocryotrons fabricated on niobium nitride can achieve a grey zone less than 210 nA wide for a 5 ns long input pulse corresponding to a maximum achievable gain of 48 dB, an energy dissipation of less than 20 aJ per operation, and a jitter of less than 60 ps.

Superconductor↗
NASA NTRS1991

Designing Accelerated Tests Of Electromigration

Method for design of accelerated tests of electromigration (as in microscopic conductors in integrated circuits) based partly on simplified mathematical model of electromigration and partly on error analysis. Objective to determine quickly operating life of tested components under normal operating conditions by extrapolation from lifetime measurements at operating stresses greater than normal. Involves compromise between reducing testing time by increasing stresses and reducing uncertainty in extrapolated lifetime by decreasing stresses.

Buehler, Martin G.↗