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At least 73 records · Page 4

Fast Sideband Control of a Weakly Coupled Multimode Bosonic Memory

Circuit quantum electrodynamics (cQED) with superconducting cavities coupled to nonlinear circuits like transmons offers a promising platform for hardware-efficient quantum information processing. We address critical challenges in realizing this architecture by weakening the dispersive coupling while also demonstrating fast, high-fidelity multimode control by dynamically amplifying gate speeds through transmon-mediated sideband interactions. This approach enables transmon-cavity SWAP gates, for which we achieve speeds up to 30 times larger than the bare dispersive coupling. Combined with transmon rotations, this allows for efficient, universal state preparation in a single cavity mode, though achieving unitary gates and extending control to multiple modes remains a challenge. In this work, we overcome this by introducing two sideband control strategies: (1) a shelving technique that prevents unwanted transitions by temporarily storing populations in sideband-transparent transmon states and (2) a method that exploits the dispersive shift to synchronize sideband transition rates across chosen photon-number pairs to implement transmon-cavity SWAP gates that are selective on photon number. We leverage these protocols to prepare Fock and binomial code states across any of ten modes of a multimode cavity with millisecond cavity coherence times. We demonstrate the encoding of a qubit from a transmon into arbitrary vacuum and Fock state superpositions, as well as entangled NOON states of cavity mode pairs— a scheme extendable to arbitrary multimode Fock encodings. Furthermore, we implement a new binomial encoding gate that converts arbitrary transmon superpositions into binomial code states in $\qty{4}{\micro\second}$ (less than $1/\chi$), achieving an average post-selected final state fidelity of $\qty{96.3}{\percent}$ across different fiducial input states.

Huang, Jordan [Rutgers U., Piscataway]↗

Dynamically suppressing cavity dephasing induced by frequency fluctuations of a coupled nonlinear mode

High-coherence superconducting cavities offer a promising platform for quantum information, with long coherence times and negligible intrinsic dephasing. However, cavity control generally relies on nonlinear Josephson elements whose frequency fluctuations are inherited by the cavity as dephasing, potentially limiting control fidelities and eroding the noise bias used in error-correction protocols. Here, we introduce Stark-Assisted Flux-noise Evasion (SAFE), a hardware-efficient protocol that protects the cavity from inherited dephasing using only a weak off-resonant microwave drive applied to the nonlinear element. As a concrete setup, we analyze a 3D superconducting cavity dispersively coupled to a flux-tunable transmon (FTT) subject to $1/f$ flux noise. Analytical predictions are confirmed by Monte Carlo simulations with realistic parameters, which show that SAFE can extend the cavity dephasing time by more than an order of magnitude while keeping residual drive-induced decoherence subdominant.

Lu, Yunwei [Northwestern U.] (ORCID:00000003401756↗

Energy Efficient Engine combustor test hardware detailed design report

The Energy Efficient Engine (E3) Combustor Development effort was conducted as part of the overall NASA/GE E3 Program. This effort included the selection of an advanced double-annular combustion system design. The primary intent was to evolve a design which meets the stringent emissions and life goals of the E3 as well as all of the usual performance requirements of combustion systems for modern turbofan engines. Numerous detailed design studies were conducted to define the features of the combustion system design. Development test hardware was fabricated, and an extensive testing effort was undertaken to evaluate the combustion system subcomponents in order to verify and refine the design. Technology derived from this development effort will be incorporated into the engine combustion system hardware design. This advanced engine combustion system will then be evaluated in component testing to verify the design intent. What is evolving from this development effort is an advanced combustion system capable of satisfying all of the combustion system design objectives and requirements of the E3. Fuel nozzle, diffuser, starting, and emissions design studies are discussed.

Burrus, D. L.↗

Energy efficient engine combustor test hardware detailed design report

The combustor for the Energy Efficient Engine is an annular, two-zone component. As designed, it either meets or exceeds all program goals for performance, safety, durability, and emissions, with the exception of oxides of nitrogen. When compared to the configuration investigated under the NASA-sponsored Experimental Clean Combustor Program, which was used as a basis for design, the Energy Efficient Engine combustor component has several technology advancements. The prediffuser section is designed with short, strutless, curved-walls to provide a uniform inlet airflow profile. Emissions control is achieved by a two-zone combustor that utilizes two types of fuel injectors to improve fuel atomization for more complete combustion. The combustor liners are a segmented configuration to meet the durability requirements at the high combustor operating pressures and temperatures. Liner cooling is accomplished with a counter-parallel FINWALL technique, which provides more effective heat transfer with less coolant.

Zeisser, M. H.↗

Energy efficient engine: Fan test hardware detailed design report

A single stage fan and quarter stage booster were designed for the energy efficient engine. The fan has an inlet radius ratio of 0.342 and a specific flow rate of 208.9 Kg/S sq m (42.8 lbm/sec sq ft). The fan rotor has 32 medium aspect ratio (2.597) titanium blades with a partspan shroud at 55% blade height. The design corrected fan tip speed is 411.5 M/S (1350 ft/sec). The quarter stage island splits the total fan flow with approximately 22% of the flow being supercharged by the quarter stage rotor. The fan bypass ratio is 6.8. The core flow total pressure ratio is 1.67 and the fan bypass pressure ratio is 1.65. The design details of the fan and booster blading, and the fan frame and static structure for the fan configuration are presented.

Sullivan, T. J.↗

Error control techniques for satellite and space communications

Research activities related to error control techniques for satellite and space communication are reported. Specific areas of research include: coding gains for bandwidth efficient codes, hardware implementation of a bandwidth efficient coding scheme for the Hubble Space Telescope, construction of long trellis codes for use with sequential decoding, performance analysis of multilevel trellis codes, and M-algorithm decoding of trellis codes. Each topic is discussed in a corresponding paper that appears in the appendices.

Costello, Daniel J., Jr.↗

Hardware-in-the-Loop Efficiency Analysis of Tidal Power Systems

Marine renewable energy presents an opportunity for sustainable power in areas located near and in the marine environment. In particular, tidal energy offers a consistent and reliable resource. However, tidal energy harvesting systems seeking to take advantage of this resource face challenges associated with power electronics. Power conversion electronics struggle with low efficiencies, lack of off-the-shelf options for small-scale energy harvesting systems, and limited opportunities for testing with deployed turbines. This work demonstrates a hardware-in-the-loop experimental design and methodology for characterizing efficiency of tidal turbine power electronics and control methods. The suggested method removes barriers to testing these power electronics by eliminating the need for a physical tidal turbine and generator to produce accurate harvested tidal power profiles.

tidal turbine, hardware-in-the-loop, energy conver↗

Integration of Ag-CBRAM crossbars and Mott ReLU neurons for efficient implementation of deep neural networks in hardware

In-memory computing with emerging non-volatile memory devices (eNVMs) has shown promising results in accelerating matrix-vector multiplications. However, activation function calculations are still being implemented with general processors or large and complex neuron peripheral circuits. Here, we present the integration of Ag-based conductive bridge random access memory (Ag-CBRAM) crossbar arrays with Mott rectified linear unit (ReLU) activation neurons for scalable, energy and area-efficient hardware (HW) implementation of deep neural networks. We develop Ag-CBRAM devices that can achieve a high ON/OFF ratio and multi-level programmability. Compact and energy-efficient Mott ReLU neuron devices implementing ReLU activation function are directly connected to the columns of Ag-CBRAM crossbars to compute the output from the weighted sum current. We implement convolution filters and activations for VGG-16 using our integrated HW and demonstrate the successful generation of feature maps for CIFAR-10 images in HW. Our approach paves a new way toward building a highly compact and energy-efficient eNVMs-based in-memory computing system.

Mott insulators↗

Differentiable Neural Architecture, Mixed Precision and Accelerator Co-Search

Quantization, effective Neural Network architecture, and efficient accelerator hardware are three important design paradigms to maximize accuracy and efficiency. Mixed Precision Quantization is a process of assigning different precision to different Neural Network layers for optimized inference. Neural Architecture Search (NAS) is a process of automatically designing the neural network for a task and can also be extended to search for the precision of each weight and activation matrix. In this paper, we develop the following three methods: (i) Fast Differentiable Hardware-aware Mixed Precision Quantization Search method to find optimal precision, (ii) Joint Differentiable hardware-aware Architecture and Mixed Precision Quantization Co-search, (iii) Joint Accelerator, Architecture, and Precision triple co-search to find best possibilities in all the three worlds. We demonstrate the effectiveness of our proposed methods targeting Bitfusion accelerator by searching mixed precision models on MobilenetV2. We achieve better accuracy-latency trade-off models than the manually designed and previously proposed search methods.

97 MATHEMATICS AND COMPUTING↗

Critical Surface Cleaning and Verification Alternatives

A viewgraph presentation outlines the goal, scope, and background of the cleaning solvent HCFC 225G. HCFC 225G is compared to other cleaning solvents such as Freon 113 and HFE 7100. Test results of hardware submersion in HCFC 225G and Freon 113 are shown. Project accomplishments, average cleaning efficiency, and hardware qualification are discussed. Results show HCFC 225G is an excellent cleaning and verification solvent for industrial contaminants.

Melton, Donald M.↗

A Plug and Play GNC Architecture Using FPGA Components

The goal of Plug and Play, or PnP, is to allow hardware and software components to work together automatically, without requiring manual setup procedures. As a result, new or replacement hardware can be plugged into a system and automatically configured with the appropriate resource assignments. However, in many cases it may not be practical or even feasible to physically replace hardware components. One method for handling these types of situations is through the incorporation of reconfigurable hardware such as Field Programmable Gate Arrays, or FPGAs. This paper describes a phased approach to developing a Guidance, Navigation, and Control (GNC) architecture that expands on the traditional concepts of PnP, in order to accommodate hardware reconfiguration without requiring detailed knowledge of the hardware. This is achieved by establishing a functional based interface that defines how the hardware will operate, and allow the hardware to reconfigure itself. The resulting system combines the flexibility of manipulating software components with the speed and efficiency of hardware.

KrishnaKumar, K.↗

ExaSGD: 2022 Kernel Thrust Activities

The Kernel Thrust milestone ADSE22-407 covers the development of device-capable optimization algorithms and solvers technologies required by the ExaSGD project’s software stack in order to solve security-constrained alternating current optimal power flow (SC-ACOPF) problems on emerging exascale architectures. To this extent, in FY22 the main objective of the Kernel Thrust was (i) provide sparse optimization solver that runs efficiently on hardware accelerator devices (i.e., NVIDIA and AMD GPUs) to perform intra-node computations, (ii) strengthen the reliability and increase the performance of the mixed-dense sparse (MDS) solver of HiOp for deployment on the FY22 target architectures, Summit and Crusher, and (iii) increase performance by improving the mathematical algorithm and refining the parallel MPI-based implementation of the coarse-grain parallel solver HiOp-PriDec for capabilities deployment on the FY22 target architectures, Summit and Crusher. This document presents the developments and contributions done by the Kernels Thrust Team in FY22 toward completion of the above-mentioned objectives. These contributions progressed along four main development (sub)thrusts: (1) Design and implementation of a sparse optimization solver for use on hardware accelerators; (2) Improvement of the mathematical algorithm and of the parallel implementation of HiOp-PriDec to ensure readiness and efficient coarse-grain parallelism for FY23 target exascale machine; and (3) Support Software and Application Development Thrusts of the exaSGD project in their deployment of the project’s software stack on AMD- and NVIDIA-based architectures. The development of the sparse optimization solver (thrust 1 above) was new in FY22 and resulted in a new sparse solver in HiOp (available as of version 0.6). The second development thrust was a continuation of the efforts from FY21 and improved the mathematical algorithm and the communication strategy of the HiOp-PriDec solver. The last developement thrust is a large collaborative effort. Namely, the project’s teams from multiple labs (LLNL, PNNL, ORNL, and NREL) performed large-scale demonstration of the ExaSGD software stack, namely the optimization solvers of HiOp interfaced with the modeling front-end ExaGO and the stochastic sampler PowerScenarios. These demonstration efforts solved large-scale instances of the SC-ACOPF challenge problem of medium network sizes (10, 000-bus system) and large number of contingencies on Summit (NVIDIA accelerators) and Crusher (AMD accelerators) systems at ORNL.

97 MATHEMATICS AND COMPUTING↗

Energy efficient engine. Low pressure turbine test hardware detailed design report

The low pressure turbine for the energy efficient engine is a five-stage configuration with moderate aerodynamic loading incorporating advanced features of decambered airfoils and extended blade overlaps at platforms and shrouds. Mechanical integrity of 18,000 hours on flowpath components and 36,000 hours on all other components is achieved along with no aeromechanical instabilities within the steady-state operating range. Selection of a large number (156) of stage 4 blades, together with an increased stage 4 vane-to-blade gap, assists in achieving FAR 36 acoustic goals. Active clearance control (ACC) of gaps at blade tips and interstage seals is achieved by fan air cooling judiciously applied at responsive locations on the casing. This ACC system is a major improvement in preventing deterioration of the 0.0381 cm (0.015 in.) clearances required to meet the integrated-core/low-spool turbine efficiency goal of 91.1% and the light propulsion system efficiency goal of 91.7%.

Cherry, D. G.↗

Energy efficient engine high pressure turbine test hardware detailed design report

The high pressure turbine configuration for the Energy Efficient Engine is built around a two-stage design system. Moderate aerodynamic loading for both stages is used to achieve the high level of turbine efficiency. Flowpath components are designed for 18,000 hours of life, while the static and rotating structures are designed for 36,000 hours of engine operation. Both stages of turbine blades and vanes are air-cooled incorporating advanced state of the art in cooling technology. Direct solidification (DS) alloys are used for blades and one stage of vanes, and an oxide dispersion system (ODS) alloy is used for the Stage 1 nozzle airfoils. Ceramic shrouds are used as the material composition for the Stage 1 shroud. An active clearance control (ACC) system is used to control the blade tip to shroud clearances for both stages. Fan air is used to impinge on the shroud casing support rings, thereby controlling the growth rate of the shroud. This procedure allows close clearance control while minimizing blade tip to shroud rubs.

Halila, E. E.↗

A Survey: Handling Irregularities in Neural Network Acceleration with FPGAs

In the last decade, Artificial Intelligence (AI) through Deep Neural Networks (DNNs) has penetrated virtually every aspect of science, technology, and business. Many types of DNNs have been and continue to be developed, including Convolutional Neural Networks (CNNs), Recurrent Neural Net- works (RNNs), and Graph Neural Networks (GNNs). The overall problem for all of these Neural Networks (NNs) is that their target applications generally pose stringent constraints on latency and throughput, while also having strict accuracy requirements. There have been many previous efforts in creating hardware to accelerate NNs. The problem designers face is that optimal NN models typically have significant irregularities, making them hardware-unfriendly. In this paper, we first define the problems in NN acceleration by characterizing common irregularities in NN processing into 4 types; then we summarize the existing works that handle the four types of irregularities efficiently using hardware, especially FPGAs; finally, we provide a new vision of next-generation FPGA-based NN acceleration: that the emerging heterogeneity in the next-generation FPGAs is the key to achieving higher performance.

Geng, Tong↗

Fiber Optic Tactical Local Network (FOTLAN)

A 100 Mbit/s FDDI (fiber distributed data interface) network interface unit is described that supports real-time data, voice and video. Its high-speed interrupt-driven hardware architecture efficiently manages stream and packet data transfer to the FDDI network. Other enhancements include modular single-mode laser-diode fiber optic links to maximize node spacing, optic bypass switches for increased fault tolerance, and a hardware performance monitor to gather real-time network diagnostics.

Bergman, L. A.↗

A high performance FDDI NIU for streaming voice, video, and data

A 100-Mbit/s FDDI network interface unit (NIU) is described that supports real-time data, voice and video. Its high-speed interrupt-driven hardware architecture efficiently manages stream and packet data transfers to the FDDI network. Other enhancements include modular single-mode laser-dioce fiber optic links to maximize node spacing, optic bypass switches for increased fault tolerance, and a hardware performance monitor to gather real-time network diagnostics.

Bergman, L. A.↗