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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1988

Comparison of results from simple expressions for MOSFET parameter extraction

In this paper results are compared from a parameter extraction procedure applied to the linear, saturation, and subthreshold regions for enhancement-mode MOSFETs fabricated in a 3-micron CMOS process. The results indicate that the extracted parameters differ significantly depending on the extraction algorithm and the distribution of I-V data points. It was observed that KP values vary by 30 percent, VT values differ by 50 mV, and Delta L values differ by 1 micron. Thus for acceptance of wafers from foundries and for modeling purposes, the extraction method and data point distribution must be specified. In this paper measurement and extraction procedures that will allow a consistent evaluation of measured parameters are discussed.

Buehler, M. G.↗
NASA NTRS1993

Macro, mini, micro and nano (M(sup 3)N) technologies for the future

Microelectromechanical systems (MEMS), micro systems technologies (MST), and micromanufacturing are relatively recent phrases or acronyms that have become synonymous with the design, development, and manufacture of 'micro' devices and systems. Micromanufacturing encompasses MEMS or MST and, in addition, includes all of the processes involved in the production of micro things. Integration of mechanical and electrical components, including built-in computers, can be formed into systems which must be connected to the macroworld. Macro, mini, micro, and nano technologies are all a part of MEMS or micromanufacturing. At this point in the development of the technology, it is becoming apparent that mini systems, with micro components, could very well be the economic drivers of the technology for the foreseeable future. Initial research in the fabrication of microdevices using IC processing technology took place over thirty years ago. Anisotropic etching of silicon was used to produce piezoresistive diaphragms. Since the early 60's, there has been gradual progress in MEMS until the early 1980's when worldwide interest in the technology really started to develop. During this time high aspect ratio micromachining using x rays was started in Germany. In 1987 the concept of a 'silicon micromechanics foundry' was proposed. Since then the interest in the U.S., Germany, and Japan has increased to the point where hundreds of millions of dollars of research monies are being funneled into the technology (at least in Germany and Japan) and the technology has been classified as critical or as a technology or national importance by the U.S. government.

Friedrich, Craig R.↗
DOE OSTI2024

Improved coherence in optically defined niobium trilayer-junction qubits

Niobium offers the benefit of increased operating temperatures and frequencies for Josephson junctions, which are the core component of superconducting devices. However existing niobium processes are limited by more complicated fabrication methods and higher losses than now-standard aluminum junctions. Combining recent trilayer fabrication advancements, methods to remove lossy dielectrics and modern superconducting qubit design, we revisit niobium trilayer junctions and fabricate all-niobium transmons using only optical lithography. We characterize devices in the microwave domain, measuring coherence times up to $62~\mu$s and an average qubit quality factor above $10^5$: much closer to state-of-the-art aluminum-junction devices. We find the higher superconducting gap energy also results in reduced quasiparticle sensitivity above $0.16~$K, where aluminum junction performance deteriorates. Our junction process is readily applied to standard optical-based foundry processes, opening new avenues for direct integration and scalability, and paves the way for higher-temperature and higher-frequency quantum devices.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2026

Future foundries: A convergent manufacturing platform

This article introduces the Future Foundries platform developed at Oak Ridge National Laboratory, a first-generation research system designed to demonstrate convergent manufacturing. Convergent manufacturing brings together additive, subtractive, and transformative processes in a digitally interconnected environment to enable end-to-end production workflows. By linking traditionally discrete steps, convergent platforms accelerate production, improve repeatability, and support high-mix, low-volume manufacturing. The Future Foundries platform exemplifies this vision in practice by combining four modular, vendor-agnostic process cells that include robotic WAAM, induction heating, optical metrology, and machining, coordinated through an automated pallet handler and a ROS 2-based digital thread. This architecture provides the flexibility and scalability needed for agile production in small and medium-sized manufacturing enterprises and for field deployable manufacturing. Two case studies illustrate the platform’s capabilities. The first presents an integrated workflow for fabricating, transforming, and repairing critical replacement components, showing how consolidated thermal, additive, inspection, and machining operations reduce manual part handling and streamline process flow. The second case study highlights coordinated multi-part production enabled by automated pallet logistics and multi-cell scheduling. Together, these examples showcase convergent manufacturing as a practical and scalable strategy for strengthening domestic casting and forging capacity, improving supply-chain resilience, and enabling rapid, adaptable production of mission-critical components.

Convergent manufacturing↗
DOE OSTI2026

Identifying Strain Stacking Boundaries between Multiphase Domains in Atomically Thin Two-Dimensional Magnets

Stacking engineering of van der Waals materials is an important strategy to control the materials’ properties, such as electronic correlations, ferroelectricity, and layer-dependent two-dimensional magnetism. A timely testbed for the study of the latter is atomically thin chromium trihalides (CrX 3 , X = Cl, Br, I). Notably, by understanding the sliding mechanism between different stacking sequences, control of the stacking arrangement, and thus magnetic properties in CrX 3 , can be achieved. Such insight, however, is currently lacking. Here, in this study, advanced electron microscopy methods are used to identify multiple stacking sequences corresponding to different bulk phases in atomically thin CrX 3 (X = Cl and Br) down to bilayer thickness and with lateral domain sizes as small as tens of nanometers. Indications of nanometer scale transitions and interactions at the stacking boundaries are found, including a universally preferred sliding direction that is consistent with density functional theory calculations and the strain fields at lateral heterostructure boundaries. This study demonstrates the necessity to consider local stacking structures when interpreting averaged magnetic properties measured with macroscale probes. Additionally, the preferred sliding direction insight from this study provides a strategy to control stacking sequence in atomically thin CrX 3 samples during the exfoliation and sample fabrication process.

DFT calculations↗
DOE OSTI2025

Green Electrode Processing Enabled by Fluoro-Free Multifunctional Binders for Lithium-Ion Batteries

The eco-friendly processing of conjugated polymer binder for lithium-ion batteries demands improved polymer solubility by introducing functional moieties, while this strategy will concurrently sacrifice polymer conductivity. Employing the polyfluorene-based binder poly(2,7-9,9 (di(oxy-2,5,8-trioxadecane))fluorene) (PFO), soluble in water-ethanol mixtures, a novel approach is presented to solve this trade-off, which features integration of aqueous solution processing with subsequent controlled thermal-induced cleavage of solubilizing side chains, to produce hierarchically ordered structures (HOS). The thermal processing can enhance the intermolecular π–π stacking of polyfluorene backbone for better electrochemical performance. Notably, HOS-PFO demonstrated a substantial 6–7 orders of magnitude enhancement in electronic conductivity, showcasing its potential as a functional binder for lithium-ion batteries. As an illustration, HOS-PFO protected SiOx anodes, utilizing in situ side chain decomposition of PFO surrounding SiOx particles after aqueous processing are fabricated. HOS-PFO contributed to the stable cycling and high-capacity retention of practical SiOx anodes (3.0 mAh cm -2 ), without the use of any conducting carbon additives or fluorinated electrolyte additives. It is proposed that this technique represents a universal approach for fabricating electrodes with conjugated polymer binders from aqueous solutions without compromising conductivity.

25 ENERGY STORAGE↗
DOE OSTI2020

Advanced CMOS Reliability Update: Sub 20nm FinFET Assessment

Advances in FinFET design and fabrication enable manufacturing of denser, more compact integrated circuits (ICs) with substantially reduced leakage while shortening the channel-lengths. The same stress-induced leakage and breakdown degradation mechanisms that affect planar transistors also impact FinFET devices. Reliability concerns such as Bias Temperature Instability (BTI), Time Dependent Dielectric Breakdown (TDDB), and Hot Carrier Injection (HCI) become very important with changes to transistor geometry and fin sidewall crystal orientation. Recent testing has shown that FinFETs respond differently to radiation (radiation effects such as total ionizing dose) when compared to planar transistors. These reliability and radiation effects issues become very important when changing transistor geometry and scaling FinFETs towards smaller feature sizes (22-nm, 16-nm, 14- nm, 10-nm, and smaller critical dimensions). The comparable 2019 state of the art transistor densities in current high-volume manufacturing silicon-based foundries is 7-nm (ISMC, Samsung) and 10-nm (Intel) [www.anandtech.com,fuse.wikichip.org]. Released products include supporting components for the cellphone and commercial microprocessor markets respectively. Extensive development in the foundry industry is driving to a 5-nm technology node in late 2020.

47 OTHER INSTRUMENTATION↗
NASA NTRS1993

Radiation hardened microprocessor for small payloads

The RH-3000 program is developing a rad-hard space qualified 32-bit MIPS R-3000 RISC processor under the Naval Research Lab sponsorship. In addition, under IR&D Harris is developing RHC-3000 for embedded control applications where low cost and radiation tolerance are primary concerns. The development program leverages heavily from commercial development of the MIPS R-3000. The commercial R-3000 has a large installed user base and several foundry partners are currently producing a wide variety of R-3000 derivative products. One of the MIPS derivative products, the LR33000 from LSI Logic, was used as the basis for the design of the RH-3000 chipset. The RH-3000 chipset consists of three core chips and two support chips. The core chips include the CPU, which is the R-3000 integer unit and the FPA/MD chip pair, which performs the R-3010 floating point functions. The two support whips contain all the support functions required for fault tolerance support, real-time support, memory management, timers, and other functions. The Harris development effort had first passed silicon success in June, 1992 with the first rad-hard 32-bit RH-3000 CPU chip. The CPU device is 30 kgates, has a 508 mil by 503 mil die size and is fabricated at Harris Semiconductor on the rad-hard CMOS Silicon on Sapphire (SOS) process. The CPU device successfully passed tesing against 600,000 test vectors derived directly on the LSI/MIPS test suite and has been operational as a single board computer running C code for the past year. In addition, the RH-3000 program has developed the methodology for converting commercially developed designs utilizing logic synthesis techniques based on a combination of VHDK and schematic data bases.

Shah, Ravi↗
NASA NTRS1989

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Buehler, M. G.↗
DOE OSTI2023

A New Class of SiC Power MOSFETs with Record-Low Resistance

Silicon carbide (SiC) power transistors are used in the main traction inverter of electric vehicles (EVs). Tesla began installing SiC power MOSFETs in 2017, and has now produced 4.8 million EVs containing over 169 million SiC power MOSFETs. Looking ahead, the worldwide EV market is projected to exceed 50 million vehicles per year by 2030 (Reuters, Oct. 25, 2022). This will create a demand for over two billion SiC power MOSFETs per year. Our program aims to double the efficiency of today's commercial power MOSFETs. This will cut the number of MOSFETs per EV in half, reducing cost, simplifying assembly, decreasing weight, and increasing vehicle reliability through reduced parts count. Our approach is to apply innovative design and advanced processing to increase the density of current-controlling channels in SiC power MOSFET. We have developed two new MOSFET devices, each of which increases the channel density by a factor of six over today's best commercial MOSFETs. This required implementing new fabrication processes, creating new device designs, and integrating the processing steps and device designs into a manufacturable technology. In this project we have developed two innovative devices: (i) a novel three-dimensional structure, the "tri-gate MOSFET," and (ii) a deeply-scaled, fully self-aligned trench MOSFET, the "IMOSFET". Both products were experimentally demonstrated during this project and meet the program goals of increased efficiency relative to the current state-of-the art commercial products. In the process we have generated significant IP, with two US patents issued and three applications pending. We have also published three journal articles and given reports on this technology at seven international conferences. The success of this program has led to significant follow-on funding from industry. In May 2023 Purdue University signed a five-year R&D contract with GlobalFoundries to transfer our novel technology to commercial production. With headquarters in Malta, NY, Global Foundries is one of the largest pure-play silicon foundries in the world, with annual revenue of $\$$8.1B. Their SiC foundry will be built around the next-generation 200-mm diameter SiC wafers, which will double the number of die per wafer and reduce per-die production cost.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2024

Tantalum pentoxide: a new material platform for high-performance dielectric metasurface optics in the ultraviolet and visible region

Dielectric metasurfaces, composed of planar arrays of subwavelength dielectric structures that collectively mimic the operation of conventional bulk optical elements, have revolutionized the field of optics by their potential in constructing high-efficiency and multi-functional optoelectronic systems on chip. The performance of a dielectric metasurface is largely determined by its constituent material, which is highly desired to have a high refractive index, low optical loss and wide bandgap, and at the same time, be fabrication friendly. Here, we present a new material platform based on tantalum pentoxide (Ta 2 O 5 ) for implementing high-performance dielectric metasurface optics over the ultraviolet and visible spectral region. This wide-bandgap dielectric, exhibiting a high refractive index exceeding 2.1 and negligible extinction coefficient across a broad spectrum, can be easily deposited over large areas with good quality using straightforward physical vapor deposition, and patterned into high-aspect-ratio subwavelength nanostructures through commonly-available fluorine-gas-based reactive ion etching. We implement a series of high-efficiency ultraviolet and visible metasurfaces with representative light-field modulation functionalities including polarization-independent high-numerical-aperture lensing, spin-selective hologram projection, and vivid structural color generation, and the devices exhibit operational efficiencies up to 80%. Our work overcomes limitations faced by scalability of commonly-employed metasurface dielectrics and their operation into the visible and ultraviolet spectral range, and provides a novel route towards realization of high-performance, robust and foundry-manufacturable metasurface optics.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Room-temperature valley-selective emission in Si-MoSe 2 heterostructures enabled by high-quality-factor chiroptical cavities

Transition metal dichalcogenides possess valley pseudospin, enabling coupling between photon spin and electron spin for classical and quantum information processing. However, rapid valley-dephasing processes have impeded the development of scalable, high-performance valleytronic devices operating at room temperature. Here we demonstrate that a chiral resonant metasurface can enable room-temperature valley-selective emission in MoSe 2 monolayers independent of excitation polarization. This platform provides circular eigen-polarization states with a high quality factor (Q-factor) and strong chiral near-field enhancement. The fabricated Si chiral metasurfaces exhibit chiroptical resonances with Q-factors up to 450 at visible wavelengths. We reveal degrees of circular polarization (DOP) reaching a record high of 0.5 at room temperature. Our measurements show that the high DOP can be attributed to the significantly increased chiroptical local density of states, which enhances valley-specific radiative transition rates by a factor of ~13. Our work could facilitate the development of ultracompact chiral classical and quantum light sources.

42 ENGINEERING↗
DOE OSTI2024

Electrochemical lithium extraction from hectorite ore

Electrochemical technologies add a unique dimension for ore refinement, representing tunable methods that can integrate with renewable energy sources and existing downstream process flows. However, the development of electrochemical extraction technologies has been impeded by the technological maturity of hydro- and pyro-metallurgy, as well as the electrical insulating properties of many metal oxide ores. The fabrication and use of carbon/insulating material composite electrodes has been a longstanding method to enable electrochemical activation. Here, using real hectorite ore, we employ this technical approach to fabricate hectorite-carbon black composite electrodes (HCCEs) and achieve electrochemical activation of hectorite. Anodic polarization results in lithium-ion release through a multi-step chemical and electrochemical mechanism that results in 50.7 ± 4.4% removal of lithium from HCCE, alongside other alkaline ions. This technical proof-of-concept study underscores that electrochemical activation of ores can facilitate lattice deterioration and ion removal from ores.

25 ENERGY STORAGE↗
DOE OSTI2025

Directed self-assembly of block copolymers for high-precision patterning in the era of extreme ultraviolet lithography

Extreme ultraviolet (EUV) lithography enables unprecedented resolution in semiconductor patterning but faces critical challenges in developing resist materials that achieve high-precision at economically viable throughput. Directed self-assembly (DSA) of block copolymers (BCPs) offers a promising solution for pattern rectification by leveraging thermodynamically determined domain structures to decouple BCP pattern quality from the imperfect original lithographic pattern. This prospective presents an overview of recent progress on the EUV + DSA strategy, covering advances in BCP material design, processing, metrology, and pattern transfer. We highlight recent advances in high-χ BCPs with perpendicular orientation and domain spacings compatible with EUV dimensions, leveraging A-b-(B-r-C) architectures. We also discuss progress in chemical pre-pattern fabrication using both positive- and negative tone resists, along with processing strategies to minimize defects and roughness based on BCP thermodynamics and assembly kinetics. We further examine metrology platforms for characterizing the thermodynamics of BCP materials and quantifying the size and shape of BCP domains. Lastly, we review pattern transfer strategies for generating functional inorganic masks suitable for semiconductor manufacturing. Together, these advances highlight the potential of DSA to complement EUV lithography, offering a pathway to address critical challenges in achieving high-precision patterning for the semiconductor industry.

Lee, Kyunghyeon [Univ. of Chicago, IL (United Stat↗
DOE OSTI2023

Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform

Two-dimensional (2D) materials are promising candidates for future electronics due to their excellent electrical and photonic properties. Although promising results on the wafer-scale synthesis (≤150 mm diameter) of monolayer molybdenum disulfide (MoS 2 ) have already been reported, the high-quality synthesis of 2D materials on wafers of 200 mm or larger, which are typically used in commercial silicon foundries, remains difficult. The back-end-of-line (BEOL) integration of directly grown 2D materials on silicon complementary metal–oxide–semiconductor (CMOS) circuits is also unavailable due to the high thermal budget required, which far exceeds the limits of silicon BEOL integration (<400 °C). This high temperature forces the use of challenging transfer processes, which tend to introduce defects and contamination to both the 2D materials and the BEOL circuits. Here we report a low-thermal-budget synthesis method (growth temperature < 300 °C, growth time ≤ 60 min) for monolayer MoS 2 films, which enables the 2D material to be synthesized at a temperature below the precursor decomposition temperature and grown directly on silicon CMOS circuits without requiring any transfer process. We designed a metal–organic chemical vapour deposition reactor to separate the low-temperature growth region from the high-temperature chalcogenide-precursor-decomposition region. We obtain monolayer MoS 2 with electrical uniformity on 200 mm wafers, as well as a high material quality with an electron mobility of ~35.9 cm 2 V -1 s -1 . Finally, we demonstrate a silicon-CMOS-compatible BEOL fabrication process flow for MoS 2 transistors; the performance of these silicon devices shows negligible degradation (current variation < 0.5%, threshold voltage shift < 20 mV). We believe that this is an important step towards monolithic 3D integration for future electronics.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2026

Patterned, Low-Temperature Growth of Transition Metal Dichalcogenides for Low Resistance Raised Contacts

Transition metal dichalcogenide (TMD) monolayers are promising channel materials for next-generation electronic devices. A challenge is the high contact resistance between monolayer TMDs and metal contacts, especially for holes. Here, in this regard, raised source/drain contacts are promising. However, the direct, patterned growth of raised contacts at CMOS-compatible temperatures remains largely unresolved. We present plasma-free selenization and sulfurization of metal oxides at substrate temperatures down to 400 °C, compatible with back-end-of-line thermal budgets. To achieve growth at such temperatures, gas-phase chalcogen precursors are first thermally activated at 950 °C. Films grown on single-crystal monolayer TMDs exhibit high crystal quality, as confirmed by transmission electron microscopy. Raised contacts on WSe 2 monolayers fabricated using this approach yield a low hole contact resistance of 0.3 kΩ·μm after chemical doping. This process is shown to be applicable to growing various TMDs, including WS 2 , MoSe 2 , MoS 2 , PtSe 2 , and NbS 2 .

contact engineering↗
DOE OSTI2026

Balancing moisture and oxygen can match the crystallization dynamics of inert halide perovskite processing

Understanding crystallization in ambient environments is essential for scaling the fabrication of halide perovskite solar cells. Antisolvent-free perovskite deposition offers improved compatibility with high-throughput processing but introduces distinct crystallization dynamics relative to the more ubiquitous use of antisolvents in lab-scale perovskite fabrication. These dynamics are driven by interactions between solutes, solvent and the deposition environment. Using in situ wide-angle X-ray scattering during spin-coating and annealing, we demonstrate how relative humidity (RH) and oxygen, can be tuned to drive polytype evolution during ambient crystallization of formamidinium lead iodide to match that of inert synthesis and achieve comparable film and device quality. In an inert (N 2 ) environment, we find that perovskite films follow a well-established 2H → 3C phase transformation with a short period of coexistence of the 4H and 6H phase during heating. During crystallization in dry air (RH 0%), the added presence of oxygen leads to the dominance of 4H intermediate for an extended duration, establishing a 2H → 4H → 3C pathway. Introducing low humidity (RH 10%) suppresses the 4H phase to a short-lived intermediate above 100 °C, facilitating a more direct transition to the desired 3C phase and almost replicating the crystallization behavior observed under inert conditions. Interestingly, films crystallized under RH 10% show a lower onset temperature for the perovskite 3C phase than under N 2 . At higher humidity (RH 40%), the strong interaction of oxygen and moisture with iodoplumbates appears to stabilize higher order polytypes (4H and 6H). Devices fabricated under RH 10% achieve higher efficiency and enhanced stability compared to those produced under inert atmosphere. These findings provide mechanistic insight into crystallization pathways in different environments and provide a framework to transfer processes from inert to ambient conditions. The results highlight the critical role of controlled humidity in tuning antisolvent-free perovskite crystallization for scalable processing.

Hossain, Maimur [Univ. of California, San Diego, C↗
DOE OSTI2025

Sub-10 nm upconversion nanocrystals for long-term single-particle tracking

Lanthanide-doped upconversion nanoparticles are attractive single-molecule imaging probes due to their high photostability and anti-Stokes luminescence. However, achieving both small particle size and strong brightness has remained a major challenge, as reducing size often leads to dimmer emission. Herein, we fabricate a sub-10 nm cascade actively protected upconversion nanoparticles, which shows a 33-fold enhanced upconversion efficiency at the single-particle level compared to larger ~19 nm conventional nanoparticles. Theoretical modeling and time-resolved measurements show that emission loss mainly comes from energy leakage of Er 3+ ions to surface defects. By introducing a NaYbF 4 layer as photon-harvesting and protective intermediate layer, we minimize this energy loss and significantly boost brightness. A monolayer of inert NaLuF 4 can effectively suppress the surface quenching to Yb 3+ . Using these ultra-small bright probes, we successfully tracked single epidermal growth factor receptor molecules on live cells for up to one hour, revealing dynamic switching between different diffusion modes.

Qiu, Xiaochen [Fudan Univ., Shanghai (China); Shen↗