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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS2002

An Embedded Reconfigurable Logic Module

A Miniature Embedded Reconfigurable Computer and Logic (MERCAL) module has been developed and verified. MERCAL was designed to be a general-purpose, universal module that that can provide significant hardware and software resources to meet the requirements of many of today's complex embedded applications. This is accomplished in the MERCAL module by combining a sub credit card size PC in a DIMM form factor with a XILINX Spartan I1 FPGA. The PC has the ability to download program files to the FPGA to configure it for different hardware functions and to transfer data to and from the FPGA via the PC's ISA bus during run time. The MERCAL module combines, in a compact package, the computational power of a 133 MHz PC with up to 150,000 gate equivalents of digital logic that can be reconfigured by software. The general architecture and functionality of the MERCAL hardware and system software are described.

Tucker, Jerry H.↗
DOE OSTI2022

Modeling Analog Tile-Based Accelerators Using SST

Analog computing has been widely proposed to improve the energy efficiency of multiple important workloads including neural network operations, and other linear algebra kernels. To properly evaluate analog computing and explore more complex workloads such as systems consisting of multiple analog data paths, system level simulations are required. Moreover, prior work on system architectures for analog computing often rely on custom simulators creating signficant additional design effort and complicating comparisons between different systems. To remedy these issues, this report describes the design and implementation of a flexible tile-based analog accelerator element for the Structural Simulation Toolkit (SST). The element focuses on heavily on the tile controller—an often neglected aspect of prior work—that is sufficiently versatile to simulate a wide range of different tile operations including neural network layers, signal processing kernels, and generic linear algebra operations without major constraints. The tile model also interoperates with existing SST memory and network models to reduce the overall development load and enable future simulation of heterogeneous systems with both conventional digital logic and analog compute tiles. Finally, both the tile and array models are designed to easily support future extensions as new analog operations and applications that can benefit from analog computing are developed.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Demonstration of Model-Based Design for Digital Controller Using Formal Methods

This report describes work originally performed in FY19 that assembled a workflow enabling formal verification of high-consequence digital controllers. The approach builds on an engineering analysis strategy using multiple abstraction levels (Model-Based Design) and performs exhaustive formal analysis of appropriate levels – here, state machines and C code – to assure always/never properties of digital logic that cannot be verified by testing alone. The operation of the workflow is illustrated using example models and code, including expected failures of verification when properties are violated.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Hardware Fuzzing with An Emulator

Bugs in digital logic have led to some significant security vulnerabilities. Hardware bugs are particularly troublesome since they cannot be easily patched. Additionally, if the bug is in the root of trust, all trust built upon it can be vulnerable. Traditional testing either require a deep knowledge of the system, creative attack vectors and lots of human interaction. This is not scalable as there are very few engineers that can wear the hat of a designer, a verification engineer, and a cybersecurity expert. Hardware fuzzing is a relatively new research area in dynamic hardware testing. It has proven to be an effective method for discovering bugs, unexpected behaviors, and security vulnerabilities in software. While hardware fuzzing is new to the hardware domain, it has a strong track record in software testing. Fuzzing is a testing technique that randomly mutates the input data to uncover bugs or vulnerabilities in the design. It is especially good at finding corner cases that test engineers can not envision. Another advantage over other dynamic testing techniques is that, if done well, deep knowledge of the design is not required. Additionally, fuzzing scales well. If the system is set up correctly, it can run unsupervised for weeks if necessary. In this work, we propose using hardware fuzzing to improve the input vector generation for an information flow tracking tool. To get reasonable throughput of test vectors, an emulator is targeted as the execution platform. Efficient emulator execution has some specific requirements.

42 ENGINEERING↗
DOE OSTI2026

Digital Silicon Photomultiplier Chip Testing

Silicon Photomultipliers (SiPMs) are highly sensitive photodetectors. Traditional analog SiPMs require complex external readout electronics. Digital SiPMs (dSiPMs) include digital readout circuitry directly on-chip, offering superior timing resolution, reduced power consumption and compact size, pixel-level masking for active noise reduction. The primary objectives of this study are to, verify digital logic integrity of the shift registers used for controlling the pixel masking circuit, and determine the dark count rate of individual pixels as a function of bias voltage and clock frequency. I observe and explain behavior of the shift register and counting circuit.

Graham, Bennett [U. Chicago (main)]↗
NASA NTRS1966

New television camera eliminates vidicon tube

Small, lightweight camera systems use solid state imaging devices in the form of phototransistor mosaic sensors instead of vidicon tubes for light sensing and image conversion. The digital logic circuits scan the sensor mosaic at 60 frames per second to produce pictures composed of a series of dots rather than lines.

Source record↗
NASA NTRS1966

Digital system provides superregulation of nanosecond amplifier-discriminator circuit

Feedback system employing a digital logic comparator to detect and correct amplifier drift provides stable gain characteristics for nanosecond amplifiers used in counting applications. Additional anticoincidence logic enables application of the regulation circuit to the amplifier and discriminator while they are mounted in an operable circuit.

Forges, K. G.↗
NASA NTRS1967

Multiplexer uses insulated gate-field effect transistors

Small lightweight multiplexer incorporates IG-FETs /Insulated Gate-Field Effect Transistors/ for all digital logic functions, including the internally generated 3.6-kHz clock. It consists of 30 primary channels, each of which is sampled 120 times per second.

Gussow, S. S.↗
NASA NTRS1969

Short circuit protection for a power distribution system

Sensing circuit detects when the output from a matrix is present and when it should be present. The circuit provides short circuit protection for a power distribution system where the selection of the driven load is accomplished by digital logic.

Owen, J. R., III↗
NASA NTRS1970

Burst synchronization detection system

System uses digital logic and a voltage-controlled oscillator to obtain appropriate horizontal and vertical sync signals from the sync bursts contained in the original transmitted signal. It is useful in systems that exhibit considerable single amplitude fluctuation.

Lipoma, P. C.↗
NASA NTRS1971

Television multiplexing system

System with single, standard, wideband line transmits ten or more real time TV video data displays over hard wire to recorders more than 22.5 km from source. Digital logic and integrated circuits ensure high reliability and low maintenance. System is adaptable for video sampling applications.

Simpkins, L. G.↗
NASA NTRS1973

Omni-axis secondary injection thrust vector control system

The concept, development, design study and preliminary analysis and layout of the required digital logic scheme to be used for injection valve control are presented. An application and optimization study of an Omni-Axis Secondary Injection Control System applicable to the proposed Space Shuttle Pressure Fed Engine is reported. Technical definition and analysis control procedures and test routines, as well as a supporting set of drawing sketches and reference manual, are enclosed.

Kirkley, D. J.↗
NASA NTRS1972

Miniature biotelemeter giving 10 channels of wideband biomedical data.

A miniature biotelemeter has been developed for sensing and transmitting multiple channels of wideband biomedical data over a radio link. Its small size and weight make it capable of being carried by free-moving laboratory animals as small as rats. Ten data channels each of 5-kHz data bandwidth are provided to permit monitoring of a wide variety of physiological signals. Multichannel telemetry of electroencephalograms, electrocardiograms, electromyograms, state functions, and dynamic processes such as blood flow and body chemistry are possible applications. Utilization of newly available monolithic chip components, low-power COS/MOS MSI digital logic, and state-of-the-art hybrid mounting techniques makes this novel device useful for both research and clinical bioinstrumentation.

Carraway, J.↗
NASA NTRS1973

Operational earth resources data handling system for the 1980's

Results of a recent study of data handling requirements for future operational earth observation systems are reported. Such systems in the 1980's may have 10-20 meter resolution and generate .2 tecabits of data per day, with peak rates of 0.8 gigabits per second based on the dominant requirements of agriculture. System alternatives are considered that will handle such data. Data relayed to the facility are recorded at high rates and then processed at lower speed by computer. Hardwired special digital logic computers may be used with an appropriate classification algorithm for crop recognition. Optical mass memories now in the prototype stage will handle the 10 tecabits and 800 megabit per second read-in rate required.

Van Vleck, E. M.↗