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At least 73 records · Page 4

Laser drilling of vias in dielectric for high density multilayer LSHI thick film circuits

A design analysis of a high density multilevel thick film digital microcircuit used for large scale integration is presented. The circuit employs 4 mil lines, 4 mil spaces and requires 4 mil diameter vias. Present screened and fired thick film technology is limited on a production basis to 16 mil square vias. A process whereby 4 mil diameter vias can be fabricated in production using laser technology was described along with a process to produce 4 mil diameter vias for conductor patterns which have 4 mil lines and 4 mil spacings.

Cocca, T.↗

Statistical circuit design for yield improvement in CMOS circuits

This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

Kamath, H. J.↗

Circuit design tool. User's manual, revision 2

The CAM chip design was produced in a UNIX software environment using a design tool that supports definition of digital electronic modules, composition of these modules into higher level circuits, and event-driven simulation of these circuits. Our design tool provides an interface whose goals include straightforward but flexible primitive module definition and circuit composition, efficient simulation, and a debugging environment that facilitates design verification and alteration. The tool provides a set of primitive modules which can be composed into higher level circuits. Each module is a C-language subroutine that uses a set of interface protocols understood by the design tool. Primitives can be altered simply by recoding their C-code image; in addition new primitives can be added allowing higher level circuits to be described in C-code rather than as a composition of primitive modules--this feature can greatly enhance the speed of simulation.

Miyake, Keith M.↗

MMIC linear-phase and digital modulators for deep space spacecraft X-band transponder applications

The design concepts, analyses, and development of GaAs monolithic microwave integrated circuit (MMIC) linear-phase and digital modulators for the next generation of space-borne communications systems are summarized. The design approach uses a compact lumped element quadrature hybrid and Metal Semiconductor Field Effect Transistors (MESFET)-varactors to provide low loss and well-controlled phase performance for deep space transponder (DST) applications. The measured results of the MESFET-diode show a capacitance range of 2:1 under reverse bias, and a Q of 38 at 10 GHz. Three cascaded sections of hybrid-coupled reflection phase shifters were modeled and simulations performed to provide an X-band (8415 +/- 50 MHz) DST phase modulator with +/- 2.5 radians of peak phase deviation. The modulator will accommodate downlink signal modulation with composite telemetry and ranging data, with a deviation linearity tolerance of +/- 8 percent and insertion loss of less than 8 +/- 0.5 dB. The MMIC digital modulator is designed to provide greater than 10 Mb/s of bi-phase modulation at X-band.

Mysoor, Narayan R.↗

Two-way digital driver/receiver uses one set of lines

Two-way /bilateral/ digital driver/receiver system using MOS circuits was designed for a multiprocess computer having several subsystems at relatively close locations. The system requires only a single set of communication lines between subsystems, thus achieving lower cost with increased reliability.

Burnett, G. J.↗

An Integrated Circuit for Radio Astronomy Correlators Supporting Large Arrays of Antennas

Radio telescopes that employ arrays of many antennas are in operation, and ever larger ones are being designed and proposed. Signals from the antennas are combined by cross-correlation. While the cost of most components of the telescope is proportional to the number of antennas N, the cost and power consumption of cross-correlationare proportional to N2 and dominate at sufficiently large N. Here we report the design of an integrated circuit (IC) that performs digital cross-correlations for arbitrarily many antennas in a power-efficient way. It uses an intrinsically low-power architecture in which the movement of data between devices is minimized. In a large system, each IC performs correlations for all pairs of antennas but for a portion of the telescope's bandwidth (the so-called "FX" structure). In our design, the correlations are performed in an array of 4096 complex multiply-accumulate (CMAC) units. This is sufficient to perform all correlations in parallel for 64 signals (N=32 antennas with 2 opposite-polarization signals per antenna). When N is larger, the input data are buffered in an on-chipmemory and the CMACs are re-used as many times as needed to compute all correlations. The design has been synthesized and simulated so as to obtain accurate estimates of the IC's size and power consumption. It isintended for fabrication in a 32 nm silicon-on-insulator process, where it will require less than 12mm2 of silicon area and achieve an energy efficiency of 1.76 to 3.3 pJ per CMAC operation, depending on the number of antennas. Operation has been analyzed in detail up to N = 4096. The system-level energy efficiency, including board-levelI/O, power supplies, and controls, is expected to be 5 to 7 pJ per CMAC operation. Existing correlators for the JVLA (N = 32) and ALMA (N = 64) telescopes achieve about 5000 pJ and 1000 pJ respectively usingapplication-specific ICs in older technologies. To our knowledge, the largest-N existing correlator is LEDA atN = 256; it uses GPUs built in 28 nm technology and achieves about 1000 pJ. Correlators being designed for the SKA telescopes (N = 128 and N = 512) using FPGAs in 16nm technology are predicted to achieve about 100 pJ.

ASIC↗

Fundamental Hardware Design in PVS

The development of Programmable Logic Devices (PLDs) has introduced programming as a primary tool in the development of digital circuits. This work attempts to create a generic verification environment in which designs can be specified and verified using the Prototype Verification System (PVS). This is accomplished by providing library support for general hardware constructs. The environment is intended for use with any PLD and any PLD programming language. The goal of the environment is to allow the easy translation of digital designs to PVS and provide sufficient support to make verification possible without a great deal of effort.

Leathrum, James F., Jr.↗

VLBI System (BLK I) If-video down Conversion Design

The prototype intermediate frequency video down converter of the Deep Space Network (BLK 1) Very Long Base Interferometry system, a hybrid of analog and digital circuits, was completed and tested. The initial results met all design specifications, establishing a milestone in new design technology for such devices. This device has uses in other similar applications and can form the basis for expanded design and applications.

Ham, N. C.↗

A high-accuracy digital star tracker for advanced planetary missions.

The digital star tracker represents a novel departure from previous analog designs in terms of circuit implementation and operational capabilities. As an element of an all-digital spacecraft control system, it combines proven low-level analog signal processing with digital error control and command functions. Additional capabilities that are obtainable with the digital circuitry include programmable intensity threshold gates, commanded electronic pointing control, and an acquisition/control algorithm which minimizes the effects of straylight disturbances. The capabilities inherent in the implementation have been successfully demonstrated in a laboratory model of the instrument.

Salomon, P. M.↗

A high-accuracy digital star tracker for advanced planetary missions

The digital star tracker represents a novel departure from previous analog designs in terms of circuit implementation and operational capabilities. As an element of an all-digital spacecraft control system, it combines proven low-level analog signal processing with digital error control and command functions. Additional capabilities that are obtainable with the digital circuitry include programmable intensity threshold gates, commanded electronic pointing control, and an acquisition/control algorithm which minimizes the effects of straylight disturbances. The capabilities inherent in the implementation have been successfully demonstrated in a laboratory model of the instrument.

Salomon, P. M.↗

Integrated low power digital gyro control electronics

Embodiments of the invention generally encompass a digital, application specific integrated circuit (ASIC) has been designed to perform excitation of a selected mode within a vibratory rate gyroscope, damping, or force-rebalance, of other modes within the sensor, and signal demodulation of the in-phase and quadrature components of the signal containing the angular rate information. The ASIC filters dedicated to each channel may be individually programmed to accommodate different rate sensor designs/technology or variations within the same class of sensors. The ASIC architecture employs a low-power design, making the ASIC, particularly suitable for use in power-sensitive applications.

M'Closkey, Robert↗

Continuous-Integration Laser Energy Lidar Monitor

This circuit design implements an integrator intended to allow digitization of the energy output of a pulsed laser, or the energy of a received pulse of laser light. It integrates the output of a detector upon which the laser light is incident. The integration is performed constantly, either by means of an active integrator, or by passive components.

Karsh, Jeremy↗

Digital Pulse-Width-Modulation Circuit

Digital pulse-width-modulation circuit provides programmable duration from 1 microsecond to full on, at repetition rate of 1 kHz. Designed for use in controlling CO2 laser, also used in applications in which precision and flexibility of digital control of pulse durations needed. Circuit incorporates low-power Schottky transistor/transistor-logic (TTL) devices in critical high-speed parts. Designed in TTL to make it compatible with Pro-Log 7914 (or equivalent) decoder input/output (I/O) utility printed-circuit card.

Wenzler, Carl J.↗

Radiation-Hard Parallel Readout Circuit for Low-Frequency Voltage Signal Measurements

NASA Goddard Space Flight Center (GSFC) has successfully developed and tested a custom-designed low-noise multi-channel digitizer (MCD) application specific integrated circuit (ASIC) for operation in harsh radiation environments. The MCD-ASIC is optimized for low-frequency and low-voltage signal measurements from sensors and transducers. It has 20 input channels where each channel is comprised of auto-zeroed chopper variable-gain amplifier, post amplifier, and a second order ∑∆ modulator. ∑∆ analog-to-digital converter (ADC) relies on oversampling and noise shaping to achieve high-resolution conversion. However, the MCD-ASIC requires digital filtering and decimation to convert the output single bit streams from the ADC to useful data words. A parallel digital platform such as a field-programmable-gate-array (FPGA) is highly suitable to fully leverage the capabilities of the MCD-ASIC. The FPGA controls the MCD-ASIC via serial peripheral interface (SPI) protocol and acquires data from it. A Python-script communicates with the FPGA board through a USB interface on a cross operating platform. Using this architecture, the system is capable of monitoring up to 20 voltage readout channels simultaneously in a real-time manner. Each channel’s parameters can be programmed independently allowing maximum user versatility. In this paper, we present analysis of the analog front-end, the implementation of the digital processing unit on the FPGA, and provide noise performance results from the MCD-ASIC readout.

ASIC↗

Advanced digital SAR processing study

A highly programmable, land based, real time synthetic aperture radar (SAR) processor requiring a processed pixel rate of 2.75 MHz or more in a four look system was designed. Variations in range and azimuth compression, number of looks, range swath, range migration and SR mode were specified. Alternative range and azimuth processing algorithms were examined in conjunction with projected integrated circuit, digital architecture, and software technologies. The advaced digital SAR processor (ADSP) employs an FFT convolver algorithm for both range and azimuth processing in a parallel architecture configuration. Algorithm performace comparisons, design system design, implementation tradeoffs and the results of a supporting survey of integrated circuit and digital architecture technologies are reported. Cost tradeoffs and projections with alternate implementation plans are presented.

Martinson, L. W.↗

Advanced transducers Final report

Design of digital adapter with limit storage for transducers for use in multichannel digital data acquisition system

INTEGRATED CIRCUIT↗