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At least 73 records · Page 4

Engineering Tunneling Selector to Achieve High Non-linearity for 1S1R Integration

Memristor devices have been extensively studied as one of the most promising technologies for next-generation non-volatile memory. However, for the memristor devices to have a real technological impact, they must be densely packed in a large crossbar array (CBA) exceeding Gigabytes in size. Devising a selector device that is CMOS compatible, 3D stackable, and has a high non-linearity (NL) and great endurance is a crucial enabling ingredient to reach this goal. Tunneling based selectors are very promising in these aspects, but the mediocre NL value limits their applications in large passive crossbar arrays. In this work, we demonstrated a trilayer tunneling selector based on the Ge/Pt/TaN 1+x /Ta 2 O 5 /TaN 1+x /Pd layers that could achieve a NL of 3 × 10 5 , which is the highest NL achieved using a tunnel selector so far. The record-high tunneling NL is partially attributed to the bottom electrode's ultra-smoothness (BE) induced by a Ge/Pt layer. We further demonstrated the feasibility of 1S1R (1-selector 1-resistor) integration by vertically integrating a Pd/Ta 2 O 5 /Ru based memristor on top of the proposed selector.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

Energy-efficient Mott activation neuron for full-hardware implementation of neural networks

To circumvent the von Neumann bottleneck, substantial progress has been made towards in-memory computing with synaptic devices. However, compact nanodevices implementing non-linear activation functions are required for efficient full-hardware implementation of deep neural networks. Here, in this work, we present an energy-efficient and compact Mott activation neuron based on vanadium dioxide and its successful integration with a conductive bridge random access memory (CBRAM) crossbar array in hardware. The Mott activation neuron implements the rectified linear unit function in the analogue domain. The neuron devices consume substantially less energy and occupy two orders of magnitude smaller area than those of analogue complementary metal–oxide semiconductor implementations. The LeNet-5 network with Mott activation neurons achieves 98.38% accuracy on the MNIST dataset, close to the ideal software accuracy. We perform large-scale image edge detection using the Mott activation neurons integrated with a CBRAM crossbar array. Our findings provide a solution towards large-scale, highly parallel and energy-efficient in-memory computing systems for neural networks.

electrical and electronic engineering↗

Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads

Abstract This study discusses the feasibility of Ferroelectric Capacitors (FeCaps) and Ferroelectric Field-Effect Transistors (FeFETs) as In-Memory Computing (IMC) elements to accelerate machine learning (ML) workloads. We conducted an exploration of device fabrication and proposed system-algorithm co-design to boost performance. A novel FeCap device, incorporating an interfacial layer (IL) and$$\text {Hf}_{0.5}\text {Zr}_{0.5}\text {O}_2$$ Hf 0.5 Zr 0.5 O 2 (HZO), ensures a reduction in operating voltage and enhances HZO scaling while being compatible with CMOS circuits. The IL also enriches ferroelectricity and retention properties. When integrated into crossbar arrays, FeCaps and FeFETs demonstrate their effectiveness as IMC components, eliminating sneak paths and enabling selector-less operation, leading to notable improvements in energy efficiency and area utilization. However, it is worth noting that limited capacitance ratios in FeCaps introduced errors in multiply-and-accumulate (MAC) computations. The proposed co-design approach helps in mitigating these errors and achieves high accuracy in classifying the CIFAR-10 dataset, elevating it from a baseline of 10% to 81.7%. FeFETs in crossbars, with a higher on-off ratio, outperform FeCaps, and our proposed charge-based sensing scheme achieved at least an order of magnitude reduction in power consumption, compared to prevalent current-based methods.

Science & Technology - Other Topics↗

Skyrmion creation and annihilation by spin waves

Single skyrmion creation and annihilation by spin waves in a crossbar geometry are theoretically analyzed. A critical spin-wave frequency is required both for the creation and the annihilation of a skyrmion. The minimum frequencies for creation and annihilation are similar, but the optimum frequency for creation is below the critical frequency for skyrmion annihilation. If a skyrmion already exists in the cross bar region, a spin wave below the critical frequency causes the skyrmion to circulate within the central region. A heat assisted creation process reduces the spin-wave frequency and amplitude required for creating a skyrmion. Finally, the effective field resulting from the Dzyaloshinskii-Moriya interaction and the emergent field of the skyrmion acting on the spin wave drive the creation and annihilation processes.

36 MATERIALS SCIENCE↗

An accurate locally active memristor model for S-type negative differential resistance in NbO{sub x}

A number of important commercial applications would benefit from the introduction of easily manufactured devices that exhibit current-controlled, or “S-type,” negative differential resistance (NDR). A leading example is emerging non-volatile memory based on crossbar array architectures. Due to the inherently linear current vs. voltage characteristics of candidate non-volatile memristor memory elements, individual memory cells in these crossbar arrays can be addressed only if a highly non-linear circuit element, termed a “selector,” is incorporated in the cell. Selectors based on a layer of niobium oxide sandwiched between two electrodes have been investigated by a number of groups because the NDR they exhibit provides a promisingly large non-linearity. We have developed a highly accurate compact dynamical model for their electrical conduction that shows that the NDR in these devices results from a thermal feedback mechanism. A series of electrothermal measurements and numerical simulations corroborate this model. These results reveal that the leakage currents can be minimized by thermally isolating the selector or by incorporating materials with larger activation energies for electron motion.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

On the origin of resistive switching volatility in Ni/TiO{sub 2}/Ni stacks

Resistive switching and resistive random access memories have attracted huge interest for next generation nonvolatile memory applications, also thought to be able to overcome flash memories limitations when arranged in crossbar arrays. A cornerstone of their potential success is that the toggling between two distinct resistance states, usually a High Resistive State (HRS) and a Low Resistive State (LRS), is an intrinsic non-volatile phenomenon with the two states being thermodynamically stable. TiO{sub 2} is one of the most common materials known to support non-volatile RS. In this paper, we report a volatile resistive switching in a titanium dioxide thin film sandwiched by two nickel electrodes. The aim of this work is to understand the underlying physical mechanism that triggers the volatile effect, which is ascribed to the presence of a NiO layer at the bottom interface. The NiO layer alters the equilibrium between electric field driven filament formation and thermal enhanced ion diffusion, resulting in the volatile behaviour. Although the volatility is not ideal for non-volatile memory applications, it shows merit for access devices in crossbar arrays due to its high LRS/HRS ratio, which are also briefly discussed.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

Memristive linear algebra

The advent of memristive devices offers a promising avenue for efficient and scalable analog computing, particularly for linear algebra operations essential in various scientific and engineering applications. This paper investigates the potential of memristive crossbars in implementing matrix inversion algorithms. We explore both static and dynamic approaches, emphasizing the advantages of analog and in-memory computing for matrix operations beyond multiplication. In particular, we demonstrate that the electrical properties of memristive crossbars uniquely suit them for the evolution of a family of matrix exponentials, which can be exploited for the efficient computation of matrix inverses and online solutions for linear problems. Our results demonstrate that memristive arrays can reduce computational complexity. We also study power consumption and show a tradeoff between precision and energy. Furthermore, we address the challenges of device variability, precision, and scalability, providing insights into the practical implementation of these algorithms.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing

Neuromorphic computers could overcome efficiency bottlenecks inherent to conventional computing through parallel programming and readout of artificial neural network weights in a crossbar memory array. However, selective and linear weight updates and <10-nanoampere read currents are required for learning that surpasses conventional computing efficiency. We introduce an ionic floating-gate memory array based on a polymer redox transistor connected to a conductive-bridge memory (CBM). Selective and linear programming of a redox transistor array is executed in parallel by overcoming the bridging threshold voltage of the CBMs. Synaptic weight readout with currents <10 nanoamperes is achieved by diluting the conductive polymer with an insulator to decrease the conductance. The redox transistors endure >1 billion write-read operations and support >1-megahertz write-read frequencies.

bio-inspired, energy storage (including batteries ↗

Sparse Data Acquisition on Emerging Memory Architectures

Emerging memory devices, such as resistive crossbars, have the capacity to store large amounts of data in a single array. Acquiring the data stored in large-capacity crossbars in a sequential fashion can become a bottleneck. We present practical methods, based on sparse sampling, to quickly acquire sparse data stored on emerging memory devices that support the basic summation kernel, reducing the acquisition time from linear to sub-linear. Experimental results show that at least an order of magnitude improvement in acquisition time can be achieved when the data is sparse.

97 MATHEMATICS AND COMPUTING↗

Spatial distribution of energetic particles in the distant magnetotail

The spatial distribution of energetic particles in the distant magnetotail is analyzed by using identical sets of two complementary energetic particle experiments aboard the IMP 7 and 8 spacecraft. It is noted that the combined IMP 7 and 8 data set provides nearly 10 years of satellite observation. The quantitative distributions of energetic electrons in two energy ranges and energetic protons are given in terms of occurrence frequency and the average particle flux intensity over an 80 earth radii x 70 earth radii plane perpendicular to the sun-earth line. A particle distribution in the shape of an O with a crossbar over the solar magnetospheric YZ plane in the antisolar direction is clearly demonstrated at all energies and for both species. It is pointed out that the O part of the distribution corresponds to the magnetosheath region and that the crossbar is the average plasma sheet configuration. A distinct, species dependent, dawn-dusk asymmetry in particle distribution is observed in the plasma sheet and, to a lesser extent, in the magnetosheath.

Meng, C.-I.↗

Dynamic switch matrix for the TDMA satellite switching system

Future high capacity satellite communication systems require signal processing on board satellites. The on-board signal processing includes switching of RF signals between multiple antennas to provide interconnection between the uplink and downlink beams. This paper describes the development of a dynamic switch matrix for a TDMA satellite switching system to be used in the next generation communications satellites. In this paper, a dynamic switch matrix, which includes the microwave switch matrix, the distribution control unit and the timing source, will be described. Several different microwave switch matrix architectures and switching devices were evaluated and compared. A unique coupler crossbar switch matrix architecture with dual-gate field effect transistor as switching element was developed. Experimental results of both microwave switch matrix (MSM) and distribution control unit (DCU) are presented. These test results verify the MSM with coupler crossbar architecture and dual-gate FET as switching element will meet the future SS-TDMA system requirements. Finally, the reliability of the dynamic switch matrix is addressed. The analysis shows reliability of 0.9981 for 7 year space operation can be achieved for the designed dynamic switch matrix.

Ho, P. T.↗

Spacecraft in switch matrix for wide band service applicatons in 30/20 GHz communications satellite systems

Bandwidth, switching speed, off-state isolation, and reliability over a ten-year mission were factors in determining the optimum available technology for satellite communications switching in 1982. A proof of concept model for a 20 x 20 coupled crossbar switch matrix designed with FET devices for microwave switching and with high speed CMOS LIS for switch crosspoint addressing was fabricated and tested. Results show the design is feasible for application in a multichannel SS-TDMA communications system. Expandibility can readily be achieved with this design. A conceptual design study for a 100 x 100 switch matrix utilizing a coupled crossbar architecture implemented with a monolithic microwave integrated circuits revealed technology needs for high capacity switch matrices.

Cory, B. J.↗

Scalable polylithic on-package integratable apparatus and method

Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

42 ENGINEERING↗

Apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual mode input-output ports and programmable network interfaces

Described is an apparatus which comprises: a Network-On-Chip fabric using crossbar switches, having distributed ingress and egress ports; and a dual-mode network interface coupled to at least one crossbar switch, the dual-mode network interface is to include: a dual-mode circuitry; a controller operable to: configure the dual-mode circuitry to transmit and receive differential signals via the egress and ingress ports, respectively, and configure the dual-mode circuitry to transmit and receive signal-ended signals via the egress and ingress ports, respectively.

97 MATHEMATICS AND COMPUTING↗

The organic redox transistor for neuromorphic computing

Inspired by the in-memory computing architectures of biological systems, neuromorphic computing using crossbar arrays of artificial synapses based on non-volatile memory (NVM) devices with variable conductances has emerged as a new paradigm to enable massively parallel and ultra-low power computing hardware for data centric applications. Although inference has been demonstrated successfully using crossbars based on a variety of NMV technologies, efficient learning and scaling to large arrays (>10 6 elements) remains a challenge due to the synaptic elements' non-ideal electrical characteristics which degrades ANN accuracy. A further challenge is that in the conductive state memristors draw large currents >μA resulting in significant voltage drops in the interconnect wires and increased probability of failure in scaled arrays. We suggest the organic polymer redox transistor (RT) is an alternate approach that could solve many of these challenges, enabling both inference and parallel outer product updates, as recently demonstrated by Fuller et al. An RT consists of redox-active channel and gate electrodes in contact with a liquid or solid electrolyte. lon insertion through the electrolyte controls the channel electronic conductivity, while electron transfer through an external circuit maintains overall charge neutrality. Unlike a rechargeable battery, in the RT the voltage built-up across the electrolyte is kept to a minimum (typically <100 mV) by using the same material for the gate and channel. Elimination of the voltage offset simplifies integration of the RT into programmable arrays by enabling the use of various selectors. RTs based on inorganic and organic materials have been recently demonstrated with conductance tuning occurring at potentials of just a few mV and hundreds to thousands of linearly and symmetrically programmable conductance states, enabling near ideal accuracy in neural network simulations. Introduced in the 1980's, redox transistors with metallic gate electrodes and organic channel materials, also known as organic electrochemical transistors (OECTs), have been explored for a variety of applications such as chem- and bio-sensing, neural interfaces, and low cost printed circuits. A typical channel material for OECTs is the conducting polymer poly(3,4-ethylenedioxythiophene) doped with poly(styrene sulfonate) (PEDOT:PSS). PEDOT is a p-type semiconducting polymer with mobile positively charged polarons that hop chain-to-chain.

Talin, Albert Alec↗

Scalable polylithic on-package integratable apparatus and method

Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

Khare, Surhud↗

Shape-Based Magnetic Domain Wall Drift for an Artificial Spintronic Leaky Integrate-and-Fire Neuron

Spintronic devices based on domain wall (DW) motion through ferromagnetic nanowire tracks have received great interest as components of neuromorphic information processing systems. Prior proposals for spintronic artificial neurons required external stimuli to perform the leaking functionality, one of the three fundamental functions of a leaky integrate-and-fire (LIF) neuron. The use of this external magnetic field or electrical current stimulus results in either a decrease in energy efficiency or an increase in fabrication complexity. Here, we modify the shape of previously demonstrated three-terminal magnetic tunnel junction neurons to perform the leaking operation without any external stimuli. The trapezoidal structure causes a shape-based DW drift, thus intrinsically providing the leaking functionality with no hardware cost. This LIF neuron, thus, promises to advance the development of spintronic neural network crossbar arrays.

42 ENGINEERING↗

Variation-Resilient FeFET-Based In-Memory Computing Leveraging Probabilistic Deep Learning

Reliability issues stemming from device level nonidealities of nonvolatile emerging technologies like ferroelectric field-effect transistors (FeFETs), especially at scaled dimensions, cause substantial degradation in the accuracy of in-memory crossbar-based AI systems. Here, in this work, we present a variation-aware design technique to characterize the device level variations and to mitigate their impact on hardware accuracy employing a Bayesian neural network (BNN) approach. An effective conductance variation model is derived from the experimental measurements of cycle-to-cycle (C2C) and device-to-device (D2D) variations performed on FeFET devices fabricated using 28 nm high-k metal gate technology. The variations were found to be a function of different conductance states within the given programming range, which sharply contrasts earlier efforts where a fixed variation dispersion was considered for all conductance values. Such variation characteristics formulated for three different device sizes at different read voltages were provided as prior variation information to the BNN to yield a more exact and reliable inference. Near-ideal accuracy for shallow networks (MLP5 and LeNet models) on the MNIST dataset and limited accuracy decline by ~3.8%–16.1% for deeper AlexNet models on CIFAR10 dataset under a wide range of variations corresponding to different device sizes and read voltages, demonstrates the efficacy of our proposed device-algorithm co-design technique.

97 MATHEMATICS AND COMPUTING↗