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At least 73 records · Page 4

An organic electrochemical transistor for multi-modal sensing, memory and processing

By integrating sensing, memory and processing functionalities, biological nervous systems are energy and area efficient. Emulating such capabilities in artificial systems is, however, challenging and is limited by the device heterogeneity of sensing and processing cores. Here we report an organic electrochemical transistor capable of sensing, memory and processing. The device has a vertical traverse architecture and a crystalline–amorphous channel that can be selectively doped by ions to enable two reconfigurable modes: a volatile receptor and a non-volatile synapse. As a volatile receptor, the device is capable of multi-modal sensing and is responsive to stimuli such as ions and light. As a non-volatile synapse, it is capable of 10-bit analogue states, low switching stochasticity and good state retention. We also show that the homogeneous integration of the devices could provide functions such as conditioned reflexes and could be used for real-time cardiac disease diagnoses via reservoir computing.

97 MATHEMATICS AND COMPUTING↗

Hardware accelerated dynamic work creation on a graphics processing unit

A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

Gutierrez, Anthony↗

Hardware accelerated dynamic work creation on a graphics processing unit

A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

Gutierrez, Anthony T.↗

Thin liquid film as an optical nonlinear-nonlocal medium and memory element in integrated optofluidic reservoir computer

Understanding light–matter interaction lies at the core of our ability to harness physical effects and to translate them into new capabilities realized in modern integrated photonics platforms. Here, we present the design and characterization of optofluidic components in an integrated photonics platform and computationally predict a series of physical effects that rely on thermocapillary-driven interaction between waveguide modes and topography changes of optically thin liquid dielectric film. Our results indicate that this coupling introduces substantial self-induced phase change and transmittance change in a single channel waveguide, transmittance through the Bragg grating waveguide, and nonlocal interaction between adjacent waveguides. We then employ the self-induced effects together with the inherent built-in finite relaxation time of the liquid film, to demonstrate that the light-driven deformation can serve as a reservoir computer capable of performing digital and analog tasks, where the gas–liquid interface operates both as a nonlinear actuator and as an optical memory element.

42 ENGINEERING↗

An Accelerated Clip Algorithm for Unstructured Meshes: A Batch-Driven Approach

The clip technique is a popular method for visualizing complex structures and phenomena within 3D unstructured meshes. Meshes can be clipped by specifying a scalar isovalue to produce an output unstructured mesh with its external surface as the isovalue. Similar to isocontouring, the clipping process relies on scalar data associated with the mesh points, including scalar data generated by implicit functions such as planes, boxes, and spheres, which facilitates the visualization of results interior to the grid. In this paper, we introduce a novel batch-driven parallel algorithm based on a sequential clip algorithm designed for high-quality results in partial volume extraction. Our algorithm comprises five passes, each progressively processing data to generate the resulting clipped unstructured mesh. The novelty lies in the use of fixed-size batches of points and cells, which enable rapid workload trimming and parallel processing, leading to a significantly improved memory footprint and run-time performance compared to the original version. On a 32-core CPU, the proposed batch-driven parallel algorithm demonstrates a run-time speed-up of up to 32.6x and a memory footprint reduction of up to 4.37x compared to the existing sequential algorithm. The software is currently available under an open-source license in the VTK visualization system.

Tsalikis, Spiros↗

A Survey on the Expanding Scope and Interdisciplinary Opportunities for Processing-in-Memory Techniques

Processing-in-Memory (PIM) is emerging as a practical path to overcome the limitations of traditional von Neumann architectures. At its core, PIM systems implement computing primitives such as logic operations and multiply-accumulate acceleration through compute-in-memory, near-memory processing, or hybrid designs. The role of memory cells varies widely across technologies, acting as inputs, outputs, or analog accumulators through bit-lines and sense amplifiers. This diversity creates trade-offs in precision, bandwidth, latency, and programmability, making it difficult to build a unified understanding on the progress of the field. In this survey, we organize recent advances of PIM into three areas. First, we discuss the progress on the architectural optimizations of PIM and its integration with both DRAM and emerging non-volatile memories. Second, we examine how PIM is being used to accelerate key computing domains, including generative AI workloads and high-performance kernels, along with new approaches. Third, we highlight the growing adoption of PIM in computational sciences, where it is being applied to solve interdisciplinary problems such as genome analysis, mRNA quantification, mass spectrometry, quantum circuit simulation, wave modeling, and secure computation. Finally, we synthesize the major challenges that continue to slow PIM adoption, including manufacturing constraints, power delivery, thermal reliability, data consistency, runtime and memory-management coordination, and the difficulty of building portable software abstractions without sacrificing commercial viability. This work provides an updated, structured perspective on PIM’s potential across computing and computational sciences and the barriers that must be solved for it to reach its full impact.

Asifuzzaman, Kazi [Oak Ridge National Laboratory (↗

Multithreading ATLAS offline software: A retrospective

For Run 3, ATLAS redesigned its offline software, Athena, so that the main workflows run completely multithreaded. The resulting substantial reduction in the overall memory requirements allows for better use of machines with many cores. This note will discuss the performance achieved by the multithreaded reconstruction, the process of migrating the large ATLAS code base, and tools and techniques that were useful in debugging threading-related problems.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

Refining HPCToolkit for application performance analysis at exascale

As part of the US Department of Energy’s Exascale Computing Project (ECP), Rice University has been refining its HPCToolkit performance tools to better support measurement and analysis of applications executing on exascale supercomputers. To efficiently collect performance measurements of GPU-accelerated applications, HPCToolkit employs novel non-blocking data structures to communicate performance measurements between tool threads and application threads. To attribute performance information in detail to source lines, loop nests, and inlined call chains, HPCToolkit performs parallel analysis of large CPU and GPU binaries involved in the execution of an exascale application to rapidly recover mappings between machine instructions and source code. To analyze terabytes of performance measurements gathered during executions at exascale, HPCToolkit employs distributed-memory parallelism, multithreading, sparse data structures, and out-of-core streaming analysis algorithms. To support interactive exploration of profiles up to terabytes in size, HPCToolkit’s hpcviewer graphical user interface uses out-of-core methods to visualize performance data. The result of these efforts is that HPCToolkit now supports collection, analysis, and presentation of profiles and traces of GPU-accelerated applications at exascale. These improvements have enabled HPCToolkit to efficiently measure, analyze and explore terabytes of performance data for executions using as many as 64K MPI ranks and 64K GPU tiles on ORNL’s Frontier supercomputer. HPCToolkit’s support for measurement and analysis of GPU-accelerated applications has been employed to study a collection of open-science applications developed as part of ECP. This paper reports on these experiences, which provided insight into opportunities for tuning applications, strengths and weaknesses of HPCToolkit itself, as well as unexpected behaviors in executions at exascale.

Adhianto, Laksono↗

Electron energy loss spectroscopy database synthesis and automation of core-loss edge recognition by deep-learning neural networks

Abstract The ionization edges encoded in the electron energy loss spectroscopy (EELS) spectra enable advanced material analysis including composition analyses and elemental quantifications. The development of the parallel EELS instrument and fast, sensitive detectors have greatly improved the acquisition speed of EELS spectra. However, the traditional way of core-loss edge recognition is experience based and human labor dependent, which limits the processing speed. So far, the low signal–noise ratio and the low jump ratio of the core-loss edges on the raw EELS spectra have been challenging for the automation of edge recognition. In this work, a convolutional-bidirectional long short-term memory neural network (CNN-BiLSTM) is proposed to automate the detection and elemental identification of core-loss edges from raw spectra. An EELS spectral database is synthesized by using our forward model to assist in the training and validation of the neural network. To make the synthesized spectra resemble the real spectra, we collected a large library of experimentally acquired EELS core edges. In synthesize the training library, the edges are modeled by fitting the multi-Gaussian model to the real edges from experiments, and the noise and instrumental imperfectness are simulated and added. The well-trained CNN-BiLSTM network is tested against both the simulated spectra and real spectra collected from experiments. The high accuracy of the network, 94.9%, proves that, without complicated preprocessing of the raw spectra, the proposed CNN-BiLSTM network achieves the automation of core-loss edge recognition for EELS spectra with high accuracy.

36 MATERIALS SCIENCE↗

HAM: Hotspot-Aware Manager for Improving Communications with 3D-Stacked Memory

merging High-Performance Computing (HPC) workloads, such as graph analytics, machine learning, and big data science, are data-intensive. Data-intensive workloads usually present fine-grained memory accesses with limited or no data locality, and thus incur frequent cache misses and low utilization of memory bandwidth. 3D-stacked memory devices such as Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) can provide significantly higher bandwidth than conventional memory modules. However, the traditional interfaces and optimization methods for JEDEC DDR devices do not allow to fully exploit the potential performance of 3D-stacked memory with the massive amount of irregular memory accesses of data-intensive applications. In this paper, we propose a novel Hotspot-Aware Manager (HAM) infrastructure for 3D-stacked memory devices capable of optimizing memory access streams via request aggregation, hotspot detection, and in-memory prefetching. %and an associated hotspot-aware page policy. We present the HAM design and implementation, and simulate it on a system using RISC-V embedded cores with attached HMC devices. We extensively evaluate HAM with over 12 benchmarks and applications representing diverse irregular memory access patterns. The results show that, on average, HAM reduces redundant requests by 37.51\% and increases the prefetch buffer hit rate by 4.2 times, compared to a baseline streaming prefetcher. On the selected benchmark set, HAM provides performance gains of 21.81\% in average (up to 34.28\%) and power savings of 35.07\% over a standard 3D-stacked memory.

Wang, Xi↗

Kernel fusion in atomistic spin dynamics simulations on Nvidia GPUs using tensor core

In atomistic spin dynamics simulations, the time cost of constructing the space- and time-displaced pair correlation function in real space increases quadratically as the number of spins N, leading to significant computational effort. The GEMM subroutine can be adopted to accelerate the calculation of the dynamical spin-spin correlation function, but the computational cost of simulating large spin systems (>40000 spins) on CPUs remains expensive. In this work, we perform the simulation on the graphics processing unit (GPU), a hardware solution widely used as an accelerator for scientific computing and deep learning. Here we show that GPUs can accelerate the simulation up to 25-fold compared to multi-core CPUs when using the GEMM subroutine on both. To hide memory latency, we fuse the element-wise operation into the GEMM kernel using CUTLASS that can improve the performance by 26% ~ 33% compared to implementation based on cuBLAS. Furthermore, we perform the on-the-fly calculation in the epilogue of the GEMM subroutine to avoid saving intermediate results on global memory, which makes the large-scale atomistic spin dynamics simulation feasible and affordable.

97 MATHEMATICS AND COMPUTING↗

Automated Hybrid Variance Reduction on Advanced Architectures in the Shift Monte Carlo Code

Monte Carlo transport methods are the most accurate schemes for solving problems with complex energy and spatial features, but they come with a high computational cost. Although hybrid methods have enabled the use of Monte Carlo transport for a large class of problems, they still require significant computing resources. Modern multicore CPUs with large numbers of compute cores and graphical processing units (GPUs) provide opportunities to optimize the memory and run-time costs of hybrid Monte Carlo methods. This paper documents the development and analysis of three Monte Carlo transport algorithms that support hybrid transport using the consistent adjoint-driven importance sampling (CADIS) and forward-weighted CADIS methods in the Shift Monte Carlo code: history-based transport using static and dynamic threading on multicore CPUs and event-based transport enabling weight window tracking on GPUs. The results are shown for two challenging hybrid problems on the Frontier supercomputer at the Oak Ridge Leadership Computing Facility. The results show that all three methods yield good performance and enable solutions of difficult fixed-source transport problems in less than 2 min on 20 nodes of Frontier. Dynamic threading was observed to give up to 20% better scaling behavior than static threading. Moreover, the AMD Instinct 250X GPU was found to give 9 to 11 times greater throughput per graphics compute die than the best CPU performance. In conclusion, additional opportunities for optimization of hybrid transport on GPUs are discussed.

Denovo↗

Neuromorphic Accelerator for Deep Spiking Neural Networks with NVM Crossbar Arrays

In this paper, we present a scalable digital hardware accelerator based on non-volatile memory arrays capable of realizing deep convolutional spiking neural networks (SNNs). Our design studies are conducted using a compact model for spin-transfer torque random access memory (STT-RAM) devices. Large networks are realized by tiling multiple cores which communicate by transmitting spike packets via an on-chip routing network. Compared to an equivalent SRAM based core design, we show that the STT-RAM based design achieves nearly 15X higher GSOPS (Synaptic Operations per Second) per Watt per mm 2 making it a promising platform for realizing systems with significant area and power limitations.

Kulkarni, Shruti↗

Medial axis and local thickness computation using the Fast Sweeping Method

This report describes an efficient and robust voxel-based methodology for computing the medial axis, local thickness, and distance-to-skeleton of arbitrary three-dimensional geometries. It is assumed that the object can be represented by an exact or approximate signed distance function on a discrete grid. The gradient of such function is used to formulate a hyperbolic partial differential equation (PDE) that models the collapse of the position vector in space. By exploiting the causality property of the PDE, the Fast Sweeping Method is able to obtain the solution in a finite number of sweeps independent of the mesh resolution. The intersection of characteristic lines leads to the formation of shocks and a discrete bisector function is used to identify the medial axis. The same PDE approach is used to compute the local thickness inside the object and obtain the distance-to-skeleton field. Multiple examples are given in two and three dimensions along with a resolution study. The methodology has optimal complexity and yields subsecond computational times for geometries with over a million zones on a single core. The methodology is also capable of parallelization across shared and distributed memory architectures.

97 MATHEMATICS AND COMPUTING↗

CMSSW Scaling Limits on Many-Core Machines

Today the LHC offline computing relies heavily on CPU resources, despite the interest in compute accelerators, such as GPUs, for the longer term future. The number of cores per CPU socket has continued to increase steadily, reaching the levels of 64 cores (128 threads) with recent AMD EPYC processors, and 128 cores on Ampere Altra Max ARM processors. Over the course of the past decade, the CMS data processing framework, CMSSW, has been transformed from a single-threaded framework into a highly concurrent one. The first multithreaded version was brought into production by the start of the LHC Run 2 in 2015. Since then, the framework's threading efficiency has gradually been improved by adding more levels of concurrency and reducing the amount of serial code paths. The latest addition was support for concurrent Runs. In this work we review the concurrency model of the CMSSW, and measure its scalability with real CMS applications, such as simulation and reconstruction, on mode rn many-core machines. We show metrics such as event processing throughput and application memory usage with and without the contribution of I/O, as I/O has been the major scaling limitation for the CMS applications.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

Cooling and Timing Tests of the ATLAS Fast TracKer VME Boards

The Fast TracKer (FTK) is an ATLAS trigger upgrade built for full-event, low-latency, high-rate tracking. The FTK core, made of 9U VME boards, performs the most demanding computational task. The associative memory board (AMB) serial link processor and the auxiliary card (AUX), plugged on the front and back sides of the same VME slot, constitute the processing unit (PU), which finds tracks using hits from eight layers of the inner detector. The PU works in pipeline with the second stage board (SSB), which finds 12-layer tracks by adding extra hits to the identified tracks. In the designed configuration, 16 PUs and four SSBs are installed in a VME crate. The high power consumption of the AMB, AUX, and SSB (respectively, of about 250, 70, and 160 W per board) required the development of a custom cooling system. Even though the expected power consumption for each VME crate of the FTK system is high compared with a common VME setup, the 8 FTK core crates will use ≈60 kW, which is just a fraction of the power and the space needed for a CPU farm performing the same task. We report on the integration of 32 PUs and eight SSBs inside the FTK system, on the infrastructures needed to run and cool them, and on the tests performed to verify the system processing rate and the temperature stability at a safe value.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

Assessment of the Griffin Reactor Multiphysics Application Using the Empire Micro Reactor Design Concept

In late 2019, INL and ANL agreed to jointly develop the reactor physics code named Griffin based on the integration of the two code suites, MAMMOTH/Rattlesnake (INL) and MC2 - 3/PROTEUS (ANL). Griffin is being developed based on the MOOSE framework and MOOSE quality assurance procedures. This decision was made to be able to allow DOE-NE to efficiently invest funding to this area and to provide effective and timely support for existing and potential users; the latter includes industry and government organizations who are developing various types of advanced reactors in the near and long term. Since MAMMOTH/Rattlesnake has been developed based on the MOOSE framework, the INL/ANL Griffin development team agreed to build Griffin beginning with a merger of MAMMOTH and Rattlesnake into a single code and moving forward by implementing capabilities from the PROTEUS suite into Griffin. Moving forward, both ANL and INL efforts are equally invested in the Griffin project, with management support, to provide an advanced reactor multiphysics tool to assist in reactor design, optimization, and safety analysis. Much work remains in moving Griffin forward to migrate PROTEUS capabilities and to optimize performance to meet user needs. The main objective of this work is to assess the current status of Griffin capabilities in terms of performance and accuracy, to determine priorities for PROTEUS migration, and to identify capabilities and features to improve for supporting the code integration effort. For this assessment, the Empire micro reactor problem that was developed in the ARPA-E MEITNER program was selected as an advance reactor concept of interest to the technical community. The Empire reactor problem was expanded from its original incomplete specification to be a small heat-pipe-cooled micro reactor core with ~113 cm radius and 70 cm in height, composed of 18 fuel assemblies, 12 control drums, and beryllium radial and axial reflectors. In the current model, using 5 cm axial reflectors specified in the original Empire assembly model, more than 10% of neutrons leak axially and through the empty center safety hole, as well as through heat pipe channels in fuel assembly elements that extend through the top reflector region. Several calculation models of the core were defined for systematic assessment, including 2-D and 3-D fuel assemblies and whole cores with cylindrical boundaries. Cross sections were generated using Serpent 2, and meshes were produced using the Argonne mesh tool or the INL neutronics meshing tools combined with CUBIT. Cross sections and meshes were converted to the ISOXML and Exodus formats, respectively, so that Griffin and PROTEUS could use consistent data for solving the reactor problems. With the prepared cross sections and meshes, PROTEUS was run first to ensure that all input data were correctly generated and input options in terms of angle, mesh, and energy group were accurately determined. Comparisons against Serpent 2 solutions were made in terms of eigenvalue and pin power. The same calculations and comparisons were then conducted using Griffin. For the fuel assembly and whole core problems, the PROTEUS eigenvalues agreed well with reference Serpent 2 solutions within 100 and 30 pcm, respectively, and pin power differences relative to Serpent 2 were overall less than 2.2% and RMS 0.8% for the whole core models. This indicated that all input data were properly prepared. Using the same data, Griffin was run selecting the SAAF-CFEM SN solver with Legendre-Gaussian quadrature and NDA and DSA for acceleration. It was found that the SAAF-CFEM solver of Griffin required finer meshes to achieve eigenvalue and pin power solutions in good agreement with Serpent 2, consequently requiring more memory requirement and longer computation time. On the other hand, the SPH-Diffusion 2-D core calculations performed using Griffin were able to recover the exact eigenvalue from the reference Serpent 2 solutions, resulting in a pin-power distribution with an RMS of 0.6% and maximum absolute difference of less than 1.4%. The runtimes for SPH-Diffusion for the 2-D core were less than 3 minutes on 40 cores. During this evolution of this evaluation, many updates were made in Griffin by the Griffin development team of INL (focusing on software updates) and ANL (reviewing and supporting software updates) to complete this assessment. Observations from the code assessment are presented in the conclusion section of this report, followed by a discussion of recommendations for future work.

21 SPECIFIC NUCLEAR REACTORS AND ASSOCIATED PLANTS↗