Shared-Memory Scalable k-Core Maintenance on Dynamic Graphs and Hypergraphs.
Abstract not provided.
Gabert, Kasimir Georg↗
SEARCH · Engineering Papers
Results for “core memory”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Enhancements to the IBM version of COSMIC/NASTRAN
Major improvements were made to the IBM version of COSMIC/NASTRAN by RPK Corporation under contract to IBM Corporation. These improvements will become part of COSMIC's IBM version and will be available in the second quarter of 1989. The first improvement is the inclusion of code to take advantage of IBM's new Vector Facility (VF) on its 3090 machines. The remaining improvements are modifications that will benefit all users as a result of the extended addressing capability provided by the MVS/XA operating system. These improvements include the availability of an in-memory data base that potentially eliminates the need for I/O to the PRIxx disk files. Another improvement is the elimination of multiple load modules that have to be loaded for every link switch within NASTRAN. The last improvement allows for NASTRAN to execute above the 16 mega-byte line. This improvement allows for NASTRAN to have access to 2 giga-bytes of memory for open core and the in-memory data base.
Brown, W. Keith↗
Indicator-directed Dynamic Power Management for Iterative Workloads on GPU-Accelerated Systems
Modern high-performance and warehouse computing centers show strong interest in minimizing system power consumption while satisfying customers’ quality of service (QoS). Dynamic voltage and frequency scaling (DVFS) is effective for achieving this goal. Nevertheless, automating the process online and making it transparent to users must address three major challenges: (1) Complexity — today’s hardware components (e.g., CPUs, GPUs, memory, network, etc.) can be configured in several or dozens of frequency/voltage states for satisfying divergent system demands. Given their combination and the emergence of heterogeneity, searching the optimal configuration in the design space online can be timing consuming. (2) QoS guarantee — user-defined objectives such as power constraint and performance target must be monitored, predicted and ensured at the best effort. (3) Adaptability — various known and unknown workloads run on systems. Workloads characteristics should be quickly determined and configurations dynamically adjusted in accord with workloads and QoS. In this work, we focus on applications exhibiting an interesting feature – iterative or periodic, which is common among conventional HPC and emerging machine learning workloads. We propose an online dynamic power-performance (ODPP) management framework to dynamically adjust GPU DVFS configurations to meet performance and power objectives and constraints, without any code annotation or intrusion. Particularly, ODPP extracts the performance and power indicators for applications from their resources utilization profiles in a short episode. It further automatically constructs an accurate model that infers from the indicators how the application's performance and power vary with GPU core and memory frequencies. Aided with the model, for both seen and unseen applications, ODPP can quickly determine the most appropriate DVFS configuration for their execution. We evaluate ODPP on an NVIDIA GPU using multiple exascale computing (ECP) and deep learning applications.
Zou, Pengfei↗
A compute-bound formulation of Galerkin model reduction for linear time-invariant dynamical systems
This work aims to advance computational methods for projection-based reduced-order models (ROMs) of linear time-invariant (LTI) dynamical systems. For such systems, current practice relies on ROM formulations expressing the state as a rank-1 tensor (i.e., a vector), leading to computational kernels that are memory bandwidth bound and, therefore, ill-suited for scalable performance on modern architectures. This weakness can be particularly limiting when tackling many-query studies, where one needs to run a large number of simulations. This work introduces a reformulation, called rank-2 Galerkin, of the Galerkin ROM for LTI dynamical systems which converts the nature of the ROM problem from memory bandwidth to compute bound. We present the details of the formulation and its implementation, and demonstrate its utility through numerical experiments using, as a test case, the simulation of elastic seismic shear waves in an axisymmetric domain. We quantify and analyze performance and scaling results for varying numbers of threads and problem sizes. In conclusion, we present an end-to-end demonstration of using the rank-2 Galerkin ROM for a Monte Carlo sampling study. We show that the rank-2 Galerkin ROM is one order of magnitude more efficient than the rank-1 Galerkin ROM (the current practice) and about 970 times more efficient than the full-order model, while maintaining accuracy in both the mean and statistics of the field.
97 MATHEMATICS AND COMPUTING↗
Memory-triggered supernova neutrino detection
Here, we demonstrate that observations of the gravitational memory from core collapse supernovae at future deci-Hz interferometers enable time-triggered searches of supernova neutrinos at Mt-scale detectors. Achieving a sensitivity to characteristic strains of at least $\sim 10^{–25}$ at $f ≃ 0.3$ $\mathrm{Hz}$ —e.g., by improving the noise of DECIGO by one order of magnitude—will allow robust time triggers for supernovae at distances $D \sim 40–300$ $\mathrm{Mpc}$, resulting in a nearly background-free sample of $\sim 3–70$ neutrino events per Mt per decade of operation. This sample would bridge the sensitivity gap between rare galactic supernova bursts and the cosmological diffuse supernova neutrino background, allowing detailed studies of the neutrino emission of supernovae in the local Universe.
79 ASTRONOMY AND ASTROPHYSICS↗
Transonic Navier-Stokes wing solutions using a zonal approach. Part 2: High angle-of-attack simulation
A computer code is under development whereby the thin-layer Reynolds-averaged Navier-Stokes equations are to be applied to realistic fighter-aircraft configurations. This transonic Navier-Stokes code (TNS) utilizes a zonal approach in order to treat complex geometries and satisfy in-core computer memory constraints. The zonal approach has been applied to isolated wing geometries in order to facilitate code development. Part 1 of this paper addresses the TNS finite-difference algorithm, zonal methodology, and code validation with experimental data. Part 2 of this paper addresses some numerical issues such as code robustness, efficiency, and accuracy at high angles of attack. Special free-stream-preserving metrics proved an effective way to treat H-mesh singularities over a large range of severe flow conditions, including strong leading-edge flow gradients, massive shock-induced separation, and stall. Furthermore, lift and drag coefficients have been computed for a wing up through CLmax. Numerical oil flow patterns and particle trajectories are presented both for subcritical and transonic flow. These flow simulations are rich with complex separated flow physics and demonstrate the efficiency and robustness of the zonal approach.
Chaderjian, N. M.↗
Transonic Navier-Stokes wing solutions using a zonal approach. Part 2: High angle-of-attack simulation
A computer code is under development whereby the thin-layer Reynolds-averaged Navier-Stokes equations are to be applied to realistic fighter aircraft configurations. This transonic Navier-Stokes code (TNS) utilizes a zonal approach in order to treat complex geometries and satisfy in-core computer memory constraints. The zonal approach was applied to isolated wing geometries in order to facilitate code development. The TNS finite difference algorithm, zonal methodology, and code validation with experimental data is addressed. Also addressed are some numerical issues such as code robustness, efficiency, and accuracy at high angles of attack. Special free-stream-preserving metrics proved an effective way to treat H-mesh singularities over a large range of severe flow conditions, including strong leading edge flow gradients, massive shock induced separation, and stall. Furthermore, lift and drag coefficients were computed for a wing up through CLmax. Numerical oil flow patterns and particle trajectories are presented both for subcritical and transonic flow. These flow simulations are rich with complex separated flow physics and demonstrate the efficiency and robustness of the zonal approach.
Chaderjian, Neal M.↗
Multi-level Hierarchical Poly Tree computer architectures
Based on the concept of hierarchical substructuring, this paper develops an optimal multi-level Hierarchical Poly Tree (HPT) parallel computer architecture scheme which is applicable to the solution of finite element and difference simulations. Emphasis is given to minimizing computational effort, in-core/out-of-core memory requirements, and the data transfer between processors. In addition, a simplified communications network that reduces the number of I/O channels between processors is presented. HPT configurations that yield optimal superlinearities are also demonstrated. Moreover, to generalize the scope of applicability, special attention is given to developing: (1) multi-level reduction trees which provide an orderly/optimal procedure by which model densification/simplification can be achieved, as well as (2) methodologies enabling processor grading that yields architectures with varying types of multi-level granularity.
Padovan, Joe↗
Performance and usability enhancements for continuous subgraph matching queries on graph-structured data
A query graph, which includes vertices and edges, represents a query on graph-structured data. The query graph is decomposed into query subgraphs. A network analysis tool performs continuous subgraph matching queries to facilitate analysis of computer network traffic, social media events, or other streams of data represented as a dynamic data graph (graph-structured data). This can help identify emerging trends in the data. Some features of the network analysis tool enhance performance by effectively utilizing distributed computing resources (including processing cores and memory at different nodes of a cluster) to speed up the process of updating the dynamic data graph and detecting matches of query subgraphs. Features of a query graph building tool enhance usability by providing intuitive ways to specify query graphs and their subgraphs. Features of a results visualization tool enhance usability by providing an intuitive way to present the results of continuous subgraph matching queries.
Choudhury, Sutanay↗
Auxiliary memory for Apollo guidance computer, volume 1 Final report
Auxiliary core and tape memory for Apollo guidance computer
Source record↗
Spaceborne Processor Array
A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.
Chow, Edward T.↗
ZFP Hardware Implementation
As core counts increase in new HPC systems with comparatively little increase in memory bandwidth, the trend is an effective decrease in memory bandwidth per core. Other bandwidth limitations in HPC systems exist between CPU and GPU memory, between system nodes, and between node memory and storage. Compression of floating-point data has the potential to reduce data movement and pressure across these communication channels. Furthermore, it has the potential to reduce the footprint of floating-point arrays stored in memory. ZFP, implemented in software, is gaining traction as an effective method in floating-point compression; however, performance gains are limited to the spare compute cycles available before reaching the bandwidth limitations of the communication channel. A hardware implementation of ZFP has the potential to raise the bar on performance. From the inception of ZFP, it was designed to accommodate a hardware implementation.
42 ENGINEERING↗
Circuit detects errors in address currents for magnetic core arrays.
Address current error detector generates signal whenever error-producing conditions arise in magnetic core arrays
MEMORY STORAGE UNIT↗
Memory Overview - Technologies and Needs
As NASA has evolved it's usage of spaceflight computing, memory applications have followed as well. In this talk, we will discuss the history of NASA's memories from magnetic core and tape recorders to current semiconductor approaches. We will briefly describe current functional memory usage in NASA space systems followed by a description of potential radiation-induced failure modes along with considerations for reliable system design.
LaBel, Kenneth A.↗
Potential bio-medical and commercial applications of cold hibernated elastic memory (CHEM) self-deployable foam structures
A cold hibernated elastic memory (CHEM) foam structure is one of the most recent results of the quest for simple, reliable and low-cost expandable space structures. The CHEM technology utilizes shape memory polymers in open cellular (foam) structure or sandwich structures made of shape memory polymer foam cores and polymeric composite skins. It takes advantage of the polymer’s heat activated shape memory in addition to the foam’s elastic recovery to deploy a compacted structure. The glass transition temperature, Tg is tailored to rigidize the structure in the fully deployed configuration.
Sokolowski, Witold↗
Memories and NASA Spacecraft: A Description of Memories, Radiation Failure Modes, and System Design Considerations
As NASA has evolved it's usage of spaceflight computing, memory applications have followed as well. In this slide presentation, the history of NASA's memories from magnetic core and tape recorders to current semiconductor approaches is discussed. There is a brief description of current functional memory usage in NASA space systems followed by a description of potential radiation-induced failure modes along with considerations for reliable system design.
LaBel, Kenneth A.↗
Accuracy Enhancement of Nuclear Power Plant Simulators Utilizing High Accuracy Simulation Predictions
More recently, reactor core simulators for core designs associated with commercial nuclear power plants that utilize what is believed to be higher fidelity models have been developed. Features such as neutronics models that utilize transport equation solvers with fine spatial meshes and many energy-groups, thermal-hydraulic models that utilize sub-channel solvers with fine spatial mesh and capable of treating a wide range of fluid conditions, and fuel-coolant chemistry interaction models capable of treating CRUD deposition are to be found in these higher fidelity core simulators. These reactor core simulators require access to higher performance computers, characterized by many processors, cores and large memory. So associated with utilization of these simulators is access to high performance computers and ability to accommodate in one’s workflow longer execution times. By contrast, currently used core simulators by the nuclear industry can execute on engineering workstations and have execution times of seconds to minutes. The desirability for having short execution times is not only desired for support of time critical tasks but supports the mental process of decision making by engineers. The goal of the work reported upon here has the objective of retaining the fidelity of higher fidelity models while retaining the ability to utilize engineering workstations. Beyond the core simulator goal, additional goals of this work include incorporating the just described core simulator capability into a Nuclear Steam Supply System (NSSS) simulator, and to incorporate the resulting capability into an environment supportive of design and operational decision making associated with nuclear power stations. The model selected for the core neutronics model is the NESTLE code, for the core thermal-hydraulic model is the CTF code utilizing coarse mesh, and for the NSSS model is the RELAP5-3D code. WSC’s proprietary 3KEYMASTERTM platform is being used to provide software coupling, user interface, visualization, and reporting. The NESTLE core neutronics simulator was first integrated with the CTF core thermal-hydraulic simulator using CTF developed communication commands which are also used for CTF to communicate with RELAP5-3D under WSC’s proprietary 3KEYMASTERTM platform. To assure NESTLE prediction consistency with higher fidelity core neutronic simulators, buffer codes have been created to automatically generate from output files written by the VERA core simulator the NESTLE nodal neutronic parameter’ library, geometry, and pin-power reconstruction input files, thereby avoiding a number of challenges associated with utilizing lattice physics codes and providing consistency with VERA predictions. To treat absorber rod effects a multi-set library is utilized, where a set refers to a specific absorber rod fully inserted pattern. A coarse spatial mesh CTF model was developed with features added that support using CTF as envisioned in the engineering quality simulator. A hybrid meshing approach was implemented to allow for automated construction of models with mixed levels of refinement. Specifically, a core model could resolve some assemblies at a nodal level (4 subchannels per assembly) and others at a pin-resolution (one subchannel per coolant subchannel in the assembly). The intention is that this will allow for better resolution of limiting conditions such as DNBR and PCT, which are based on local rod and subchannel conditions. Further development was done of features that enhance the capabilities for the envisioned engineering quality simulator that has been developed, but now for RELAP-3D. The RELAP5-3D code development includes ability to model more than 999 components and the addition of the cross-channels turbulence mixing model and the void drift model that are implemented in CTF, aiming to achieve closer prediction agreement of the two codes for transient simulations, specifically, more accurate matches of the overall mass, momentum, and energy exchanges of both the liquid and gas phases between the neighboring core assemblies. Graphics were also developed for the Instructor Station for this project under WSC’s proprietary 3KEYMASTERTM platform to facilitate design and operational decision making.
42 ENGINEERING↗
Guideline for Single-Event Effect (SEE) Testing of System on a Chip (SOC) Devices
The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.
Guertin, Steven M.↗