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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1994

A PC based time domain reflectometer for space station cable fault isolation

Significant problems are faced by astronauts on orbit in the Space Station when trying to locate electrical faults in multi-segment avionics and communication cables. These problems necessitate the development of an automated portable device that will detect and locate cable faults using the pulse-echo technique known as Time Domain Reflectometry. A breadboard time domain reflectometer (TDR) circuit board was designed and developed at the NASA-JSC. The TDR board works in conjunction with a GRiD lap-top computer to automate the fault detection and isolation process. A software program was written to automatically display the nature and location of any possible faults. The breadboard system can isolate open circuit and short circuit faults within two feet in a typical space station cable configuration. Follow-on efforts planned for 1994 will produce a compact, portable prototype Space Station TDR capable of automated switching in multi-conductor cables for high fidelity evaluation. This device has many possible commercial applications, including commercial and military aircraft avionics, cable TV, telephone, communication, information and computer network systems. This paper describes the principle of time domain reflectometry and the methodology for on-orbit avionics utility distribution system repair, utilizing the newly developed device called the Space Station Time Domain Reflectometer (SSTDR).

Pham, Michael↗
NASA NTRS1977

High frequency capacitor-diode voltage multiplier dc-dc converter development

A power conditioner was developed which used a capacitor diode voltage multiplier to provide a high voltage without the use of a step-up transformer. The power conditioner delivered 1200 Vdc at 100 watts and was operated from a 120 Vdc line. The efficiency was in excess of 90 percent. The component weight was 197 grams. A modified boost-add circuit was used for the regulation. A short circuit protection circuit was used which turns off the drive circuit upon a fault condition, and recovers within 5 ms after removal of the short. High energy density polysulfone capacitors and high speed diodes were used in the multiplier circuit.

Kisch, J. J.↗
NASA NTRS1995

Formal development of a clock synchronization circuit

This talk presents the latest stage in formal development of a fault-tolerant clock synchronization circuit. The development spans from a high level specification of the required properties to a circuit realizing the core function of the system. An abstract description of an algorithm has been verified to satisfy the high-level properties using the mechanical verification system EHDM. This abstract description is recast as a behavioral specification input to the Digital Design Derivation system (DDD) developed at Indiana University. DDD provides a formal design algebra for developing correct digital hardware. Using DDD as the principle design environment, a core circuit implementing the clock synchronization algorithm was developed. The design process consisted of standard DDD transformations augmented with an ad hoc refinement justified using the Prototype Verification System (PVS) from SRI International. Subsequent to the above development, Wilfredo Torres-Pomales discovered an area-efficient realization of the same function. Establishing correctness of this optimization requires reasoning in arithmetic, so a general verification is outside the domain of both DDD transformations and model-checking techniques. DDD represents digital hardware by systems of mutually recursive stream equations. A collection of PVS theories was developed to aid in reasoning about DDD-style streams. These theories include a combinator for defining streams that satisfy stream equations, and a means for proving stream equivalence by exhibiting a stream bisimulation. DDD was used to isolate the sub-system involved in Torres-Pomales' optimization. The equivalence between the original design and the optimized verified was verified in PVS by exhibiting a suitable bisimulation. The verification depended upon type constraints on the input streams and made extensive use of the PVS type system. The dependent types in PVS provided a useful mechanism for defining an appropriate bisimulation.

Miner, Paul S.↗
NASA NTRS1985

Method and apparatus for transfer function simulator for testing complex systems

A method and apparatus for testing the operation of a complex stabilization circuit in a closed loop system is presented. The method is comprised of a programmed analog or digital computing system for implementing the transfer function of a load thereby providing a predictable load. The digital computing system employs a table stored in a microprocessor in which precomputed values of the load transfer function are stored for values of input signal from the stabilization circuit over the range of interest. This technique may be used not only for isolating faults in the stabilization circuit, but also for analyzing a fault in a faulty load by so varying parameters of the computing system as to simulate operation of the actual load with the fault.

Kavaya, M. J.↗
NASA NTRS1986

Interface Circuits for Self-Checking Microprocessors

Fault-tolerant-microcomputer concept based on enhancing "simple" computer with redundancy and self-checking logic circuits detect hardware faults. Interface and checking logic and redundant processors confer on 16-bit microcomputer ability to check itself for hardware faults. Checking circuitry also checks itself. Concept of self-checking complementary pairs (SCCP's) employed throughout ICL unit.

Rennels, D. A.↗
NASA NTRS1988

Boolean integral calculus

The concept of Boolean integration is developed, and different Boolean integral operators are introduced. Given the changes in a desired function in terms of the changes in its arguments, the ways of 'integrating' (i.e. realizing) such a function, if it exists, are presented. The necessary and sufficient conditions for integrating, in different senses, the expression specifying the changes are obtained. Boolean calculus has applications in the design of logic circuits and in fault analysis.

Tucker, Jerry H.↗
NASA NTRS1991

Single-chip microcontrollers for switchgear control

A switchgear controller utilizing a microcontroller is described. The primary goal was to mimic the functions and performance of the generic controller board with a microcontroller board which will cause the power automation system to consume less power. The code for the microcontroller implementation on a development board has been developed, and the signal conditioning for the signals to the microcontroller has been designed and tested. The implementation of this decision system for data gathering, command control, fault detection, and circuit protection, when compared to other implementations, provides more functions and better response while reducing weight, volume, and power consumption.

Watson, Karan↗
NASA NTRS1994

Problems with aging wiring in Naval aircraft

The Navy is experiencing a severe aircraft electrical wiring maintenance problem as a result of the extensive use of an aromatic polyimide insulation that is deteriorating at a rate that was unexpected when this wire was initially selected. This problem has significantly affected readiness, reliability, and safety and has greatly increased the cost of ownership of Naval aircraft. Failures in wire harnesses have exhibited arcing and burning that will propagate drastically, to the interruption of many electrical circuits from a fault initiated by the failure of deteriorating wires. There is an urgent need for a capability to schedule aircraft rewiring in an orderly manner with a logically derived determination of which aircraft have aged to the point of absolute necessity. Excessive maintenance was demonstrated to result from the accelerated aging due to the parameters of moisture, temperature, and strain that exist in the Naval Aircraft environment. Laboratory studies have demonstrated that MIL-W-81381 wire insulation when aged at high humidities followed the classical Arrhenius thermal aging relationship. In an extension of the project a multifactor formula was developed that is now capable of predicting life under varying conditions of these service parameters. An automated test system has also been developed to analyze the degree of deterioration that has occurred in wires taken from an aircraft in order to obtain an assessment of remaining life. Since it is both physically and financially impossible to replace the wiring in all the Navy's aircraft at once, this system will permit expedient scheduling so that those aircraft that are most probable to have wiring failure problems can be overhauled first.

Campbell, Frank J.↗
NASA NTRS2010

Self-Validating Thermocouple

Self-Validating Thermocouple (SVT) Systems capable of detecting sensor probe open circuits, short circuits, and unnoticeable faults such as a probe debonding and probe degradation are useful in the measurement of temperatures. SVT Systems provide such capabilities by incorporating a heating or excitation element into the measuring junction of the thermocouple. By heating the measuring junction and observing the decay time for the detected DC voltage signal, it is possible to indicate whether the thermocouple is bonded or debonded. A change in the thermal transfer function of the thermocouple system causes a change in the rise and decay times of the thermocouple output. Incorporation of the excitation element does not interfere with normal thermocouple operation, thus further allowing traditional validation procedures as well.

Perotti, Jose M.↗
NASA NTRS1986

Measurement and application of fault latency

The time interval between the occurrence of a fault and the detection of the error caused by the fault is divided by the generation of that error into two parts: fault latency and error latency. Since the moment of error generation is not directly observable, all related works in the literature have dealt with only the sum of fault and error latencies, thereby making the analysis of their separate effects impossible. To remedy this deficiency, (1) a new methodology for indirectly measuring fault latency is presented; the distribution of fault latency is derived from the methodology; and (3) the knowledge of fault latency is applied to the analysis of two important examples. The proposed methodology has been implemented for measuring fault latency in the Fault-Tolerant Multiprocessor (FTMP) at the NASA Airlab. The experimental results show wide variations in the mean fault latencies of different function circuits within FTMP. Also, the measured distributions of fault latency are shown to have monotone hazard rates. Consequently, Gamma and Weibull distributions are selected for the least-squares fit as the distribution of fault latency.

Shin, K. G.↗
NASA NTRS2006

Evolutionary Based Techniques for Fault Tolerant Field Programmable Gate Arrays

The use of SRAM-based Field Programmable Gate Arrays (FPGAs) is becoming more and more prevalent in space applications. Commercial-grade FPGAs are potentially susceptible to permanently debilitating Single-Event Latchups (SELs). Repair methods based on Evolutionary Algorithms may be applied to FPGA circuits to enable successful fault recovery. This paper presents the experimental results of applying such methods to repair four commonly used circuits (quadrature decoder, 3-by-3-bit multiplier, 3-by-3-bit adder, 440-7 decoder) into which a number of simulated faults have been introduced. The results suggest that evolutionary repair techniques can improve the process of fault recovery when used instead of or as a supplement to Triple Modular Redundancy (TMR), which is currently the predominant method for mitigating FPGA faults.

Larchev, Gregory V.↗
NASA NTRS1966

Circuit protects regulated power supply against overload current

Sensing circuit in which a tunnel diode controls a series regulator transistor protects a low voltage transistorized dc regulator from damage by excessive load currents. When a fault occurs, the faulty circuit is limited to a preset percentage of the current when limiting first occurs.

Airth, H. B.↗
NASA NTRS1993

Design methods for fault-tolerant finite state machines

VLSI electronic circuits are increasingly being used in space-borne applications where high levels of radiation may induce faults, known as single event upsets. In this paper we review the classical methods of designing fault tolerant digital systems, with an emphasis on those methods which are particularly suitable for VLSI-implementation of finite state machines. Four methods are presented and will be compared in terms of design complexity, circuit size, and estimated circuit delay.

Niranjan, Shailesh↗
NASA NTRS2017

Hybrid Direct-Current Circuit Breaker

A circuit breaking system includes a first branch including at least one solid-state snubber; a second branch coupled in parallel to the first branch and including a superconductor and a cryogenic contactor coupled in series; and a controller operatively coupled to the at least one solid-state snubber and the cryogenic contactor and programmed to, when a fault occurs in the load circuit, activate the at least one solid-state snubber for migrating flow of the electrical current from the second branch to the first branch, and, when the fault is cleared in the load circuit, activate the cryogenic contactor for migrating the flow of the electrical current from the first branch to the second branch.

Wang, Ruxi↗
NASA NTRS1981

Fault-tolerant computer study

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed.

Rennels, D. A.↗
NASA NTRS2015

Architecture, Voltage, and Components for a Turboelectric Distributed Propulsion Electric Grid (AVC-TeDP)

The purpose of this effort was to advance the selection, characterization, and modeling of a propulsion electric grid for a Turboelectric Distributed Propulsion (TeDP) system for transport aircraft. The TeDP aircraft would constitute a miniature electric grid with 50 MW or more of total power, two or more generators, redundant transmission lines, and multiple electric motors driving propulsion fans. The study proposed power system architectures, investigated electromechanical and solid state circuit breakers, estimated the impact of the system voltage on system mass, and recommended DC bus voltage range. The study assumed an all cryogenic power system. Detailed assumptions within the study include hybrid circuit breakers, a two cryogen system, and supercritical cyrogens. A dynamic model was developed to investigate control and parameter selection.

power↗