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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Impact of K-factor on Short Circuit Program Convergence for Inverter-Based Resources during Faults

Classical short-circuit programs that linearize the power network are no longer applicable for inverter based resources (IBRs), necessitating an iterative approach. Phasor domain programs can model the IBRs using an iterative approach considering nonlinear fault responses. In phasor domain models, the IBR can be modeled as a voltage controlled current source (VCCS) in tabular form with positive, negative, and zero sequence information for balanced and unbalance short-circuit faults. In the VCCS modeling of the IBR, positive and negative incremental reactive current, also known as the k-factor, plays an important role in short circuit program convergence. In this work, a few approaches: conventional VCCS modeling with a k-factor of 2, conventional VCCS modeling with a k-factor of 2 with modified pre-fault voltages, VCCS characteristics based on the power flow solution with a k-factor of 2, and VCCS characteristics based on the power flow solution with a k-factor of 1 are investigated for short circuit program convergence under higher IBR penetration. The IEEE 39 bus New England Test System is taken as the test system, and simulations are carried out in PSS®CAPE 15.0.26 simulation software. Simulation results demonstrate that IBR penetration is higher for the VCCS model, which corresponds to the power flow solution with k-factor 1, compared to other approaches.

42 ENGINEERING↗
NASA NTRS1992

Detection of feed-through faults in CMOS storage elements

In testing sequential circuits, internal faults in the storage elements (SE's) are sometimes modeled as stuck-at faults in the combinational circuits surrounding the SE. The detection of some transistor-level faults that cannot be modeled as stuck-at are considered. These feed-through faults cause the cell to become either data-feed-through, which makes the cell combinational, or clock-feed-through, which causes the clock signal or its complement to appear at the output. Under such faults, the cell does not function as a memory element. Here it is shown that such faults may or may not be detected depending on delays involved. Conditions under which race-ahead occurs are identified.

Al-Assadi, Waleed K.↗
NASA NTRS1982

On testing stuck-open faults in CMOS combinational circuits

Recently it has been found that a class of failure related to a particular technology (CMOS) cannot be modelled as the conventional stuck-at fault model. These failures change the combinational behavior of CMOS logic gates into a sequential one. Such a failure is modelled as a fault, called the Stuck-Open fault (SOP). The object of this paper is to develop a procedure to detect single SOPs in combinational circuits. It is shown, that in general, tests generated for stuck-at faults when applied in a particular sequence will detect all single SOP faults. In case of single redundancy in the network, the SOP fault on the redundant line cannot be detected. When there is reconvergent fan-out in the network, there is a one-one correspondence between the conditions for stuck-at fault and stuck-open fault detectability.

Chandramouli, R.↗
DOE OSTI2023

Simultaneous estimation of multiple eigenvalues with short-depth quantum circuit on early fault-tolerant quantum computers

We introduce a multi-modal, multi-level quantum complex exponential least squares (MM-QCELS) method to simultaneously estimate multiple eigenvalues of a quantum Hamiltonian on early fault-tolerant quantum computers. Our theoretical analysis demonstrates that the algorithm exhibits Heisenberg-limited scaling in terms of circuit depth and total cost. Notably, the proposed quantum circuit utilizes just one ancilla qubit, and with appropriate initial state conditions, it achieves significantly shorter circuit depths compared to circuits based on quantum phase estimation (QPE). Numerical results suggest that compared to QPE, the circuit depth can be reduced by around two orders of magnitude under several settings for estimating ground-state and excited-state energies of certain quantum systems.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1975

Testability enhancement in digital system design

A new way of employing hardware redundancy to reduce the number of tests for fault detection in both combinational and synchronous sequential circuits is investigated. An approach is presented for utilizing systematic redundancy to simplify design work. Models for PLM (programmable logic module) and CMM (controllable memory module) are depicted. Systematic design and detection procedures are described. Using these procedures, an easily testable circuit (for stuck faults) can be designed. In contrast to the earlier results on fault detection in logic circuit, two tests are needed to detect any stuck faults of combinational logic circuit. Four tests are necessary and sufficient to detect any stuck faults of elementary logic gates and the malfunction of flip-flops of synchronous sequential circuit using Delay flip-flops or trigger flip-flops.

Chuang, C. S.↗
DOE OSTI2022

Random Forest Regressor-Based Approach for Detecting Fault Location and Duration in Power Systems

Power system failures or outages due to short-circuits or “faults” can result in long service interruptions leading to significant socio-economic consequences. It is critical for electrical utilities to quickly ascertain fault characteristics, including location, type, and duration, to reduce the service time of an outage. Existing fault detection mechanisms (relays and digital fault recorders) are slow to communicate the fault characteristics upstream to the substations and control centers for action to be taken quickly. Fortunately, due to availability of high-resolution phasor measurement units (PMUs), more event-driven solutions can be captured in real time. In this paper, we propose a data-driven approach for determining fault characteristics using samples of fault trajectories. A random forest regressor (RFR)-based model is used to detect real-time fault location and its duration simultaneously. This model is based on combining multiple uncorrelated trees with state-of-the-art boosting and aggregating techniques in order to obtain robust generalizations and greater accuracy without overfitting or underfitting. Four cases were studied to evaluate the performance of RFR: 1. Detecting fault location (case 1), 2. Predicting fault duration (case 2), 3. Handling missing data (case 3), and 4. Identifying fault location and length in a real-time streaming environment (case 4). A comparative analysis was conducted between the RFR algorithm and state-of-the-art models, including deep neural network, Hoeffding tree, neural network, support vector machine, decision tree, naive Bayesian, and K-nearest neighborhood. Experiments revealed that RFR consistently outperformed the other models in detection accuracy, prediction error, and processing time.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1989

Closure of the Africa-Eurasia-North America plate motion circuit and tectonics of the Gloria fault

The current motions of the African, Eurasian, and North American plates are examined. The problems addressed include whether there is resolvable motion of a Spitsbergen microplate, the direction of motion between the African and North American plates, whether the Gloria fault is an active transform fault, and the implications of plate circuit closures for rates of intraplate deformation. Marine geophysical data and magnetic profiles are used to construct a model which predicts about 4 mm/yr slip across the Azores-Gibraltar Ridge, and west-northwest convergence near Gibraltar. The analyzed data are consistent with a rigid plate model with the Gloria fault being a transform fault.

Argus, Donald F.↗
NASA NTRS2011

Impulse Testing of Corporate-Fed Patch Array Antennas

This paper discusses a novel method for detecting faults in antenna arrays. The method, termed Impulse Testing, was developed for corporate-fed patch arrays where the element is fed by a probe and is shorted at its center. Impulse Testing was devised to supplement conventional microwave measurements in order to quickly verify antenna integrity. The technique relies on exciting each antenna element in turn with a fast pulse (or impulse) that propagates through the feed network to the output port of the antenna. The resulting impulse response is characteristic of the path through the feed network. Using an oscilloscope, a simple amplitude measurement can be made to detect faults. A circuit model of the antenna elements and feed network was constructed to assess various fault scenarios and determine fault-detection thresholds. The experimental setup and impulse measurements for two patch array antennas are presented. Advantages and limitations of the technique are discussed along with applications to other antenna array topologies

antenna array↗
NASA NTRS1995

Electrical short circuit and current overload tests on aircraft wiring

The findings of electrical short circuit and current overload tests performed on commercial aircraft wiring are presented. A series of bench-scale tests were conducted to evaluate circuit breaker response to overcurrent and to determine if the wire showed any visible signs of thermal degradation due to overcurrent. Three types of wire used in commercial aircraft were evaluated: MIL-W-22759/34 (150 C rated), MIL-W-81381/12 (200 C rated), and BMS 1360 (260 C rated). A second series of tests evaluated circuit breaker response to short circuits and ticking faults. These tests were also meant to determine if the three test wires behaved differently under these conditions and if a short circuit or ticking fault could start a fire. It is concluded that circuit breakers provided reliable overcurrent protection. Circuit breakers may not protect wire from ticking faults but can protect wire from direct shorts. These tests indicated that the appearance of a wire subjected to a current that totally degrades the insulation looks identical to a wire subjected to a fire; however the 'fire exposed' conductor was more brittle than the conductor degraded by overcurrent. Preliminary testing indicates that direct short circuits are not likely to start a fire. Preliminary testing indicated that direct short circuits do not erode insulation and conductor to the extent that ticking faults did. Circuit breakers may not safeguard against the ignition of flammable materials by ticking faults. The flammability of materials near ticking faults is far more important than the rating of the wire insulation material.

Cahill, Patricia↗
DOE OSTI2022

A Hybrid DC Fault Primary Protection Algorithm for Multi-Terminal HVdc Systems

Protection against dc faults is one of the main technical hurdles faced when operating converter-based HVdc systems. Protection becomes even more challenging for multi-terminal dc (MTdc) systems with more than two terminals/converter stations. In this paper, a hybrid primary fault detection algorithm for MTdc systems is proposed to detect a broad range of failures. Sensor measurements, i.e., line currents and dc reactor voltages measured at local terminals, are first processed by a top-level context clustering algorithm. For each cluster, the best fault detector is selected among a detector pool according to a rule resulting from a learning algorithm. The detector pool consists of several existing detection algorithms, each performing differently across fault scenarios. The proposed hybrid primary detection algorithm: i) offers superior performance compared to an individual detector through a data-driven approach; ii) detects all major fault types including pole-to-pole (P2P), pole-to-ground (P2G), and external dc faults; iii) identifies faults with various fault locations and impedances; iv) is more robust to noisy sensor measurements compared to existing methods; v) does not require exhaustive simulation and sampling for training the model. Performance and effectiveness of the proposed algorithm are evaluated and verified based on time-domain simulations in the PSCAD/EMTDC software environment. The results confirm satisfactory operation, accuracy, and detection speed of the proposed algorithm under various fault scenarios.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1978

Apparatus including a plurality of spaced transformers for locating short circuits in cables

A cable fault locator is described for sensing faults such as short circuits in power cables. The apparatus includes a plurality of current transformers strategically located along a cable. Trigger circuits are connected to each of the current transformers for placing a resistor in series with a resistive element responsive to an abnormally high current flowing through that portion of the cable. By measuring the voltage drop across the resistive element, the location of the fault can be determined.

Cason, R. L.↗
NASA NTRS1975

The probability of a correct output from a combinational circuit

The paper discusses two methods to evaluate the signal reliability of the output of logical circuits. It is known that faults present in a circuit will not always cause the output of the circuit to be incorrect. The first method evaluates the contribution of each fault to the reliability of the circuit and requires the enumeration of the behavior of each fault in the entire fault set. The use of McCluskey and Clegg's characterization of faulty networks by evaluating the functional equivalence classes of the network is a way to reduce the amount of computation involved. The second method uses a probabilistic model of logical circuits and consists of straightforward operations which can easily be automated. The method also yields the signal reliability and has the capability of very easily specifying the individual fault probabilities of all the circuit lines independently.

Ogus, R. C.↗
DOE OSTI2024

Searching for Grid-Forming Technologies That Do Not Impact Protection Systems: A promising technology

The design of legacy-line protection elements has been guided by the behavior of synchronous machines during faults. Because of the significant field-winding inductance and rotating mass, the magnitude, angular frequency, and phase angle of the back-electromotive force (EMF) voltage waveforms of synchronous machines remain practically constant for several hundreds of milliseconds after a fault occurs. Furthermore this has facilitated the engineering of the memory-polarization technique in mho distance elements, which has been effective for machine-dominant power grids. However, this assumption is no longer held for inverter-based resources (IBRs) because of the lack of field winding and moment of inertia in power electronics devices. Notably, the negative-sequence directional overcurrent protection and the quadrilateral distance elements have been impacted by early IBRs with grid-following (GFL) controls because they did not inject negative-sequence currents during asymmetrical faults.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2021

Information Leakage Analysis using a Co-design-Based Fault Injection Technique on a RISC-V Microprocessor

The RISC-V instruction set architecture open licensing policy has spawned a hive of development activity, making a range of implementations publicly available. The environments in which RISC-V operates have expanded correspondingly, driving the need for a generalized approach to evaluating the reliability of RISC-V implementations under adverse operating conditions or after normal wear-out periods. Fault injection (FI) refers to the process of changing the state of registers or wires, either permanently or momentarily, and then observing execution behavior. The analysis provides insight into the development of countermeasures that protect against the leakage or corruption of sensitive information which might occur because of unexpected execution behavior. In this paper, we develop a hardware-software co-design architecture that enables fast, configurable fault emulation and utilize it for information leakage and data corruption analysis. Modern System-on-chip FPGAs enable building an evaluation platform where control elements run on a processor(s) (PS) simultaneously with the target design running in the programmable logic (PL). Software components of the FI system introduce faults and report execution behavior. A pair of RISC-V FI-instrumented implementations are created and configured to execute the Advanced Encryption Standard and Twister algorithms. Key and plaintext information leakage and degraded pseudo-random sequences are both observed in the output for a subset of the emulated faults.

42 ENGINEERING↗
NASA NTRS1980

Detector verifier for circuit analyzers

Economical tool checks operation of automatic circuit analyzer. Each loop is addressed directly from analyzer console by switching internal analyzer bridge to resistance equal that of connecting cable plus specified limiting test value. Procedure verifies whether detected faults in circuit under test are actually due to analyzer malfunction. Standard-length universal test cables make it possible to shift detector tool from cable to cable without resistance compensation.

Pope, D. L.↗
NASA NTRS1991

High reliability megawatt transformer/rectifier

The goal of the two phase program is to develop the technology and design and fabricate ultralightweight high reliability DC to DC converters for space power applications. The converters will operate from a 5000 V dc source and deliver 1 MW of power at 100 kV dc. The power weight density goal is 0.1 kg/kW. The cycle to cycle voltage stability goals was + or - 1 percent RMS. The converter is to operate at an ambient temperature of -40 C with 16 minute power pulses and one hour off time. The uniqueness of the design in Phase 1 resided in the dc switching array which operates the converter at 20 kHz using Hollotron plasma switches along with a specially designed low loss, low leakage inductance and a light weight high voltage transformer. This approach reduced considerably the number of components in the converter thereby increasing the system reliability. To achieve an optimum transformer for this application, the design uses four 25 kV secondary windings to produce the 100 kV dc output, thus reducing the transformer leakage inductance, and the ac voltage stresses. A specially designed insulation system improves the high voltage dielectric withstanding ability and reduces the insulation path thickness thereby reducing the component weight. Tradeoff studies and tests conducted on scaled-down model circuits and using representative coil insulation paths have verified the calculated transformer wave shape parameters and the insulation system safety. In Phase 1 of the program a converter design approach was developed and a preliminary transformer design was completed. A fault control circuit was designed and a thermal profile of the converter was also developed.

Zwass, Samuel↗