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NASA NTRS1996

System Guidelines for EMC Safety-Critical Circuits: Design, Selection, and Margin Demonstration

Demonstration of required safety margins on critical electrical/electronic circuits in large complex systems has become an implementation and cost problem. These margins are the difference between the activation level of the circuit and the electrical noise on the circuit in the actual operating environment. This document discusses the origin of the requirement and gives a detailed process flow for the identification of the system electromagnetic compatibility (EMC) critical circuit list. The process flow discusses the roles of engineering disciplines such as systems engineering, safety, and EMC. Design and analysis guidelines are provided to assist the designer in assuring the system design has a high probability of meeting the margin requirements. Examples of approaches used on actual programs (Skylab and Space Shuttle Solid Rocket Booster) are provided to show how variations of the approach can be used successfully.

Lawton, R. M.↗

NASA NTRS1983

Automatic hardware synthesis

The complexity of the circuit that can fit on an integrated circuit (IC) chip has reached the level of a million transistors with the advent of Very-Large-Scale Integration (VLSI). Several automatic synthesis systems have evolved that 'aid' the human designer in managing this complexity. This paper surveys such efforts. The synthesis is viewed as the process of transforming a high-level design specification into a lower level design specification that includes more structural details, leading to the physical design of the IC. The characteristics of ten automatic synthesis systems are summarized.

Shiva, S. G.↗

NASA NTRS1999

Numerical Prediction of Transient Axial Thrust and Internal Flows in a Rocket Engine Turbopump

This paper presents the application of the Generalized Fluid System Simulation Program (GFSSP) to model the time-dependent flow in a complex secondary flow circuit of the turbopump of the Fastrac engine currently under development at Marshall Space Flight Center. GFSSP is a general purpose computer program for analyzing steady-state and time-dependant flowrates, pressures, temperatures, and concentrations in a complex flow network. The program employs a finite volume formulation of mass, momentum and energy conservation equations in conjunction with the thermodynamic equation of state of real fluids. GFSSP was used to calculate the axial thrust and internal flow distribution of the Fastrac engine turbopump during the start and shut down transients. The models discussed in this paper use boundary conditions that were extracted from turbopump test data. The GFSSP predicted turbopump secondary flow passage pressures and temperatures were compared with actual measured values.

VanHooser, Katherine↗

NASA NTRS1998

Flow Simulation in Secondary Flow Passages of a Rocket Engine Turbopump

This paper presents application of a Generalized Fluid System Simulation Program (GFSSP) to model fluid flow in a very complex secondary flow circuit of a rocket engine turbopump, SIMPLEX. SIMPLEX was a low cost turbopump designed, manufactured and tested to demonstrate the ability to reduce the overall cost and design cycle time of turbomachinery. GFSSP is a general purpose computer program for analyzing flowrate, pressure, temperature and concentration distribution in a complex flow network. The program employs a finite volume formulation of mass, momentum and energy conservation equations in conjunction with thermodynamic equation of state of a real fluid. The secondary flow passages modeled include flow between the impeller shroud and housing, impeller back face and housing, flow through labyrinth seal and bearing, return line flow to inducer and flow adjacent to front and back face of the turbine. Axial load on the bearing are calculated from the predicted pressure on all axial faces of the rotor. The predicted pressure and temperature distributions compared well with the test data.

Schallhorn, Paul↗

NASA NTRS2003

120-GHz HEMT Oscillator With Surface-Wave-Assisted Antenna

Two monolithic microwave integrated circuits (MMICs) have been designed and built to function together as a source of electromagnetic radiation at a frequency of 120 GHz. One of the MMICs is an oscillator and is the highest-power 120-GHz oscillator reported thus far in the literature. The other MMIC is an end-fire antenna that radiates the oscillator signal. Although these MMICs were constructed as separate units and electrically connected with wire bonds, future oscillator/ antenna combinations could readily be fabricated as monolithic integrated units. Such units could be used as relatively high-power solid-state microwave sources in diverse applications that include automotive radar, imaging, scientific instrumentation, communications, and radio astronomy. As such, these units would be attractive alternatives to vacuum-tube oscillators, which are still used to obtain acceptably high power in the frequency range of interest. The oscillator (see figure) includes a high-electron-mobility transistor (HEMT), with gate-periphery dimensions of 4 by 37 m, in a common-source configuration. The series feedback element of the oscillator is a grounded coplanar waveguide (CPW) at the source. The HEMT is biased for class-A operation (meaning that current is conducted throughout the oscillation cycle) to maximize the output power of the oscillator. Input and output impedance-matching circuit elements are designed to maximize output power and to establish the conditions needed for oscillation. The design of the antenna takes advantage of surface waves, which, heretofore, have been regarded as highly disadvantageous because they can leak power and degrade the performances of antennas that have not been designed to exploit them. Measures taken to suppress surface waves have included complex machining of circuit substrates and addition of separate substrates. These measures are difficult to implement in standard MMIC fabrication processes. In contrast, because the design of the present antenna eliminates the need to suppress surface waves, the fabrication of the antenna is fully compatible with standard MMIC fabrication processes.

Samoska, Lorene↗

NASA NTRS2004

Design Space Issues for Intrinsic Evolvable Hardware

This paper discuss the problem of increased programming time for intrinsic evolvable hardware (EHW) as the complexity of the circuit grows. We develop equations for the size of the population, n, and the number of generations required for the population to converge, ngen, based on L, the length of the programming string. We show that the processing time of the computer becomes negligible for intrinsic EHW since the selection/crossover/mutation steps are only done once per generation, suggesting there is room for use of more complex evolutionary algorithms m intrinsic EHW. F i y , we review the state of the practice and discuss the notion of a system design approach for intrinsic EHW.

Hereford, James↗

NASA NTRS2008

Split-Block Waveguide Polarization Twist for 220 to 325 GHz

A split-block waveguide circuit that rotates polarization by 90 has been designed with WR-3 input and output waveguides, which are rectangular waveguides used for a nominal frequency range of 220 to 325 GHz. Heretofore, twisted rectangular waveguides equipped with flanges at the input and output have been the standard means of rotating the polarizations of guided microwave signals. However, the fabrication and assembly of such components become difficult at high frequency due to decreasing wavelength, such that twisted rectangular waveguides become impractical at frequencies above a few hundred gigahertz. Conventional twisted rectangular waveguides are also not amenable to integration into highly miniaturized subassemblies of advanced millimeter- and submillimeter-wave detector arrays now undergoing development. In contrast, the present polarization- rotating waveguide can readily be incorporated into complex integrated waveguide circuits such as miniaturized detector arrays fabricated by either conventional end milling of metal blocks or by deep reactive ion etching of silicon blocks. Moreover, the present split-block design can be scaled up in frequency to at least 5 THz. The main step in fabricating a splitblock polarization-rotating waveguide of the present design is to cut channels having special asymmetrically shaped steps into mating upper and lower blocks (see Figure 1). The dimensions of the steps are chosen to be consistent with the WR-3 waveguide cross section, which is 0.864 by 0.432 mm. The channels are characterized by varying widths with constant depths of 0.432, 0.324, and 0.216 mm and by relatively large corner radii to facilitate fabrication. The steps effect both a geometric transition and the corresponding impedance-matched electromagnetic-polarization transition between (1) a WR-3 rectangular waveguide oriented with the electric field vector normal to the block mating surfaces and (2) a corresponding WR-3 waveguide oriented with its electric field vector parallel to the mating surfaces of the blocks. A prototype has been built and tested. Figure 2 presents test results indicative of good performance over nearly the entire WR-3 waveguide frequency band.

Ward, John↗

NASA NTRS1996

Good trellises for IC implementation of viterbi decoders for linear block codes

This paper investigates trellis structures of linear block codes for the IC (integrated circuit) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called ACS-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the VLSI complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a non-minimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.

Moorthy, H. T.↗

NASA NTRS1996

Good trellises for IC implementation of viterbi decoders for linear block codes

Lin, Shu↗

NASA NTRS1997

Good Trellises for IC Implementation of Viterbi Decoders for Linear Block Codes

This paper investigates trellis structures of linear block codes for the integrated circuit (IC) implementation of Viterbi decoders capable of achieving high decoding speed while satisfying a constraint on the structural complexity of the trellis in terms of the maximum number of states at any particular depth. Only uniform sectionalizations of the code trellis diagram are considered. An upper-bound on the number of parallel and structurally identical (or isomorphic) subtrellises in a proper trellis for a code without exceeding the maximum state complexity of the minimal trellis of the code is first derived. Parallel structures of trellises with various section lengths for binary BCH and Reed-Muller (RM) codes of lengths 32 and 64 are analyzed. Next, the complexity of IC implementation of a Viterbi decoder based on an L-section trellis diagram for a code is investigated. A structural property of a Viterbi decoder called add-compare-select (ACS)-connectivity which is related to state connectivity is introduced. This parameter affects the complexity of wire-routing (interconnections within the IC). The effect of five parameters namely: (1) effective computational complexity; (2) complexity of the ACS-circuit; (3) traceback complexity; (4) ACS-connectivity; and (5) branch complexity of a trellis diagram on the very large scale integration (VISI) complexity of a Viterbi decoder is investigated. It is shown that an IC implementation of a Viterbi decoder based on a nonminimal trellis requires less area and is capable of operation at higher speed than one based on the minimal trellis when the commonly used ACS-array architecture is considered.

Moorthy, Hari T.↗

NASA NTRS1970

Fast multipliers

Parallel multiplier design with carry-save scheme and constructed from series integrated circuits, discussing speed, complexity and cost

Habibi, A.↗

NASA NTRS1978

CMOS bulk-metal design handbook

User's guide describes techniques for generating precision mask artwork for complex CMOS integrated circuits, starting from logic diagram. Techniques are based on standard-cell approach. Guide also includes user guidelines for designing efficient CMOS arrays.

Edge, T. M.↗

NASA NTRS1981

Ignitor plug erosion and arc initiation processes in a one-millipound pulsed plasma thruster

The results are presented of a one-millipound pulsed plasma ignition system study. The preliminary data indicate that inductively coupling the ignition plug cathode to the thruster cathode is more beneficial to ignitor plug longevity than resistive coupling. These benefits arise from the ability of the coupling conductor to control the build-up of a carbonaceous deposit on the plug face. The deposit build-up is a strong function of the peak coupling current experienced during thruster operation. The relationship between the ignitor plug discharge and thruster discharge is shown to be very complex with equivalent circuit elements which are dynamic in nature. A preliminary representation of this equivalent circuit is developed.

Aston, G.↗

NASA NTRS2001

Whole-cell biocomputing

The ability to manipulate systems on the molecular scale naturally leads to speculation about the rational design of molecular-scale machines. Cells might be the ultimate molecular-scale machines and our ability to engineer them is relatively advanced when compared with our ability to control the synthesis and direct the assembly of man-made materials. Indeed, engineered whole cells deployed in biosensors can be considered one of the practical successes of molecular-scale devices. However, these devices explore only a small portion of cellular functionality. Individual cells or self-organized groups of cells perform extremely complex functions that include sensing, communication, navigation, cooperation and even fabrication of synthetic nanoscopic materials. In natural systems, these capabilities are controlled by complex genetic regulatory circuits, which are only partially understood and not readily accessible for use in engineered systems. Here, we focus on efforts to mimic the functionality of man-made information-processing systems within whole cells.

Non-NASA Center↗

NASA NTRS2007

A CMOS Imager with Focal Plane Compression using Predictive Coding

This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

Leon-Salas, Walter D.↗

NASA NTRS2019

Design of Experiment for the Measurement of Aerosol Droplet Size Distribution of Temperature-Controlled Thermally Atomized Printed Electronic Inks

In-Space Manufacturing (ISM) centers around NASA’s growing need and ability to produce space technologies on demand in space. As the future of long term presence in space and deep space exploration approach, fundamental questions of our dependence on earth resupply to Low Earth Orbit (LEO) remain unanswered. ISM is leading various effort to evaluate the feasibility of producing essential spares and redundant parts on demand to enable a sustainable space-based supply chain model for part resupply. Among the parts and systems being considered, Avionics form the neural network of modern day aircraft and space vehicles providing a wealth of information ranging from Guidance, Navigation, and Control (GN&C) systems to on board Environmental Control and Life Support (ECLS) systems. Recent advances in the use of Aerosol Jet Technology to print Avionics components ranging from electrical traces on a circuit board to complex transistors and sensors raise the possibility of using such technology to reproduce or recreate electronic parts on demand with the help of custom electronics 3D printers. The challenge herein lies within the ability of such printers to generate and deposit an aerosol of electronic material utilizing processes independent of or enhanced by gravity to ensure controllably identical or improved behavior of the aerosol in an International Space Station (ISS) laboratory and on the ground. The behavior as well as the hazards and properties associated with such aerosols in a microgravity environment must be understood well in order to merit a feasible approach to utilizing them for manufacturing in space. In this report, we outline the experimental setup of a modified conventional vaping device to be used as the ideal gravity independent thermal atomization mechanism to generate aerosol. Our objective is to identify the ideal mass, density, and volume of our aerosolized droplets of ink to conclude that there exist a threshold of aerosolized ink droplet sizes that are indeed independent of the effects of gravity and remain stable after atomization. We use a Malvern Spraytec® Spray Particle Size Analyzer to perform real-time laser diffraction measurement of our ink droplets during atomization. The droplet size between conductive ink, dielectric ink and vegetable glycerin have been measured and contrasted. Furthermore, the mechanism of thermal atomization versus traditional pneumatic and ultrasonic atomization for operation in microgravity have been explored.

Wu, Chih-Hao↗

NASA NTRS1993

Delay analysis of combinations of pass transistors and classical logic gates

Combinations of pass transistors and logic gates driving nonlinear capacitive loads are analyzed for the presence of characteristics that will permit easier and more accurate digital logic simulation. Accurate time delay models are developed by studying the nature of the response of simplified circuit models to variations of input waveform rise and fall times and output loading. The nonlinear effects of the CMOS logic devices are minimized to permit easier interpretation of the influence of nonlinear capacitive loads. The performance of a CMOS inverter with a complex nonlinear load consisting of a pass transistor that separates a range of capacitances is compared to the same inverter circuit with a linear capacitive load to develop an understanding of the unique requirements of modeling a nonlinear system. Several methods of modeling the delay of CMOS circuits are reviewed, and a multi-parameter linear model is described. General guidelines for designing CMOS circuits with complex load circuits are developed, emphasizing that the circuit output rise delays and fall delays must be separately analyzed.

Gibson, Jonathan S.↗

NASA NTRS1986

Total-dose radiation effects data for semiconductor devices. 1985 supplement. Volume 2, part A

Steady-state, total-dose radiation test data, are provided in graphic format for use by electronic designers and other personnel using semiconductor devices in a radiation environment. The data were generated by JPL for various NASA space programs. This volume provides data on integrated circuits. The data are presented in graphic, tabular, and/or narrative format, depending on the complexity of the integrated circuit. Most tests were done using the JPL or Boeing electron accelerator (Dynamitron) which provides a steady-state 2.5 MeV electron beam. However, some radiation exposures were made with a Cobalt-60 gamma ray source, the results of which should be regarded as only an approximate measure of the radiation damage that would be incurred by an equivalent electron dose.

Martin, K. E.↗