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Array of tiny probes tests complex printed circuit boards prior to mounting of microcircuit chips and other active and passive components. Insertion and alignment of board, performance of entire computer-controlled test, and printing of results requires about a minute; performed manually same tests require as much as 30 hours.
Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.
Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.
Unlike circuit parameter and sizing optimizations, the automated design of analog circuit topologies poses significant challenges for learning-based approaches. One challenge arises from the combinatorial growth of the topology space with circuit size, which limits the topology optimization efficiency. Moreover, traditional circuit evaluation methods are time-consuming, while the presence of data discontinuity in the topology space makes the accurate prediction of circuit performance exceptionally difficult for unseen topologies. To tackle these challenges, we design a novel Graph-Transformer-based Network (GTN) as the surrogate model for circuit evaluation, offering a substantial acceleration in the speed of circuit topology optimization without sacrificing performance. Our GTN model architecture is designed to embed voltage changes in circuit loops and current flows in connected devices, enabling accurate performance predictions for circuits with unseen topologies. To address the cold start problem when scaling GTN to large-scale circuits, we further introduce a curriculum learning strategy that progressively trains GTN from small-scale to large-scale circuits. This approach enables the model to first learn fundamental physical principles from simpler topologies and gradually adapt to complex configurations, effectively bridging the circuit complexity gap and improving prediction accuracy. Taking the power converter circuit design as an experimental task, our GTN model significantly outperforms an analytical approach and baseline methods directly utilizing graph neural networks. Furthermore, GTN achieves less than 5% relative error and 196× speed-up compared with high-fidelity simulation. Notably, our GTN surrogate model empowers an automatic circuit design framework to discover circuits of comparable quality to those identified through high-fidelity simulation while reducing the time required by up to 98.2%. With curriculum learning, the enhanced GTN achieves a 51% improvement for performance prediction of large-scale circuits compared to the GTN model without this strategy. These advancements establish GTN as a scalable framework for automated analog circuit design across varying circuit complexity levels.
We present the conceptual design of the modular detector and readout system for the Cosmic Microwave Background – Stage four (CMB-S4) ground-based survey experiment. CMB-S4 will map the cosmic microwave background (CMB) and the millimeter-wave sky to unprecedented sensitivity, using 500,000 superconducting detectors observing from Chile and Antarctica to map over 60% of the sky. The fundamental building block of the detector and readout system is a detector module package operated at 100 mK, which is connected to a readout and amplification chain that carries signals out to room temperature. It uses arrays of feedhorn-coupled orthomode transducers (OMT) that collect optical power from the sky onto dc-voltage-biased transition-edge sensor (TES) bolometers. The resulting current signal in the TESs is then amplified by a two-stage cryogenic Superconducting Quantum Interference Device (SQUID) system with a time-division multiplexer to reduce wire count, and matching room-temperature electronics to condition and transmit signals to the data acquisition system. Sensitivity and systematics requirements are being developed for the detector and readout system over wide range of observing bands (20 to 300 GHz) and optical powers to accomplish CMB-S4’s science goals. While the design incorporates the successes of previous generations of CMB instruments, CMB-S4 requires an order of magnitude more detectors than any prior experiment. This requires fabrication of complex superconducting circuits on over 10 m2 of silicon, as well as significant amounts of precision wiring, assembly and cryogenic testing
A key question in origin-of-life research is how primitive life or life-like systems obtained reusable and reprogrammable machinery of processing information to respond to various environmental and internal stimuli. One strategy to approach this question is to view living systems as universal chemical computers. This approach focuses upon uncovering how reusable and reprogrammable chemical NOT, AND, and OR logic gates could appear under prebiotically possible scenarios where simple chemicals and second- or lower-order reactions are more frequent than macromolecules and higher-order reactions. In this article, we theoretically model two generic mechanisms of forming Boolean gates based on geochemically plausible reaction systems that could have preceded complex biopolymers. The mechanisms exploit simple bistable autocatalytic systems to encode binary variables and use heterogeneous dilution rates to differentially activate or deactivate autocatalysis in different reactors. We found that NOT, AND, and OR gates, as well as more complex logic circuits, can spontaneously arise from connected, well-mixed flow reactors based on (i) catalysis by a heterodimer between mutually inhibitory autocatalysts or (ii) selectively permeable tunnels connecting reactors. Our results suggest that simple machinery can support the prebiotic emergence of complex chemical logic circuits and provide new guides for experimentally actualizing chemical computation.
Abstract The variational quantum eigensolver (VQE) is a method that uses a hybrid quantum-classical computational approach to find eigenvalues of a Hamiltonian. VQE has been proposed as an alternative to fully quantum algorithms such as quantum phase estimation (QPE) because fully quantum algorithms require quantum hardware that will not be accessible in the near future. VQE has been successfully applied to solve the electronic Schrödinger equation for a variety of small molecules. However, the scalability of this method is limited by two factors: the complexity of the quantum circuits and the complexity of the classical optimization problem. Both of these factors are affected by the choice of the variational ansatz used to represent the trial wave function. Hence, the construction of an efficient ansatz is an active area of research. Put another way, modern quantum computers are not capable of executing deep quantum circuits produced by using currently available ansatzes for problems that map onto more than several qubits. In this review, we present recent developments in the field of designing efficient ansatzes that fall into two categories—chemistry–inspired and hardware–efficient—that produce quantum circuits that are easier to run on modern hardware. We discuss the shortfalls of ansatzes originally formulated for VQE simulations, how they are addressed in more sophisticated methods, and the potential ways for further improvements.
Noise lower than with sliprings. Rotary transformer transfers electric power across rotary joint. No wearing contacts, no contact noise, and no contamination from lubricants or wear debris. Because additional inductor not required, size and complexity of circuit reduced considerably.
Cryogenic Process Design Kits (PDKs) are an indispensable tool in the design of complex integrated circuits across a wide spectrum of applications, from noble element detectors to Quantum Information Science, Superconducting Nanowire Single Photon Detectors (SNSPDs), and precision atomic clocks. The development of PDK-compatible SPICE models is a complex endeavor requiring test structures, measurements, model extraction and fitting. We will present the cryogenic modeling and development of a cryo-PDK for a 22nm FDSOI CMOS process for operation at 3.8 Kelvin.
The 40- by 80-foot wind tunnel circuit of the National Full-Scale Aerodynamic Complex (NFAC) has recently undergone major modifications and subsequently completed final acceptance testing. The initial testing and calibration of the wind tunnel are described and in many cases these results are compared with predictions derived from model tests and theoretical analyses. The wind tunnel meets or exceeds essentially all performance objectives. The facility runs smoothly and routinely at its maximum test-section velocity of 300 knots (Mach number = 0.45). An effective cooling air exchange system enables the wind tunnel to operate indefinitely at this maximum power condition. Throughout the operating envelope of the wind tunnel the test-section dynamic pressure is uniform to within + or - 0.5 deg, and the axial component of turbulence is generally less than 0.5 percent. Acoustic measurements indicate that, due to the low noise fans and acoustic treatment in the wind-tunnel circuit and test section, the background noise level in the test section is comparable to other large-scale acoustic wind tunnels in the United States and abroad.
The Component-Level Electronic-Assembly Repair (CLEAR) project at the NASA Glenn Research Center is aimed at developing technologies that will enable space-flight crews to perform in situ component-level repair of electronics on Moon and Mars outposts, where there is no existing infrastructure for logistics spares. These technologies must provide effective repair capabilities yet meet the payload and operational constraints of space facilities. Effective repair depends on a diagnostic capability that is versatile but easy to use by crew members that have limited training in electronics. CLEAR studied two techniques that involve extensive precharacterization of "known good" circuits to produce graphical signatures that provide an easy-to-use comparison method to quickly identify faulty components. Analog Signature Analysis (ASA) allows relatively rapid diagnostics of complex electronics by technicians with limited experience. Because of frequency limits and the growing dependence on broadband technologies, ASA must be augmented with other capabilities. To meet this challenge while preserving ease of use, CLEAR proposed an alternative called Complex Signature Analysis (CSA). Tests of ASA and CSA were used to compare capabilities and to determine if the techniques provided an overlapping or complementary capability. The results showed that the methods are complementary.
The accuracy of high-speed wafer-level measurements on digital IC's is limited by the probe interface. This limitation strongly encourages the use of built-in on-chip test hardware to reduce the number of critical off-chip high-speed interfaces. A novel synchronous propagation delay test structure is described which will provide accurate parametric data under typical automatic test conditions. Built-in test features added to complex combinational circuits are shown which are useful for delay measurement and which reduce the total number of high-speed I/O connections while still providing acceptable fault coverage in many cases.
Suppressing errors is the central challenge for useful quantum computing, requiring quantum error correction (QEC) for large-scale processing. However, the overhead in the realization of error-corrected ‘logical’ qubits, in which information is encoded across many physical qubits for redundancy, poses substantial challenges to large-scale logical quantum computing. Here we report the realization of a programmable quantum processor based on encoded logical qubits operating with up to 280 physical qubits. Using logical-level control and a zoned architecture in reconfigurable neutral-atom arrays, our system combines high two-qubit gate fidelities, arbitrary connectivity, as well as fully programmable single-qubit rotations and mid-circuit readout. Operating this logical processor with various types of encoding, we demonstrate improvement of a two-qubit logic gate by scaling surface-code distance from d = 3 to d = 7, preparation of colour-code qubits with break-even fidelities, fault-tolerant creation of logical Greenberger–Horne–Zeilinger (GHZ) states and feedforward entanglement teleportation, as well as operation of 40 colour-code qubits. Finally, using 3D [[8,3,2]] code blocks, we realize computationally complex sampling circuits with up to 48 logical qubits entangled with hypercube connectivity with 228 logical two-qubit gates and 48 logical CCZ gates. We find that this logical encoding substantially improves algorithmic performance with error detection, outperforming physical-qubit fidelities at both cross-entropy benchmarking and quantum simulations of fast scrambling. These results herald the advent of early error-corrected quantum computation and chart a path towards large-scale logical processors.
Silicon-carbide based, multi-level converters with dual-active-bridge (DAB) are getting attention for medium voltage, direct grid-connected, utility-scale photovoltaic (PV) applications due to their higher efficiency and power density. To de-risk complex control development for these high-voltage and high-power inverters, hardware-in-the-loop techniques are often required. Due to the high switching frequency and the large number of power electronic switches, off-the-shelf, real-time simulation tools are not yet fully developed for this application, even with FPGA-based simulators. To address this, a new co-simulation approach in FPGA is presented that utilizes Time-Stamped Bridge (TSB) for the higher frequency converters along with detailed fixed conductance based discrete device simulation of the rest of the circuit. A complex DAB-based PV converter with maximum switching frequency of 50 kHz is successfully simulated in real-time in the FPGA and the results are compared with offline simulation results. A controller hardware-in-the-loop (CHIL) platform is developed to demonstrate real-time, closed-loop test results for this DAB-based PV converter.
An adiabatic resonator, an adiabatic oscillator, and an adiabatic oscillator system are disclosed. An adiabatic system is one that ideally transfers no heat outside of the system, thereby reducing the required operating power. The adiabatic resonator, which includes a plurality of tank circuits, acts as an energy reservoir, the missing aspect of previously attempted adiabatic computational systems. By using the adiabatic resonator as a feedback element with an amplifier, an adiabatic oscillator is formed. An adiabatic oscillator system is formed with a primary adiabatic oscillator feeding a plurality of secondary adiabatic oscillators. In this manner, the adiabatic oscillator system may be used to generate the multiple clock signals required of adiabatic computational logic elements, such as Split-level Charge Recovery Logic and 2-Level Adiabatic Logic. The adiabatic oscillator system stores enough energy to drive many individual adiabatic computational logic elements, permitting implementation of complex logic circuits.
Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.
This report describes the development of a tunable electromechanical Helmholtz resonator (EMHR) for engine nacelles using smart materials technology. This effort addresses both near-term and long-term goals for tunable electromechanical acoustic liner technology for the Quiet Aircraft Technology (QAT) Program. Analytical models, i.e. lumped element model (LEM) and transfer matrix (TM) representation of the EMHR, have been developed to predict the acoustic behavior of the EMHR. The models have been implemented in a MATLAB program and used to compare with measurement results. Moreover, the prediction performance of models is further improved with the aid of parameter extraction of the piezoelectric backplate. The EMHR has been experimentally investigated using standard two-microphone method (TMM). The measurement results validated both the LEM and TM models of the EMHR. Good agreement between predicted and measured impedance is obtained. Short- and open circuit loads define the limits of the tuning range using resistive and capacitive loads. There is approximately a 9% tuning limit under these conditions for the non-optimized resonator configuration studied. Inductive shunt loads result in a 3 degree-of-freedom DOF) system and an enhanced tuning range of over 20% that is not restricted by the short- and open-circuit limits. Damping coefficient ' measurements for piezoelectric backplates in a vacuum chamber are also performed and indicate that the damping is dominated by the structural damping losses, such as compliant boundaries, and other intrinsic loss mechanisms. Based on models of the EMHR, a Pareto optimization design of the EMHR has been performed for the EMHR with non-inductive loads. The EMHR with non-inductive loads is a 2DOF system with two resonant fiequencies. The tuning ranges of the two resonant frequencies of the EMHR with non-inductive loads cannot be optimized simultaneously; a trade-off (i.e., a Pareto solution) must be reached. The Pareto solution provides the information for a designer that shows how design trade-offs can be used to satisfy specific design requirements. The optimization design of the EMHR with inductive loads aims at optimal tuning of these three resonant fiequencies. The results indicate that it is possible to keep the acoustic reactance of the resonator close to a constant over a given frequency range. An effort to mimic the second layer of the NASA 2DOF liner using a piezoelectric composite diaphragm has been made. The optimal acoustic reactance of the second layer of the NASA 2DOF liner is achieved using a thin PVDF composite diaphragm, but matching the acoustic resistance requires further investigation. Acoustic energy harvesting is achieved by connecting the EMHR to an energy reclamation circuit that converts the ac voltage signal across the piezoceramic to a conditioned dc signal. Energy harvesting experiment yields 16 m W continuous power for an incident SPL of 153 dB. Such a level is sufficient to power a variety of low power electronic devices. Finally, technology transfer has been achieved by converting the original NASA ZKTL FORTRAN code to a MATLAB code while incorporating the models of the EMHR. Initial studies indicate that the EMHR is a promising technology that may enable lowpower, light weight, tunable engine nacelle liners. This technology, however, is very immature, and additional developments are required. Recommendations for future work include testing of sample EMHR liner designs in NASA Langley s normal incidence dual-waveguide and the grazing-incidence flow facility to evaluating both the impedance characteristics as well as the energy reclamation abilities. Additional design work is required for more complex tuning circuits with greater performance. Poor electromechanical coupling limited the electromechanical tuning capabilities of the proof of concept EMHR. Different materials than those studies and perhaps novel composite material systems may dramatically improvehe electromechanical coupling. Such improvements are essential to improved mimicking of existing double layer liners.
Quantum Phase Estimation (QPE) is a cardinal algorithm in quantum computing that plays a crucial role in various applications, including cryptography, molecular simulation, and solving systems of linear equations. However, the standard implementation of QPE faces challenges related to time complexity and circuit depth, which limit its practicality for large-scale computations. We introduce LuGo, a novel framework designed to enhance the performance of QPE by reducing circuit duplication, as well as using parallelization techniques to achieve faster generation of the QPE circuit and gate reduction. We validate the effectiveness of our framework by generating quantum linear solver circuits, which require both QPE and inverse QPE, to solve linear systems of equations. LuGo achieves significant improvements in both computational efficiency and hardware requirements without compromising on accuracy. Compared to a standard QPE implementation, LuGo reduces time consumption to generate a circuit that solves a 2 6 × 2 6 system matrix by a factor of 50.68 and over 31× reduction of quantum gates and circuit depth, with no fidelity loss on an ideal quantum simulator. Furthermore, we demonstrated the versatility and scalability of LuGo enabled HHL algorithm by simulating a canonical Hele-Shaw fluid problem using a quantum simulator. With these advantages, LuGo paves the way for more efficient implementations of QPE, enabling broader applications across several quantum computing domains.